foxBMS  1.5.0
The foxBMS Battery Management System API Documentation
dma.c
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41 
42 /**
43  * @file dma.c
44  * @author foxBMS Team
45  * @date 2019-12-12 (date of creation)
46  * @updated 2023-02-03 (date of last update)
47  * @version v1.5.0
48  * @ingroup DRIVERS
49  * @prefix DMA
50  *
51  * @brief Driver for the DMA module.
52  *
53  */
54 
55 /*========== Includes =======================================================*/
56 #include "dma.h"
57 
58 #include "afe_dma.h"
59 #include "ftask.h"
60 #include "i2c.h"
61 #include "spi.h"
62 
63 #include <stdint.h>
64 
65 /*========== Macros and Definitions =========================================*/
66 
67 /*========== Static Constant and Variable Definitions =======================*/
68 
69 /*========== Extern Constant and Variable Definitions =======================*/
70 
71 /*========== Static Function Prototypes =====================================*/
72 
73 /*========== Static Function Implementations ================================*/
74 
75 /*========== Extern Function Implementations ================================*/
76 
77 void DMA_Initialize(void) {
78  /* DMA control packets configuration for SPI */
79  g_dmaCTRL dma_controlPacketSpiTx = {
80  .SADD = 0u, /* source address */
81  .DADD = 0u, /* destination address */
82  .CHCTRL = 0u, /* channel chain control */
83  .FRCNT = 0u, /* frame count */
84  .ELCNT = 1u, /* element count */
85  .ELDOFFSET = 0u, /* element destination offset */
86  .ELSOFFSET = 0u, /* element destination offset */
87  .FRDOFFSET = 0u, /* frame destination offset */
88  .FRSOFFSET = 0u, /* frame destination offset */
89  .PORTASGN = (uint32_t)PORTA_READ_PORTB_WRITE, /* port assignment */
90  .RDSIZE = (uint32_t)ACCESS_16_BIT, /* read size */
91  .WRSIZE = (uint32_t)ACCESS_16_BIT, /* write size */
92  .TTYPE = (uint32_t)FRAME_TRANSFER, /* transfer type */
93  .ADDMODERD = (uint32_t)ADDR_INC1, /* address mode read */
94  .ADDMODEWR = (uint32_t)ADDR_FIXED, /* address mode write */
95  .AUTOINIT = (uint32_t)AUTOINIT_OFF /* autoinit */
96  };
97 
98  g_dmaCTRL dma_controlPacketSpiRx = {
99  .SADD = 0u, /* source address */
100  .DADD = 0u, /* destination address */
101  .CHCTRL = 0u, /* channel chain control */
102  .FRCNT = 0u, /* frame count */
103  .ELCNT = 1u, /* element count */
104  .ELDOFFSET = 0u, /* element destination offset */
105  .ELSOFFSET = 0u, /* element destination offset */
106  .FRDOFFSET = 0u, /* frame destination offset */
107  .FRSOFFSET = 0u, /* frame destination offset */
108  .PORTASGN = (uint32_t)PORTB_READ_PORTA_WRITE, /* port assignment */
109  .RDSIZE = ACCESS_16_BIT, /* read size */
110  .WRSIZE = ACCESS_16_BIT, /* write size */
111  .TTYPE = FRAME_TRANSFER, /* transfer type */
112  .ADDMODERD = ADDR_FIXED, /* address mode read */
113  .ADDMODEWR = ADDR_INC1, /* address mode write */
114  .AUTOINIT = AUTOINIT_OFF /* autoinit */
115  };
116 
117  /* DMA control packets configuration for I2C1 */
118  g_dmaCTRL dma_controlPacketI2cTx = {
119  .SADD = 0u, /* source address */
120  .DADD = 0u, /* destination address */
121  .CHCTRL = 0u, /* channel chain control */
122  .FRCNT = 0u, /* frame count */
123  .ELCNT = 1u, /* element count */
124  .ELDOFFSET = 0u, /* element destination offset */
125  .ELSOFFSET = 0u, /* element destination offset */
126  .FRDOFFSET = 0u, /* frame destination offset */
127  .FRSOFFSET = 0u, /* frame destination offset */
128  .PORTASGN = (uint32_t)PORTA_READ_PORTB_WRITE, /* port assignment */
129  .RDSIZE = (uint32_t)ACCESS_8_BIT, /* read size */
130  .WRSIZE = (uint32_t)ACCESS_8_BIT, /* write size */
131  .TTYPE = (uint32_t)FRAME_TRANSFER, /* transfer type */
132  .ADDMODERD = (uint32_t)ADDR_INC1, /* address mode read */
133  .ADDMODEWR = (uint32_t)ADDR_FIXED, /* address mode write */
134  .AUTOINIT = (uint32_t)AUTOINIT_OFF /* autoinit */
135  };
136 
137  g_dmaCTRL dma_controlPacketI2cRx = {
138  .SADD = 0u, /* source address */
139  .DADD = 0u, /* destination address */
140  .CHCTRL = 0u, /* channel chain control */
141  .FRCNT = 0u, /* frame count */
142  .ELCNT = 1u, /* element count */
143  .ELDOFFSET = 0u, /* element destination offset */
144  .ELSOFFSET = 0u, /* element destination offset */
145  .FRDOFFSET = 0u, /* frame destination offset */
146  .FRSOFFSET = 0u, /* frame destination offset */
147  .PORTASGN = (uint32_t)PORTB_READ_PORTA_WRITE, /* port assignment */
148  .RDSIZE = (uint32_t)ACCESS_8_BIT, /* read size */
149  .WRSIZE = (uint32_t)ACCESS_8_BIT, /* write size */
150  .TTYPE = (uint32_t)FRAME_TRANSFER, /* transfer type */
151  .ADDMODERD = (uint32_t)ADDR_FIXED, /* address mode read */
152  .ADDMODEWR = (uint32_t)ADDR_INC1, /* address mode write */
153  .AUTOINIT = (uint32_t)AUTOINIT_OFF /* autoinit */
154  };
155 
156  dmaEnable();
157 
158  /* Configuration for SPI */
159 
160  for (uint8_t i = 0u; i < DMA_NUMBER_SPI_INTERFACES; i++) {
161  /* assign dma request to Tx channel */
162  dmaReqAssign((dmaChannel_t)dma_spiDmaChannels[i].txChannel, (dmaRequest_t)dma_spiDmaRequests[i].txRequest);
163  /* assign dma request to Rx channel */
164  dmaReqAssign((dmaChannel_t)dma_spiDmaChannels[i].rxChannel, (dmaRequest_t)dma_spiDmaRequests[i].rxRequest);
165 
166  /* Enable Interrupt after reception of data
167  Group A - Interrupts (FTC, LFS, HBC, and BTC) are routed to the ARM CPU
168  User software should configure only Group A interrupts */
169  /**
170  * Use Tx interrupt to transfer last word with CSHOLD = 0
171  * DO NOT ACTIVATE FOR SLAVE SPI NODES (here SPI4 used as slave)
172  * */
173  if (i != SPI_GetSpiIndex(spiREG4)) {
174  dmaEnableInterrupt(
175  (dmaChannel_t)(dmaChannel_t)dma_spiDmaChannels[i].txChannel,
176  (dmaInterrupt_t)BTC,
177  (dmaIntGroup_t)DMA_INTA);
178  }
179  /* Use Rx to determine when SPI over DMA transaction is finished */
180  dmaEnableInterrupt(
181  (dmaChannel_t)(dmaChannel_t)dma_spiDmaChannels[i].rxChannel, (dmaInterrupt_t)BTC, (dmaIntGroup_t)DMA_INTA);
182 
183  dma_controlPacketSpiTx.DADD = (uint32_t)(&(dma_spiInterfaces[i]->DAT1)) + DMA_BIG_ENDIAN_ADDRESS_16BIT;
184  dma_controlPacketSpiRx.SADD = (uint32_t)(&(dma_spiInterfaces[i]->BUF)) + DMA_BIG_ENDIAN_ADDRESS_16BIT;
185 
186  /* Set dma control packet for Tx */
187  dmaSetCtrlPacket((dmaChannel_t)dma_spiDmaChannels[i].txChannel, dma_controlPacketSpiTx);
188 
189  /* Set dma control packet for Rx */
190  dmaSetCtrlPacket((dmaChannel_t)dma_spiDmaChannels[i].rxChannel, dma_controlPacketSpiRx);
191 
192  /* Set the dma channels to trigger on h/w request */
193  dmaSetChEnable((dmaChannel_t)dma_spiDmaChannels[i].txChannel, (dmaTriggerType_t)DMA_HW);
194  dmaSetChEnable((dmaChannel_t)dma_spiDmaChannels[i].rxChannel, (dmaTriggerType_t)DMA_HW);
195  }
196 
197  /* Configuration for I2C1 */
198 
199  /* assign dma request to Tx channel */
200  dmaReqAssign((dmaChannel_t)DMA_CHANNEL_I2C1_TX, (dmaRequest_t)DMA_REQ_LINE_I2C1_TX);
201  /* assign dma request to Rx channel */
202  dmaReqAssign((dmaChannel_t)DMA_CHANNEL_I2C1_RX, (dmaRequest_t)DMA_REQ_LINE_I2C1_RX);
203 
204  /* Enable Interrupt after reception of data
205  Group A - Interrupts (FTC, LFS, HBC, and BTC) are routed to the ARM CPU
206  User software should configure only Group A interrupts */
207  dmaEnableInterrupt((dmaChannel_t)(dmaChannel_t)DMA_CHANNEL_I2C1_TX, (dmaInterrupt_t)BTC, (dmaIntGroup_t)DMA_INTA);
208  dmaEnableInterrupt((dmaChannel_t)(dmaChannel_t)DMA_CHANNEL_I2C1_RX, (dmaInterrupt_t)BTC, (dmaIntGroup_t)DMA_INTA);
209  dmaEnableInterrupt((dmaChannel_t)(dmaChannel_t)DMA_CHANNEL_I2C1_RX, (dmaInterrupt_t)LFS, (dmaIntGroup_t)DMA_INTA);
210 
211  dma_controlPacketI2cTx.DADD = (uint32_t)(&(i2cREG1->DXR)) + DMA_BIG_ENDIAN_ADDRESS_8BIT;
212  dma_controlPacketI2cRx.SADD = (uint32_t)(&(i2cREG1->DRR)) + DMA_BIG_ENDIAN_ADDRESS_8BIT;
213 
214  /* Set dma control packet for Tx */
215  dmaSetCtrlPacket((dmaChannel_t)DMA_CHANNEL_I2C1_TX, dma_controlPacketI2cTx);
216 
217  /* Set dma control packet for Rx */
218  dmaSetCtrlPacket((dmaChannel_t)DMA_CHANNEL_I2C1_RX, dma_controlPacketI2cRx);
219 
220  /* Set the dma channels to trigger on h/w request */
221  dmaSetChEnable((dmaChannel_t)DMA_CHANNEL_I2C1_TX, (dmaTriggerType_t)DMA_HW);
222  dmaSetChEnable((dmaChannel_t)DMA_CHANNEL_I2C1_RX, (dmaTriggerType_t)DMA_HW);
223 
224  /* Configuration for I2C2 */
225 
226  /* assign dma request to Tx channel */
227  dmaReqAssign((dmaChannel_t)DMA_CHANNEL_I2C2_TX, (dmaRequest_t)DMA_REQ_LINE_I2C2_TX);
228  /* assign dma request to Rx channel */
229  dmaReqAssign((dmaChannel_t)DMA_CHANNEL_I2C2_RX, (dmaRequest_t)DMA_REQ_LINE_I2C2_RX);
230 
231  /* Enable Interrupt after reception of data
232  Group A - Interrupts (FTC, LFS, HBC, and BTC) are routed to the ARM CPU
233  User software should configure only Group A interrupts */
234  dmaEnableInterrupt((dmaChannel_t)(dmaChannel_t)DMA_CHANNEL_I2C2_TX, (dmaInterrupt_t)BTC, (dmaIntGroup_t)DMA_INTA);
235  dmaEnableInterrupt((dmaChannel_t)(dmaChannel_t)DMA_CHANNEL_I2C2_RX, (dmaInterrupt_t)BTC, (dmaIntGroup_t)DMA_INTA);
236  dmaEnableInterrupt((dmaChannel_t)(dmaChannel_t)DMA_CHANNEL_I2C2_RX, (dmaInterrupt_t)LFS, (dmaIntGroup_t)DMA_INTA);
237 
238  dma_controlPacketI2cTx.DADD = (uint32_t)(&(i2cREG2->DXR)) + DMA_BIG_ENDIAN_ADDRESS_8BIT;
239  dma_controlPacketI2cRx.SADD = (uint32_t)(&(i2cREG2->DRR)) + DMA_BIG_ENDIAN_ADDRESS_8BIT;
240 
241  /* Set dma control packet for Tx */
242  dmaSetCtrlPacket((dmaChannel_t)DMA_CHANNEL_I2C2_TX, dma_controlPacketI2cTx);
243 
244  /* Set dma control packet for Rx */
245  dmaSetCtrlPacket((dmaChannel_t)DMA_CHANNEL_I2C2_RX, dma_controlPacketI2cRx);
246 
247  /* Set the dma channels to trigger on h/w request */
248  dmaSetChEnable((dmaChannel_t)DMA_CHANNEL_I2C2_TX, (dmaTriggerType_t)DMA_HW);
249  dmaSetChEnable((dmaChannel_t)DMA_CHANNEL_I2C2_RX, (dmaTriggerType_t)DMA_HW);
250 }
251 
252 /** Function called on DMA complete interrupts (TX and RX). Defined as weak in HAL. */
253 /* AXIVION Next Codeline Style Linker-Multiple_Definition: TI HAL only provides a weak implementation */
254 void UNIT_TEST_WEAK_IMPL dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) {
255  /* AXIVION Routine Generic-MissingParameterAssert: inttype: unchecked in interrupt */
256  /* AXIVION Routine Generic-MissingParameterAssert: channel: unchecked in interrupt */
257 
258  if (inttype == (dmaInterrupt_t)BTC) {
259  uint16_t timeoutIterations = 0u;
260  uint8_t spiIndex = 0u;
261  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
262  bool success = true;
263  switch (channel) {
264  /* DMA for SPI Tx */
265  case DMA_CHANNEL_SPI1_TX:
266  case DMA_CHANNEL_SPI2_TX:
267  case DMA_CHANNEL_SPI3_TX:
268  case DMA_CHANNEL_SPI4_TX:
269  case DMA_CHANNEL_SPI5_TX:
270  /* Search for SPI index with DMA TX channel */
271  for (uint8_t i = 0u; i < DMA_NUMBER_SPI_INTERFACES; i++) {
272  if (channel == (uint32_t)dma_spiDmaChannels[i].txChannel) {
273  spiIndex = i;
274  break;
275  }
276  }
277  /**
278  * TX SPI DMA interrupt: last but one word transmitted,
279  * last word is transmitted manually (in order to write CSHOLD field)
280  */
281  timeoutIterations = SPI_TX_EMPTY_TIMEOUT_ITERATIONS;
282  /* Wait until TX buffer is free for the last word */
283  while (((dma_spiInterfaces[spiIndex]->FLG &
284  (uint32)((uint32_t)1u << SPI_TX_BUFFER_EMPTY_FLAG_POSITION)) == 0u) &&
285  (timeoutIterations > 0u)) {
286  timeoutIterations--;
287  }
288  SPI_DmaSendLastByte(spiIndex);
289  break;
290 
291  /* DMA for SPI Rx */
292  case DMA_CHANNEL_SPI1_RX:
293  case DMA_CHANNEL_SPI2_RX:
294  case DMA_CHANNEL_SPI3_RX:
295  case DMA_CHANNEL_SPI4_RX:
296  case DMA_CHANNEL_SPI5_RX:
297  /* Search for SPI index with DMA RX channel */
298  for (uint8_t i = 0u; i < DMA_NUMBER_SPI_INTERFACES; i++) {
299  if (channel == (uint32_t)dma_spiDmaChannels[i].rxChannel) {
300  spiIndex = i;
301  break;
302  }
303  }
304  /* RX SPI DMA interrupt: last word received, means SPI transmission is finished */
305  if (spiIndex == SPI_GetSpiIndex(spiREG4)) { /** SPI configured as slave */
306  /* RX DMA interrupt, transmission finished, disable DMA */
307  dma_spiInterfaces[spiIndex]->INT0 &= ~DMAREQEN_BIT;
308  /* Disable SPI to prevent unwanted reception */
309  dma_spiInterfaces[spiIndex]->GCR1 &= ~SPIEN_BIT;
310  /* Set slave SPI Chip Select pins as GIO to deactivate slave SPI Chip Select pins */
312 
313  /* Specific call for AFEs */
314  AFE_DmaCallback(spiIndex);
315  } else { /* SPI configured as master */
316  /* RX DMA interrupt, transmission finished, disable DMA */
317  dma_spiInterfaces[spiIndex]->INT0 &= ~DMAREQEN_BIT;
318 
319  /* Specific call for AFEs */
320  if (spiIndex == SPI_GetSpiIndex(spiREG1)) {
321  AFE_DmaCallback(spiIndex);
322  }
323  spi_busyFlags[spiIndex] = SPI_IDLE;
324  }
325  break;
326 
327  /* DMA for I2C Tx */
328  case DMA_CHANNEL_I2C1_TX:
329  i2cREG1->DMACR &= ~((uint32_t)I2C_TXDMAEN);
330  (void)xTaskNotifyIndexedFromISR(
334  eSetValueWithOverwrite,
335  &xHigherPriorityTaskWoken);
336  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
337  break;
338  case DMA_CHANNEL_I2C2_TX:
339  i2cREG2->DMACR &= ~((uint32_t)I2C_TXDMAEN);
340  (void)xTaskNotifyIndexedFromISR(
344  eSetValueWithOverwrite,
345  &xHigherPriorityTaskWoken);
346  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
347  break;
348 
349  /* DMA for I2C Rx */
350  case DMA_CHANNEL_I2C1_RX:
351  i2cREG1->DMACR &= ~((uint32_t)I2C_RXDMAEN);
352  /* Received all but the last byte, now wait until receive buffer is filled with the last byte to receive */
353  success = I2C_WaitReceive(i2cREG1, I2C_TIMEOUT_us);
354  if (success == false) {
355  /* Set Stop condition */
356  i2cREG1->MDR |= (uint32_t)I2C_REPEATMODE;
357  i2cSetStop(i2cREG1);
358  (void)xTaskNotifyIndexedFromISR(
362  eSetValueWithOverwrite,
363  &xHigherPriorityTaskWoken);
364  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
365  } else {
367  (void)xTaskNotifyIndexedFromISR(
371  eSetValueWithOverwrite,
372  &xHigherPriorityTaskWoken);
373  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
374  }
375  break;
376  case DMA_CHANNEL_I2C2_RX:
377  i2cREG2->DMACR &= ~((uint32_t)I2C_RXDMAEN);
378  /* Received all but the last byte, now wait until receive buffer is filled with the last byte to receive */
379  success = I2C_WaitReceive(i2cREG2, I2C_TIMEOUT_us);
380  if (success == false) {
381  /* Set Stop condition */
382  i2cREG2->MDR |= (uint32_t)I2C_REPEATMODE;
383  i2cSetStop(i2cREG2);
384  (void)xTaskNotifyIndexedFromISR(
388  eSetValueWithOverwrite,
389  &xHigherPriorityTaskWoken);
390  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
391  } else {
393  (void)xTaskNotifyIndexedFromISR(
397  eSetValueWithOverwrite,
398  &xHigherPriorityTaskWoken);
399  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
400  }
401  break;
402  default:
403  break;
404  }
405  }
406  /* Interrupt before last transfer is started */
407  if (inttype == (dmaInterrupt_t)LFS) {
408  if (channel == DMA_CHANNEL_I2C1_RX) {
409  /* Before last byte is received, set stop to generate NACK*/
410  i2cSetStop(i2cREG1);
411  }
412  if (channel == DMA_CHANNEL_I2C2_RX) {
413  /* Before last byte is received, set stop to generate NACK*/
414  i2cSetStop(i2cREG2);
415  }
416  }
417 }
418 
419 /*========== Externalized Static Function Implementations (Unit Test) =======*/
420 #ifdef UNITY_UNIT_TEST
421 #endif
Headers for the driver for the general DMA module of monitoring ICs.
void AFE_DmaCallback(uint8_t spiIndex)
Function called by DMA block transfer callback.
void DMA_Initialize(void)
Enables the DMA module.
Definition: dma.c:77
void UNIT_TEST_WEAK_IMPL dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
Definition: dma.c:254
Headers for the driver for the DMA module.
DMA_REQUEST_CONFIG_s dma_spiDmaRequests[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:78
spiBASE_t * dma_spiInterfaces[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:87
DMA_CHANNEL_CONFIG_s dma_spiDmaChannels[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:69
#define DMA_REQ_LINE_I2C2_TX
Definition: dma_cfg.h:105
#define DMA_CHANNEL_SPI1_RX
Definition: dma_cfg.h:76
#define DMA_CHANNEL_SPI5_RX
Definition: dma_cfg.h:84
#define SPIEN_BIT
Definition: dma_cfg.h:119
#define DMA_REQ_LINE_I2C1_RX
Definition: dma_cfg.h:104
#define DMA_BIG_ENDIAN_ADDRESS_16BIT
Definition: dma_cfg.h:112
#define DMA_CHANNEL_SPI4_TX
Definition: dma_cfg.h:81
#define DMA_BIG_ENDIAN_ADDRESS_8BIT
Definition: dma_cfg.h:110
#define DMA_CHANNEL_I2C1_TX
Definition: dma_cfg.h:85
#define DMA_NUMBER_SPI_INTERFACES
Definition: dma_cfg.h:115
#define DMAREQEN_BIT
Definition: dma_cfg.h:117
#define DMA_CHANNEL_I2C2_TX
Definition: dma_cfg.h:87
#define DMA_CHANNEL_SPI3_RX
Definition: dma_cfg.h:80
#define DMA_REQ_LINE_I2C1_TX
Definition: dma_cfg.h:103
#define DMA_CHANNEL_I2C2_RX
Definition: dma_cfg.h:88
#define DMA_REQ_LINE_I2C2_RX
Definition: dma_cfg.h:106
#define DMA_CHANNEL_SPI5_TX
Definition: dma_cfg.h:83
#define DMA_CHANNEL_SPI1_TX
Definition: dma_cfg.h:75
#define DMA_CHANNEL_SPI4_RX
Definition: dma_cfg.h:82
#define DMA_CHANNEL_SPI3_TX
Definition: dma_cfg.h:79
#define DMA_CHANNEL_SPI2_TX
Definition: dma_cfg.h:77
#define DMA_CHANNEL_I2C1_RX
Definition: dma_cfg.h:86
#define DMA_CHANNEL_SPI2_RX
Definition: dma_cfg.h:78
Header of task driver implementation.
#define UNIT_TEST_WEAK_IMPL
Definition: general.h:97
bool I2C_WaitReceive(i2cBASE_t *pI2cInterface, uint32_t timeout_us)
Waits for the I2C Rx buffer to be full.
Definition: i2c.c:772
uint8_t i2c_rxLastByteInterface2
Definition: i2c.c:77
uint8_t i2c_rxLastByteInterface1
Definition: i2c.c:75
uint8_t I2C_ReadLastRxByte(i2cBASE_t *pI2cInterface)
Used to read last byte received per I2C.
Definition: i2c.c:766
Header for the driver for the I2C module.
#define I2C_NOTIFICATION_RX_INDEX
Definition: i2c.h:85
#define I2C_TIMEOUT_us
Definition: i2c.h:69
#define I2C_NOTIFICATION_TX_INDEX
Definition: i2c.h:83
#define I2C_RXDMAEN
Definition: i2c.h:74
#define I2C_TASK_HANDLE
Definition: i2c.h:80
#define I2C_TX_NOTIFIED_VALUE
Definition: i2c.h:89
#define I2C_RX_NOTIFIED_VALUE
Definition: i2c.h:91
#define I2C_TXDMAEN
Definition: i2c.h:72
#define I2C_RX_NOTCOME_VALUE
Definition: i2c.h:93
void SPI_DmaSendLastByte(uint8_t spiIndex)
Used to send last byte per SPI.
Definition: spi.c:530
uint8_t SPI_GetSpiIndex(spiBASE_t *pNode)
Returns index of SPI node.
Definition: spi.c:555
Headers for the driver for the SPI module.
SPI_BUSY_STATE_e spi_busyFlags[]
Definition: spi_cfg.c:240
@ SPI_IDLE
Definition: spi_cfg.h:110
#define SPI_TX_EMPTY_TIMEOUT_ITERATIONS
Definition: spi_cfg.h:100
#define SPI_TX_BUFFER_EMPTY_FLAG_POSITION
Definition: spi_cfg.h:94
#define SPI_PC0_CLEAR_HW_CS_MASK
Definition: spi_cfg.h:97