foxBMS - Unit Tests  1.4.0
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mxm_17841b.c
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41 
42 /**
43  * @file mxm_17841b.c
44  * @author foxBMS Team
45  * @date 2018-12-14 (date of creation)
46  * @updated 2022-07-28 (date of last update)
47  * @version v1.4.0
48  * @ingroup DRIVERS
49  * @prefix MXM
50  *
51  * @brief Driver for the MAX17841B ASCI and MAX1785x monitoring chip
52  *
53  * @details def
54  *
55  */
56 
57 /*========== Includes =======================================================*/
58 #include "mxm_17841b.h"
59 
60 #include "mxm_41b_register_map.h"
61 #include "mxm_bitextract.h"
62 #include "os.h"
63 
64 /*========== Macros and Definitions =========================================*/
65 /** bit shift half byte length */
66 #define MXM_41B_BIT_SHIFT_HALF_BYTE (4u)
67 
68 /** low nibble (of uint8_t) bit mask */
69 #define MXM_41B_BIT_MASK_LOW_NIBBLE (0xFu)
70 
71 /** high nibble (of uint8_t) bit mask */
72 #define MXM_41B_BIT_MASK_HIGH_NIBBLE (0xF0u)
73 
74 /** (uint8_t) one byte bit mask */
75 #define MXM_41B_BIT_MASK_ONE_BYTE (0xFFu)
76 
77 /** threshold above which a reset in this driver occurs in case of hangup */
78 #define MXM_41B_WAIT_COUNTER_THRESHOLD (75u)
79 #if MXM_41B_WAIT_COUNTER_THRESHOLD > (UINT8_MAX - 1)
80 #error "invalid wait counter threshold (counter is implemented in uint8_t)"
81 #endif
82 
83 /**
84  * time interval that shall ensure that the bridge IC is completely reset in ms
85  */
86 #define MXM_41B_BRIDGE_RESET_TIME_MS (100u)
87 
88 /** default config register bank length
89  *
90  * Length of the array that writes the registers referenced in
91  * mxm_41B_reg_default_values in #MXM_41BStateHandlerInit().
92  */
93 #define MXM_41B_CONFIG_REGISTER_LENGTH (7u)
94 
95 /*========== Static Constant and Variable Definitions =======================*/
96 
97 /*========== Extern Constant and Variable Definitions =======================*/
98 
99 /*========== Static Function Prototypes =====================================*/
100 /* static MXM_SPI_STATE_s mxm_proto_enable_keep_alive(void); */
101 /**
102  * @brief Write one or multiple registers of MAX17841B.
103  *
104  * This function puts together a SPI message consisting of command
105  * and payload and writes it to the assigned SPI interface.
106  *
107  * The command should be one of the #MXM_41B_REG_ADD_t commands.
108  * The function checks whether the chosen command is a write command.
109  *
110  * The payload-length has to be consistent with the payload.
111  * Payload-lengths of one will write to one register only. Longer payloads
112  * will write to adjacent registers. Please see the MAX17841B data sheet
113  * for reference.
114  *
115  * @param[in,out] pInstance pointer to the state of the MAX17841B-state-machine
116  * @param[in] command register command of #MXM_41B_REG_ADD_t
117  * @param[in] kpkPayload pointer to an array of data to be written
118  * @param[in] lengthPayload length of the payload array
119  * @return #STD_NOT_OK for inconsistent input or a blocked SPI interface,
120  * otherwise #STD_OK
121  */
123  MXM_41B_INSTANCE_s *pInstance,
124  MXM_41B_REG_ADD_t command,
125  const uint8_t *const kpkPayload,
126  uint8_t lengthPayload);
127 
128 /**
129  * @brief Read one or multiple registers of MAX17841B.
130  *
131  * This function puts together a SPI message consisting of command
132  * and bit-stuffing and writes it to the assigned SPI-interface.
133  *
134  * The command should be one of the #MXM_41B_REG_ADD_t commands.
135  * The function checks whether the chosen command is a read command.
136  *
137  * The RX buffer length has to be consistent with the RX buffer.
138  * RX buffer lengths of one will read one register only. Longer RX buffers
139  * will read also from adjacent registers. Please see the MAX17841B data sheet
140  * for reference.
141  *
142  * @param[in,out] pInstance pointer to the state of the MAX17841B-state-machine
143  * @param[in] command register command of #MXM_41B_REG_ADD_t
144  * @param[out] pRxBuffer pointer to an array into which read data will be written
145  * @param[in] length length of the RX buffer array
146  * @return #STD_NOT_OK for inconsistent input or a blocked SPI interface,
147  * otherwise #STD_OK
148  */
150  MXM_41B_INSTANCE_s *pInstance,
151  MXM_41B_REG_ADD_t command,
152  uint16_t *pRxBuffer,
153  uint8_t length);
154 
155 /**
156  * @brief Write the config register of MAX17841B.
157  *
158  * This functions writes the config registers with the values
159  * from the local register copies. It puts together a
160  * buffer from these register values and calls MXM_41BRegisterWrite()
161  * with this data.
162  * Calling this function will clear the interrupt registers and reset them
163  * to their default values (which is #MXM_41B_RX_INT_FLAG_DEFAULT_VALUE and
164  * #MXM_41B_TX_INT_FLAG_DEFAULT_VALUE).
165  *
166  * @param[in,out] pInstance state pointer
167  * @return returnvalue of #MXM_41BRegisterWrite()
168  */
170 
171 /**
172  * @brief Write a buffer transaction to MAX17841B.
173  *
174  * Writes into the load-queue-buffer.
175  * The supplied-message-length marks the length of the Battery Management
176  * Protocol message without any stuffing-bytes for read-commands.
177  * The extendMessage parameter describes with how much bytes the
178  * command shall be stretched. This number will be added to the
179  * length of the command and written into the length field of the
180  * buffer.
181  * After this action the user has to select the next load queue with
182  * the appropriate command in order to mark the load queue as sendable.
183  *
184  * @param[in,out] pInstance pointer to the state of the MAX17841B-state-machine
185  * @param[in] kpkMessage pointer to an array containing the message
186  * @param[in] messageLength length of the supplied array
187  * @param[in] extendMessage stretch the message by number of bytes
188  * @return #STD_NOT_OK for inconsistent input or a blocked SPI interface,
189  * otherwise #STD_OK
190  */
192  MXM_41B_INSTANCE_s *pInstance,
193  const uint16_t *const kpkMessage,
194  uint8_t messageLength,
195  uint8_t extendMessage);
196 
197 /**
198  * @brief Transition into idle, mark as successful
199  * @param[out] pInstance pointer to the state-struct
200  */
201 static void MXM_41BTransitionToIdleSuccess(MXM_41B_INSTANCE_s *pInstance);
202 
203 /**
204  * @brief Transition into idle, mark as an error occurred
205  * @param[out] pInstance pointer to the state-struct
206  */
207 static void MXM_41BTransitionToIdleError(MXM_41B_INSTANCE_s *pInstance);
208 
209 /**
210  * @brief Reset register copies to default
211  * @param[out] pInstance pointer to the state-struct
212  */
214 
215 /**
216  * \defgroup mxm-41b-state-handlers State handler functions for #MXM_41BStateMachine()
217  * @{
218  */
219 
220 /**
221  * @brief init state handler
222  * @details This function contains all states for #MXM_STATEMACH_41B_INIT.
223  * @param[in,out] pInstance pointer to the state-struct
224  */
225 static void MXM_41BStateHandlerInit(MXM_41B_INSTANCE_s *pInstance);
226 
227 /**
228  * @brief state handler for "get version"
229  * @details This function contains all states for #MXM_STATEMACH_41B_GET_VERSION.
230  * @param[in,out] pInstance pointer to the state-struct
231  */
232 static void MXM_41BStateHandlerGetVersion(MXM_41B_INSTANCE_s *pInstance);
233 
234 /**
235  * @brief state handler for "idle"
236  * @details This function contains all states for #MXM_STATEMACH_41B_IDLE.
237  * @param[in,out] pInstance pointer to the state-struct
238  */
239 static void MXM_41BStateHandlerIdle(MXM_41B_INSTANCE_s *pInstance);
240 
241 /**
242  * @brief state handler for "write conf and int register"
243  * @details This functions contains all states for #MXM_STATEMACH_41B_WRITE_CONF_AND_INT_REGISTER.
244  * @param[in,out] pInstance pointer to the state-struct
245  */
247 
248 /**
249  * @brief state handler for "read status register"
250  * @details This functions contains all states for #MXM_STATEMACH_41B_READ_STATUS_REGISTER.
251  * @param[in,out] pInstance pointer to the state-struct
252  */
254 
255 /**
256  * @brief state handler for "uart transaction"
257  * @details This functions contains all states for #MXM_STATEMACH_41B_UART_TRANSACTION.
258  * @param[in,out] pInstance pointer to the state-struct
259  */
261 
262 /**
263  * @brief state handler for "check fmea"
264  * @details This functions contains all states for #MXM_STATEMACH_41B_CHECK_FMEA.
265  * @param[in,out] pInstance pointer to the state-struct
266  */
267 static void MXM_41BStateHandlerCheckFmea(MXM_41B_INSTANCE_s *pInstance);
268 
269 /**
270  * @brief state handler for "clear receive buffer"
271  * @details This functions contains all states for #MXM_STATEMACH_41B_CLEAR_RECEIVE_BUFFER.
272  * @param[in,out] pInstance pointer to the state-struct
273  */
275 
276 /**
277  * @brief state handler for "clear transmit buffer"
278  * @details This functions contains all states for #MXM_STATEMACH_41B_CLEAR_TRANSMIT_BUFFER.
279  * @param[in,out] pInstance pointer to the state-struct
280  */
282 
283 /** @} */
284 
285 /*========== Static Function Implementations ================================*/
287  MXM_41B_INSTANCE_s *pInstance,
288  MXM_41B_REG_ADD_t command,
289  const uint8_t *const kpkPayload,
290  uint8_t lengthPayload) {
291  /* sanity check: state-pointer may not be null */
292  FAS_ASSERT(pInstance != NULL_PTR);
293  FAS_ASSERT(lengthPayload < (MXM_SPI_TX_BUFFER_LENGTH - 1u));
294  /* AXIVION Routine Generic-MissingParameterAssert: command: parameter accepts whole range */
295  /* AXIVION Routine Generic-MissingParameterAssert: kpkPayload: pointer may be NULL */
296 
297  STD_RETURN_TYPE_e retval = STD_NOT_OK;
298  /* check if command is a write command (write addresses in MAX17841B are even) */
299  if ((command % 2u) == 0u) {
300  /* construct tx buffer */
301  pInstance->spiTXBuffer[0] = command;
302  /* message has payload --> copy into buffer */
303  if ((kpkPayload != NULL_PTR) && (lengthPayload != 0u)) {
304  for (uint8_t i = 0u; i < lengthPayload; i++) {
305  pInstance->spiTXBuffer[i + 1u] = kpkPayload[i];
306  }
307  /* null rest of tx buffer */
308  for (uint8_t i = lengthPayload + 1u; i < MXM_SPI_TX_BUFFER_LENGTH; i++) {
309  pInstance->spiTXBuffer[i] = 0u;
310  }
311  /* send command with payload */
312  retval = MXM_SendData(pInstance->spiTXBuffer, (uint16_t)lengthPayload + 1u);
313  } else if ((kpkPayload == NULL_PTR) && (lengthPayload == 0u)) {
314  /* send command without payload */
315  retval = MXM_SendData(pInstance->spiTXBuffer, 1);
316  } else {
317  /* invalid configuration */
318  }
319  }
320  return retval;
321 }
322 
324  MXM_41B_INSTANCE_s *pInstance,
325  MXM_41B_REG_ADD_t command,
326  uint16_t *pRxBuffer,
327  uint8_t length) {
328  /* sanity check: state-pointer may not be null */
329  FAS_ASSERT(pInstance != NULL_PTR);
330  /* RX Buffer may not be NULL pointer for this function */
331  FAS_ASSERT(pRxBuffer != NULL_PTR);
333  /* AXIVION Routine Generic-MissingParameterAssert: command: parameter accepts whole range */
334 
335  STD_RETURN_TYPE_e retval = STD_NOT_OK;
336  /* check if command is a read command (read addresses in MAX17841B are odd) */
337  if ((command % 2u) != 0u) {
338  /* construct tx buffer */
339  pInstance->spiTXBuffer[0] = command;
340  /* null rest of tx buffer */
341  for (uint16_t i = 1u; i < MXM_SPI_TX_BUFFER_LENGTH; i++) {
342  pInstance->spiTXBuffer[i] = 0u;
343  }
344  /* send command with payload */
345  retval = MXM_ReceiveData(pInstance->spiTXBuffer, pRxBuffer, ((uint16_t)length + 1u));
346  }
347  return retval;
348 }
349 
351  /* sanity check: state-pointer may not be null */
352  FAS_ASSERT(pInstance != NULL_PTR);
353  uint8_t mxm_spi_temp_buffer[MXM_41B_CONFIG_REGISTER_LENGTH] = {0};
354 
355  /* AXIVION Disable Style Generic-NoMagicNumbers: Magic numbers for index value of array is clear in usage */
356  mxm_spi_temp_buffer[0u] = pInstance->regRXIntEnable;
357  mxm_spi_temp_buffer[1u] = pInstance->regTXIntEnable;
358  mxm_spi_temp_buffer[2u] = MXM_41B_RX_INT_FLAG_DEFAULT_VALUE;
359  mxm_spi_temp_buffer[3u] = MXM_41B_TX_INT_FLAG_DEFAULT_VALUE;
360  mxm_spi_temp_buffer[4u] = pInstance->regConfig1;
361  mxm_spi_temp_buffer[5u] = pInstance->regConfig2;
362  mxm_spi_temp_buffer[6u] = pInstance->regConfig3;
363  /* AXIVION Enable Style Generic-NoMagicNumbers: */
364  FAS_STATIC_ASSERT((6u < MXM_41B_CONFIG_REGISTER_LENGTH), "Revise this function and config register length!");
365 
366  return MXM_41BRegisterWrite(
367  pInstance, MXM_REG_RX_INTERRUPT_ENABLE_W, mxm_spi_temp_buffer, MXM_41B_CONFIG_REGISTER_LENGTH);
368 }
369 
371  MXM_41B_INSTANCE_s *pInstance,
372  const uint16_t *const kpkMessage,
373  uint8_t messageLength,
374  uint8_t extendMessage) {
375  /* sanity check: state-pointer may not be null */
376  FAS_ASSERT(pInstance != NULL_PTR);
377  /* check if message-pointer is valid */
378  FAS_ASSERT(kpkMessage != NULL_PTR);
379  FAS_ASSERT(messageLength >= 1u);
380  FAS_ASSERT(messageLength <= 6u);
381  /* AXIVION Routine Generic-MissingParameterAssert: extendMessage: parameter accepts whole range */
382 
383  /* write address and length to buffer */
384  pInstance->spiTXBuffer[0] = (uint16_t)MXM_BUF_WR_LD_Q_0;
385  pInstance->spiTXBuffer[1] = (uint16_t)messageLength + extendMessage;
386  /* iterate of complete TX buffer and
387  * write into proper fields, null rest
388  */
389  for (uint8_t i = 0; i < (MXM_SPI_TX_BUFFER_LENGTH - 2u); i++) {
390  if (i < messageLength) {
391  pInstance->spiTXBuffer[i + 2u] = kpkMessage[i];
392  } else {
393  pInstance->spiTXBuffer[i + 2u] = 0x00u;
394  }
395  }
396 
397  /* send data */
398  return MXM_SendData(pInstance->spiTXBuffer, ((uint16_t)messageLength + 2u));
399 }
400 
402  FAS_ASSERT(pInstance != NULL_PTR);
403  FAS_ASSERT(pInstance->processed != NULL_PTR);
404  pInstance->state = MXM_STATEMACH_41B_IDLE;
405  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
406  *pInstance->processed = MXM_41B_STATE_PROCESSED;
407  return;
408 }
409 
411  FAS_ASSERT(pInstance != NULL_PTR);
412  FAS_ASSERT(pInstance->processed != NULL_PTR);
413  pInstance->state = MXM_STATEMACH_41B_IDLE;
414  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
415  *pInstance->processed = MXM_41B_STATE_ERROR;
416  return;
417 }
418 
420  FAS_ASSERT(pInstance != NULL_PTR);
421  pInstance->regRXStatus = 0u;
422  pInstance->regTXStatus = 0u;
428  return;
429 }
430 
432  FAS_ASSERT(pInstance != NULL_PTR);
433 
434  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
435  /* entry of state --> set to first substate */
437  }
438 
439  if (pInstance->substate == MXM_41B_INIT_RESET_BRIDGE_IC) {
441  pInstance->shutdownTimeStamp = OS_GetTickCount();
443  } else if (pInstance->substate == MXM_41B_INIT_START_BRIDGE_IC) {
444  const bool resetTimeHasPassed =
446  if (resetTimeHasPassed) {
449  }
450  } else if (pInstance->substate == MXM_41B_INIT_WRITE_DEFAULT_VALUES) {
451  /* set default register values according to data sheet */
453  const STD_RETURN_TYPE_e retval = MXM_41BConfigRegisterWrite(pInstance);
454  if (retval == STD_OK) {
456  }
457  } else if (pInstance->substate == MXM_41B_INIT_READ_CONFIG_REGISTERS) {
458  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(
460 
461  if (retval == STD_OK) {
463  }
464  } else if (pInstance->substate == MXM_41B_INIT_CHECK_INITIALIZATION) {
465  STD_RETURN_TYPE_e retval = STD_OK;
466 
467  if (MXM_GetSPIStateReady() == STD_OK) {
468  /**
469  * @brief Default values for the configuration and interrupt registers
470  * @details This constant array contains the default values to which the
471  * configuration is compared when resetting it.
472  * The array is 7 entries long in order to fit onto the following
473  * registers which are placed in succession in the memory of
474  * MAX17841B:
475  * - RX_Interrupt_Enable
476  * - TX_Interrupt_Enable
477  * - RX_Interrupt_Flags
478  * - TX_Interrupt_Flags
479  * - Configuration_1
480  * - Configuration_2
481  * - Configuration_3
482  */
483  const uint8_t mxm_41B_reg_default_values[MXM_41B_CONFIG_REGISTER_LENGTH] = {
491 
492  for (uint8_t i = 0; i < MXM_41B_CONFIG_REGISTER_LENGTH; i++) {
493  if (pInstance->spiRXBuffer[i + 1u] != mxm_41B_reg_default_values[i]) {
494  retval = STD_NOT_OK;
495  }
496  }
497  } else {
498  retval = STD_NOT_OK;
499  }
500 
501  if (retval == STD_NOT_OK) {
502  MXM_41BTransitionToIdleError(pInstance);
503  } else {
505  }
506  } else {
507  MXM_41BTransitionToIdleError(pInstance);
508  }
509 }
510 
512  FAS_ASSERT(pInstance != NULL_PTR);
513  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
515  }
516 
517  if (pInstance->substate == MXM_41B_VERSION_REQUEST_REGISTER) {
518  /* read two byte in order to read also the adjacent version register */
519  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_MODEL_R, pInstance->spiRXBuffer, 2);
520 
521  if (retval == STD_OK) {
522  pInstance->substate = MXM_41B_VERSION_VERIFY;
523  }
524  } else if (pInstance->substate == MXM_41B_VERSION_VERIFY) {
525  if (MXM_GetSPIStateReady() == STD_OK) {
526  /* get model from model register and high nibble of mask revision (should be 0x8410) */
527  pInstance->hwModel =
528  (uint16_t)((pInstance->spiRXBuffer[1] & MXM_41B_BIT_MASK_ONE_BYTE) << MXM_41B_BIT_SHIFT_HALF_BYTE);
529  pInstance->hwModel |=
531  /* extract mask revision from low nibble */
532  pInstance->hwMaskRevision = (uint8_t)(pInstance->spiRXBuffer[2] & MXM_41B_BIT_MASK_LOW_NIBBLE);
533 
535  }
536  } else {
537  /* something is very broken */
538  MXM_41BTransitionToIdleError(pInstance);
539  }
540 }
541 
543  FAS_ASSERT(pInstance != NULL_PTR);
544  /* do nothing in idle state
545  just clean up substate */
546  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
547 }
548 
550  FAS_ASSERT(pInstance != NULL_PTR);
551  const STD_RETURN_TYPE_e retval = MXM_41BConfigRegisterWrite(pInstance);
552 
553  if (retval == STD_NOT_OK) {
554  MXM_41BTransitionToIdleError(pInstance);
555  } else {
557  }
558 }
559 
561  FAS_ASSERT(pInstance != NULL_PTR);
562  /* TODO read status register and parse into static variables */
563  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
564  /* entry of state --> set to first substate */
566  }
567 
568  if (pInstance->substate == MXM_41B_READ_STATUS_REGISTER_SEND) {
569  /* read rx and tx status register */
570  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_RX_STATUS_R, pInstance->spiRXBuffer, 2);
571  if (retval == STD_NOT_OK) {
572  MXM_41BTransitionToIdleError(pInstance);
573  } else {
575  }
576  } else if (pInstance->substate == MXM_41B_READ_STATUS_REGISTER_PROCESS) {
577  pInstance->regRXStatus = (uint8_t)(pInstance->spiRXBuffer[1] & 0xFFu);
578  pInstance->regTXStatus = (uint8_t)(pInstance->spiRXBuffer[2] & 0xFFu);
580  } else {
581  /* something is very broken */
582  MXM_41BTransitionToIdleError(pInstance);
583  }
584 }
585 
587  FAS_ASSERT(pInstance != NULL_PTR);
588  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
589  /* entry of state --> set to first substate */
591  }
592 
593  if (pInstance->substate == MXM_41B_UART_READ_RX_SPACE) {
594  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_RX_SPACE_R, pInstance->spiRXBuffer, 1u);
595  if (retval == STD_NOT_OK) {
596  MXM_41BTransitionToIdleError(pInstance);
597  } else {
599  }
600  } else if (pInstance->substate == MXM_41B_UART_READ_RX_SPACE_PARSE) {
601  pInstance->regRxSpace = (uint8_t)(pInstance->spiRXBuffer[1] & MXM_41B_BIT_MASK_ONE_BYTE);
603 
604  } else if (pInstance->substate == MXM_41B_UART_WRITE_LOAD_QUEUE) {
605  /* load queue with message */
606  const STD_RETURN_TYPE_e retval =
607  MXM_41BBufferWrite(pInstance, pInstance->pPayload, pInstance->payloadLength, pInstance->extendMessageBytes);
608 
609  if (retval == STD_NOT_OK) {
610  MXM_41BTransitionToIdleError(pInstance);
611  } else {
613  }
614  } else if (pInstance->substate == MXM_41B_UART_READ_LOAD_QUEUE) {
615  /* check assumption that incremented payloadlength fits into uint8_t */
616  FAS_ASSERT(pInstance->payloadLength < (uint8_t)UINT8_MAX);
617  const uint8_t payloadLength = pInstance->payloadLength + 1u;
618  /* send read load queue */
619  const STD_RETURN_TYPE_e retval =
620  MXM_41BRegisterRead(pInstance, MXM_BUF_RD_LD_Q_0, pInstance->spiRXBuffer, payloadLength);
621 
622  if (retval == STD_NOT_OK) {
623  MXM_41BTransitionToIdleError(pInstance);
624  } else {
626  }
627  } else if (pInstance->substate == MXM_41B_UART_VERIFY_LOAD_QUEUE_AND_TRANSMIT) {
628  /* verify load queue */
629  STD_RETURN_TYPE_e retval = STD_OK;
630  /* check message length */
631  if (pInstance->spiRXBuffer[1] != (pInstance->payloadLength + (uint16_t)pInstance->extendMessageBytes)) {
632  retval = STD_NOT_OK;
633  }
634  for (uint8_t i = 0; i < pInstance->payloadLength; i++) {
635  FAS_ASSERT(pInstance->pPayload != NULL_PTR);
636  if (pInstance->spiRXBuffer[i + 2u] != pInstance->pPayload[i]) {
637  /* message corrupted during SPI transfer */
638  retval = STD_NOT_OK;
639  }
640  }
641  if (retval == STD_NOT_OK) {
642  MXM_41BTransitionToIdleError(pInstance);
643  } else {
644  /* transmit queue */
645  retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_WR_NXT_LD_Q_0, NULL_PTR, 0);
646 
647  if (retval == STD_NOT_OK) {
648  MXM_41BTransitionToIdleError(pInstance);
649  } else {
651  }
652  }
653  } else if (pInstance->substate == MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_WRITE) {
654  /* poll RX status change */
655  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_RX_STATUS_R, pInstance->spiRXBuffer, 1);
656 
657  if (retval == STD_NOT_OK) {
658  MXM_41BTransitionToIdleError(pInstance);
659  } else {
661  }
663  /* update RX status register copy with received buffer */
664  pInstance->regRXStatus = (uint8_t)(pInstance->spiRXBuffer[1] & MXM_41B_BIT_MASK_ONE_BYTE);
665  /* check if RX_OVERFLOW_Status is 1 */
666  MXM_41B_REG_BIT_VALUE rx_overflow_status_value = MXM_41B_REG_FALSE;
667  const STD_RETURN_TYPE_e resultWrongRegisterOverflow =
668  MXM_41BReadRegisterFunction(pInstance, MXM_41B_REG_FUNCTION_RX_OVERFLOW_STATUS, &rx_overflow_status_value);
669  FAS_ASSERT(resultWrongRegisterOverflow == STD_OK);
670  /* check if RX_STOP_Status is 1 */
671  MXM_41B_REG_BIT_VALUE rx_stop_status_value = MXM_41B_REG_FALSE;
672  const STD_RETURN_TYPE_e resultWrongRegisterStop =
673  MXM_41BReadRegisterFunction(pInstance, MXM_41B_REG_FUNCTION_RX_STOP_STATUS, &rx_stop_status_value);
674  FAS_ASSERT(resultWrongRegisterStop == STD_OK);
675  if (rx_overflow_status_value == MXM_41B_REG_TRUE) {
676  /* overflow, we have to discard the rx buffer */
677  const STD_RETURN_TYPE_e retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_CLR_RX_BUF, NULL_PTR, 0);
678  if (retval == STD_NOT_OK) {
679  MXM_41BTransitionToIdleError(pInstance);
680  } else {
681  MXM_41BTransitionToIdleError(pInstance);
682  }
683  } else if (rx_stop_status_value == MXM_41B_REG_TRUE) {
684  /* received full UART frame --> continue */
685  /* check assumption that payload length fits into uint8_t */
686  FAS_ASSERT((pInstance->payloadLength + (uint16_t)1u + pInstance->extendMessageBytes) <= (uint8_t)UINT8_MAX);
687  const uint8_t payloadLength = pInstance->payloadLength + 1u + pInstance->extendMessageBytes;
688  /* read back receive buffer */
689  const STD_RETURN_TYPE_e retval =
690  MXM_41BRegisterRead(pInstance, MXM_BUF_RD_NXT_MSG, pInstance->spiRXBuffer, payloadLength);
691 
692  if (retval == STD_NOT_OK) {
693  MXM_41BTransitionToIdleError(pInstance);
694  } else {
696  pInstance->waitCounter = 0u;
697  }
698  } else {
699  /* no UART frame received yet --> check again */
701  /* increment wait counter (only to 1 above MXM_41B_WAIT_COUNTER_THRESHOLD,
702  then other parts of the code will reset). */
703  if (pInstance->waitCounter <= MXM_41B_WAIT_COUNTER_THRESHOLD) {
704  pInstance->waitCounter++;
705  }
706  }
707  } else if (pInstance->substate == MXM_41B_UART_READ_BACK_RECEIVE_BUFFER_SAVE) {
708  if ((pInstance->spiRXBuffer != NULL_PTR) && (pInstance->pRxBuffer != NULL_PTR)) {
709  for (uint16_t i = 0; i < ((uint16_t)pInstance->payloadLength + pInstance->extendMessageBytes); i++) {
710  if (i < pInstance->rxBufferLength) {
711  pInstance->pRxBuffer[i] = pInstance->spiRXBuffer[i + 1u];
712  }
713  }
714  }
716  } else {
717  /* we should not be here */
719  }
720 }
721 
723  FAS_ASSERT(pInstance != NULL_PTR);
724  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
726  }
727 
728  if (pInstance->substate == MXM_41B_FMEA_REQUEST_REGISTER) {
729  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_FMEA_R, pInstance->spiRXBuffer, 1);
730 
731  if (retval == STD_OK) {
732  pInstance->substate = MXM_41B_FMEA_VERIFY;
733  }
734  } else if (pInstance->substate == MXM_41B_FMEA_VERIFY) {
735  STD_RETURN_TYPE_e retval = STD_NOT_OK;
736  if (MXM_GetSPIStateReady() == STD_OK) {
737  pInstance->regFmea = pInstance->spiRXBuffer[1u];
738  if (pInstance->regFmea == 0u) {
739  retval = STD_OK;
740  }
741  }
742 
743  if (retval == STD_NOT_OK) {
744  /* FMEA check went bad */
745  MXM_41BTransitionToIdleError(pInstance);
746  } else {
748  }
749  } else {
750  /* something is very broken */
751  MXM_41BTransitionToIdleError(pInstance);
752  }
753 }
754 
756  FAS_ASSERT(pInstance != NULL_PTR);
757  /* clear receive buffer --> reset UART RX into defined state */
758  const STD_RETURN_TYPE_e retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_CLR_RX_BUF, NULL_PTR, 0);
759 
760  if (retval == STD_OK) {
761  /* writing successful, return to idle */
763  } else {
764  /* an error has occurred, retry and set error */
765  MXM_41BTransitionToIdleError(pInstance);
766  }
767 }
768 
770  FAS_ASSERT(pInstance != NULL_PTR);
771  /* clear receive buffer --> reset UART RX into defined state */
772  const STD_RETURN_TYPE_e retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_CLR_TX_BUF, NULL_PTR, 0);
773 
774  if (retval == STD_OK) {
775  /* writing successful, return to idle */
777  } else {
778  /* an error has occurred, retry and set error */
779  MXM_41BTransitionToIdleError(pInstance);
780  }
781 }
782 
783 /*========== Extern Function Implementations ================================*/
785  MXM_41B_INSTANCE_s *pInstance,
786  MXM_STATEMACH_41B_e state,
787  uint16_t *pPayload,
788  uint8_t payloadLength,
789  uint8_t extendMessageBytes,
790  uint16_t *pRxBuffer,
791  uint16_t rxBufferLength,
792  MXM_41B_STATE_REQUEST_STATUS_e *processed) {
793  /* sanity check: state-pointer may not be null */
794  FAS_ASSERT(pInstance != NULL_PTR);
795  /* AXIVION Routine Generic-MissingParameterAssert: state: parameter accepts whole range */
796  /* AXIVION Routine Generic-MissingParameterAssert: pPayload: pointer may be NULL */
797  /* AXIVION Routine Generic-MissingParameterAssert: payloadLength: parameter accepts whole range */
798  /* AXIVION Routine Generic-MissingParameterAssert: extendMessageBytes: parameter accepts whole range */
799  /* AXIVION Routine Generic-MissingParameterAssert: pRxBuffer: pointer may be NULL */
800  /* AXIVION Routine Generic-MissingParameterAssert: rxBufferLength: parameter accepts whole range */
801 
802  STD_RETURN_TYPE_e retval = STD_OK;
803  /* start by checking for input inconsistency */
804  if (state >= MXM_STATEMACH_41B_MAXSTATE) {
805  retval = STD_NOT_OK;
806  } else if ((pPayload == NULL_PTR) && (payloadLength != 0u)) {
807  retval = STD_NOT_OK;
808  } else if ((payloadLength == 0u) && (pPayload != NULL_PTR)) {
809  retval = STD_NOT_OK;
810  } else if ((pRxBuffer == NULL_PTR) && (rxBufferLength != 0u)) {
811  retval = STD_NOT_OK;
812  } else if ((rxBufferLength == 0u) && (pRxBuffer != NULL_PTR)) {
813  retval = STD_NOT_OK;
814  } else if (processed == NULL_PTR) {
815  retval = STD_NOT_OK;
816  } else if (pInstance->state == MXM_STATEMACH_41B_UNINITIALIZED) {
817  if (state == MXM_STATEMACH_41B_INIT) {
818  pInstance->state = state;
819  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
820  pInstance->pPayload = pPayload;
821  pInstance->payloadLength = payloadLength;
822  pInstance->extendMessageBytes = extendMessageBytes;
823  pInstance->pRxBuffer = pRxBuffer;
824  pInstance->rxBufferLength = rxBufferLength;
825  pInstance->processed = processed;
826  *pInstance->processed = MXM_41B_STATE_UNPROCESSED;
827  } else {
828  retval = STD_NOT_OK;
829  }
830  } else if (pInstance->state == MXM_STATEMACH_41B_IDLE) {
831  pInstance->state = state;
832  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
833  pInstance->pPayload = pPayload;
834  pInstance->payloadLength = payloadLength;
835  pInstance->extendMessageBytes = extendMessageBytes;
836  pInstance->pRxBuffer = pRxBuffer;
837  pInstance->rxBufferLength = rxBufferLength;
838  pInstance->processed = processed;
839  *pInstance->processed = MXM_41B_STATE_UNPROCESSED;
840  } else {
841  retval = STD_NOT_OK;
842  }
843  return retval;
844 }
845 
847  MXM_41B_INSTANCE_s *pInstance,
848  MXM_41B_REG_FUNCTION_e registerFunction,
849  MXM_41B_REG_BIT_VALUE value) {
850  /* sanity check: state-pointer may not be null */
851  FAS_ASSERT(pInstance != NULL_PTR);
852  /* AXIVION Routine Generic-MissingParameterAssert: registerFunction: parameter accepts whole range */
853  /* AXIVION Routine Generic-MissingParameterAssert: value: parameter accepts whole range */
854 
855  STD_RETURN_TYPE_e retval = STD_OK;
856  /* TODO sanitize value */
857 
858  switch (registerFunction) {
860  pInstance->regConfig2 = mxm_41bWriteValue(
861  value,
862  1,
864  pInstance->regConfig2); /* MXM_41B_TX_PREAMBLES is 5th bit of regConfig2 */
865  break;
867  pInstance->regConfig3 = mxm_41bWriteValue(
868  value, 4, MXM_41B_KEEP_ALIVE, pInstance->regConfig3); /* MXM_41B_KEEP_ALIVE is 0st bit of regConfig3 */
869  break;
871  pInstance->regRXIntEnable = mxm_41bWriteValue(
872  value,
873  1,
875  pInstance->regRXIntEnable); /* MXM_41B_RX_ERROR is 7th bit of regRXIntEnable */
876  break;
878  pInstance->regRXIntEnable = mxm_41bWriteValue(
879  value,
880  1,
882  pInstance->regRXIntEnable); /* MXM_41B_RX_OVERFLOW is 2nd bit of regRXIntEnable */
883  break;
884  default:
885  retval = STD_NOT_OK;
886  break;
887  }
888 
889  return retval;
890 }
891 
893  const MXM_41B_INSTANCE_s *const kpkInstance,
894  MXM_41B_REG_FUNCTION_e registerFunction,
895  MXM_41B_REG_BIT_VALUE *pValue) {
896  /* sanity check: state-pointer may not be null */
897  FAS_ASSERT(kpkInstance != NULL_PTR);
898  /* sanity check: pValue may not be null */
899  FAS_ASSERT(pValue != NULL_PTR);
900  STD_RETURN_TYPE_e retval = STD_OK;
901 
902  switch (registerFunction) {
904  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_BUSY_STATUS); /* 5th bit */
905  break;
907  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_STOP_STATUS); /* 1st bit */
908  break;
910  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_OVERFLOW_STATUS); /* 3rd bit */
911  break;
913  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_EMPTY_STATUS); /* 0th bit */
914  break;
916  *pValue = mxm_41bReadValue(kpkInstance->regConfig2, 1, MXM_41B_TX_PREAMBLES); /* 5th bit */
917  break;
918  default:
919  *pValue = MXM_41B_REG_FALSE;
920  retval = STD_NOT_OK;
921  break;
922  }
923 
924  return retval;
925 }
926 
928  /* sanity check: state-pointer may not be null */
929  FAS_ASSERT(pInstance != NULL_PTR);
930 
931  if (pInstance->waitCounter > MXM_41B_WAIT_COUNTER_THRESHOLD) {
932  /* error, reset to idle state */
933  MXM_41BTransitionToIdleError(pInstance);
934  pInstance->waitCounter = 0u;
935  }
936  switch (pInstance->state) {
938  break;
940  MXM_41BStateHandlerInit(pInstance);
941  break;
944  break;
946  MXM_41BStateHandlerIdle(pInstance);
947  break;
950  break;
953  break;
956  break;
958  MXM_41BStateHandlerCheckFmea(pInstance);
959  break;
962  break;
965  break;
966  default:
967  /* this default case should never be reached */
969  break;
970  }
971 }
972 
974  FAS_ASSERT(pInstance != NULL_PTR);
975 
977 
979  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
980  pInstance->pPayload = NULL_PTR;
981  pInstance->payloadLength = 0u;
982  pInstance->pRxBuffer = NULL_PTR;
983  pInstance->rxBufferLength = 0u;
984  pInstance->processed = NULL_PTR;
985  pInstance->extendMessageBytes = 0u;
986  pInstance->waitCounter = 0u;
987  pInstance->regRxSpace = 0u;
988  pInstance->regFmea = 0u;
989  pInstance->hwModel = 0u;
990  pInstance->hwMaskRevision = 0u;
991  pInstance->shutdownTimeStamp = 0u;
992 
993  for (uint32_t i = 0u; i < MXM_SPI_RX_BUFFER_LENGTH; i++) {
994  pInstance->spiRXBuffer[i] = 0u;
995  }
996 
997  for (uint32_t i = 0u; i < MXM_SPI_TX_BUFFER_LENGTH; i++) {
998  pInstance->spiTXBuffer[i] = 0u;
999  }
1000 }
1001 
1002 /*========== Externalized Static Function Implementations (Unit Test) =======*/
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:248
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:126
#define FAS_STATIC_ASSERT(cond, msg)
Definition: fassert.h:282
STD_RETURN_TYPE_e
Definition: fstd_types.h:81
@ STD_NOT_OK
Definition: fstd_types.h:83
@ STD_OK
Definition: fstd_types.h:82
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:76
static void MXM_41BStateHandlerClearTransmitBuffer(MXM_41B_INSTANCE_s *pInstance)
state handler for "clear transmit buffer"
Definition: mxm_17841b.c:769
static void MXM_41BStateHandlerIdle(MXM_41B_INSTANCE_s *pInstance)
state handler for "idle"
Definition: mxm_17841b.c:542
static void MXM_41BStateHandlerClearReceiveBuffer(MXM_41B_INSTANCE_s *pInstance)
state handler for "clear receive buffer"
Definition: mxm_17841b.c:755
static void MXM_41BStateHandlerUartTransaction(MXM_41B_INSTANCE_s *pInstance)
state handler for "uart transaction"
Definition: mxm_17841b.c:586
static void MXM_41BStateHandlerWriteConfAndIntRegister(MXM_41B_INSTANCE_s *pInstance)
state handler for "write conf and int register"
Definition: mxm_17841b.c:549
static void MXM_41BStateHandlerReadStatusRegister(MXM_41B_INSTANCE_s *pInstance)
state handler for "read status register"
Definition: mxm_17841b.c:560
static void MXM_41BStateHandlerGetVersion(MXM_41B_INSTANCE_s *pInstance)
state handler for "get version"
Definition: mxm_17841b.c:511
static void MXM_41BStateHandlerCheckFmea(MXM_41B_INSTANCE_s *pInstance)
state handler for "check fmea"
Definition: mxm_17841b.c:722
static void MXM_41BStateHandlerInit(MXM_41B_INSTANCE_s *pInstance)
init state handler
Definition: mxm_17841b.c:431
STD_RETURN_TYPE_e MXM_41BSetStateRequest(MXM_41B_INSTANCE_s *pInstance, MXM_STATEMACH_41B_e state, uint16_t *pPayload, uint8_t payloadLength, uint8_t extendMessageBytes, uint16_t *pRxBuffer, uint16_t rxBufferLength, MXM_41B_STATE_REQUEST_STATUS_e *processed)
Set state transition for MAX17841B-state-machine.
Definition: mxm_17841b.c:784
void MXM_41BStateMachine(MXM_41B_INSTANCE_s *pInstance)
Execute state-machine for the MAX17841B.
Definition: mxm_17841b.c:927
static STD_RETURN_TYPE_e MXM_41BRegisterWrite(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_ADD_t command, const uint8_t *const kpkPayload, uint8_t lengthPayload)
Write one or multiple registers of MAX17841B.
Definition: mxm_17841b.c:286
STD_RETURN_TYPE_e MXM_41BWriteRegisterFunction(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_FUNCTION_e registerFunction, MXM_41B_REG_BIT_VALUE value)
Write a register function.
Definition: mxm_17841b.c:846
static STD_RETURN_TYPE_e MXM_41BConfigRegisterWrite(MXM_41B_INSTANCE_s *pInstance)
Write the config register of MAX17841B.
Definition: mxm_17841b.c:350
static void MXM_41BTransitionToIdleError(MXM_41B_INSTANCE_s *pInstance)
Transition into idle, mark as an error occurred.
Definition: mxm_17841b.c:410
static void MXM_41BInitializeRegisterCopies(MXM_41B_INSTANCE_s *pInstance)
Reset register copies to default.
Definition: mxm_17841b.c:419
static STD_RETURN_TYPE_e MXM_41BRegisterRead(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_ADD_t command, uint16_t *pRxBuffer, uint8_t length)
Read one or multiple registers of MAX17841B.
Definition: mxm_17841b.c:323
#define MXM_41B_CONFIG_REGISTER_LENGTH
Definition: mxm_17841b.c:93
#define MXM_41B_BIT_MASK_HIGH_NIBBLE
Definition: mxm_17841b.c:72
#define MXM_41B_BIT_MASK_ONE_BYTE
Definition: mxm_17841b.c:75
void MXM_41BInitializeStateStruct(MXM_41B_INSTANCE_s *pInstance)
Initializes the state struct with default values.
Definition: mxm_17841b.c:973
static void MXM_41BTransitionToIdleSuccess(MXM_41B_INSTANCE_s *pInstance)
Transition into idle, mark as successful.
Definition: mxm_17841b.c:401
STD_RETURN_TYPE_e MXM_41BReadRegisterFunction(const MXM_41B_INSTANCE_s *const kpkInstance, MXM_41B_REG_FUNCTION_e registerFunction, MXM_41B_REG_BIT_VALUE *pValue)
Read the value of a register function.
Definition: mxm_17841b.c:892
static STD_RETURN_TYPE_e MXM_41BBufferWrite(MXM_41B_INSTANCE_s *pInstance, const uint16_t *const kpkMessage, uint8_t messageLength, uint8_t extendMessage)
Write a buffer transaction to MAX17841B.
Definition: mxm_17841b.c:370
#define MXM_41B_BIT_SHIFT_HALF_BYTE
Definition: mxm_17841b.c:66
#define MXM_41B_BRIDGE_RESET_TIME_MS
Definition: mxm_17841b.c:86
#define MXM_41B_WAIT_COUNTER_THRESHOLD
Definition: mxm_17841b.c:78
#define MXM_41B_BIT_MASK_LOW_NIBBLE
Definition: mxm_17841b.c:69
Headers for the driver for the MAX17841B ASCI and MAX1785x monitoring chip.
#define MXM_SPI_TX_BUFFER_LENGTH
SPI TX buffer length.
Definition: mxm_17841b.h:76
MXM_STATEMACH_41B_e
States of the MAX17841B state-machine.
Definition: mxm_17841b.h:84
@ MXM_STATEMACH_41B_MAXSTATE
Definition: mxm_17841b.h:95
@ MXM_STATEMACH_41B_GET_VERSION
Definition: mxm_17841b.h:89
@ MXM_STATEMACH_41B_CLEAR_RECEIVE_BUFFER
Definition: mxm_17841b.h:93
@ MXM_STATEMACH_41B_CLEAR_TRANSMIT_BUFFER
Definition: mxm_17841b.h:94
@ MXM_STATEMACH_41B_UNINITIALIZED
Definition: mxm_17841b.h:85
@ MXM_STATEMACH_41B_INIT
Definition: mxm_17841b.h:86
@ MXM_STATEMACH_41B_WRITE_CONF_AND_INT_REGISTER
Definition: mxm_17841b.h:90
@ MXM_STATEMACH_41B_CHECK_FMEA
Definition: mxm_17841b.h:88
@ MXM_STATEMACH_41B_READ_STATUS_REGISTER
Definition: mxm_17841b.h:91
@ MXM_STATEMACH_41B_IDLE
Definition: mxm_17841b.h:87
@ MXM_STATEMACH_41B_UART_TRANSACTION
Definition: mxm_17841b.h:92
@ MXM_41B_FMEA_REQUEST_REGISTER
Definition: mxm_17841b.h:108
@ MXM_41B_INIT_RESET_BRIDGE_IC
Definition: mxm_17841b.h:103
@ MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_WRITE
Definition: mxm_17841b.h:118
@ MXM_41B_VERSION_VERIFY
Definition: mxm_17841b.h:111
@ MXM_41B_UART_READ_RX_SPACE
Definition: mxm_17841b.h:113
@ MXM_41B_INIT_CHECK_INITIALIZATION
Definition: mxm_17841b.h:107
@ MXM_41B_FMEA_VERIFY
Definition: mxm_17841b.h:109
@ MXM_41B_UART_READ_BACK_RECEIVE_BUFFER_SAVE
Definition: mxm_17841b.h:120
@ MXM_41B_VERSION_REQUEST_REGISTER
Definition: mxm_17841b.h:110
@ MXM_41B_ENTRY_SUBSTATE
Definition: mxm_17841b.h:102
@ MXM_41B_UART_WRITE_LOAD_QUEUE
Definition: mxm_17841b.h:115
@ MXM_41B_UART_READ_LOAD_QUEUE
Definition: mxm_17841b.h:116
@ MXM_41B_INIT_START_BRIDGE_IC
Definition: mxm_17841b.h:104
@ MXM_41B_UART_READ_RX_SPACE_PARSE
Definition: mxm_17841b.h:114
@ MXM_41B_INIT_READ_CONFIG_REGISTERS
Definition: mxm_17841b.h:106
@ MXM_41B_UART_VERIFY_LOAD_QUEUE_AND_TRANSMIT
Definition: mxm_17841b.h:117
@ MXM_41B_READ_STATUS_REGISTER_SEND
Definition: mxm_17841b.h:121
@ MXM_41B_READ_STATUS_REGISTER_PROCESS
Definition: mxm_17841b.h:122
@ MXM_41B_INIT_WRITE_DEFAULT_VALUES
Definition: mxm_17841b.h:105
@ MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_READ_AND_READ_BACK_RCV_BUF
Definition: mxm_17841b.h:119
#define MXM_SPI_RX_BUFFER_LENGTH
Definition: mxm_17841b.h:79
MXM_41B_REG_FUNCTION_e
Register functions.
Definition: mxm_17841b.h:141
@ MXM_41B_REG_FUNCTION_RX_BUSY_STATUS
Definition: mxm_17841b.h:142
@ MXM_41B_REG_FUNCTION_RX_EMPTY_STATUS
Definition: mxm_17841b.h:145
@ MXM_41B_REG_FUNCTION_RX_STOP_STATUS
Definition: mxm_17841b.h:144
@ MXM_41B_REG_FUNCTION_RX_OVERFLOW_STATUS
Definition: mxm_17841b.h:143
@ MXM_41B_REG_FUNCTION_TX_PREAMBLES
Definition: mxm_17841b.h:146
@ MXM_41B_REG_FUNCTION_RX_ERROR_INT
Definition: mxm_17841b.h:148
@ MXM_41B_REG_FUNCTION_KEEP_ALIVE
Definition: mxm_17841b.h:147
@ MXM_41B_REG_FUNCTION_RX_OVERFLOW_INT
Definition: mxm_17841b.h:149
MXM_41B_STATE_REQUEST_STATUS_e
Request status of MAX17841B states.
Definition: mxm_17841b.h:131
@ MXM_41B_STATE_ERROR
Definition: mxm_17841b.h:135
@ MXM_41B_STATE_UNPROCESSED
Definition: mxm_17841b.h:133
@ MXM_41B_STATE_PROCESSED
Definition: mxm_17841b.h:134
Register map of the MAX17841 bridge IC.
#define MXM_REG_RX_INTERRUPT_ENABLE_W
RX interrupt enable register write address.
#define MXM_BUF_RD_LD_Q_0
Read load queue starting from location 0.
#define MXM_REG_RX_SPACE_R
RX space register read address.
#define MXM_BUF_CLR_RX_BUF
Reset receive buffer and pointers to default state.
#define MXM_REG_FMEA_R
FMEA register read address.
#define MXM_REG_RX_INTERRUPT_ENABLE_R
RX interrupt enable register read address.
#define MXM_BUF_RD_NXT_MSG
Read receive buffer starting at the oldest unread message.
#define MXM_REG_RX_STATUS_R
RX status register read address.
#define MXM_REG_MODEL_R
Model register read address.
#define MXM_BUF_WR_LD_Q_0
Write load queue starting from location 0.
#define MXM_BUF_CLR_TX_BUF
Reset transmit buffer to default state and clear TX_Q and LD_Q.
#define MXM_BUF_WR_NXT_LD_Q_0
Select next load queue and write starting from location 0.
uint8_t MXM_41B_REG_ADD_t
MAX17841B register addresses.
MXM_41B_REG_BIT_VALUE mxm_41bWriteValue(MXM_41B_REG_BIT_VALUE value, uint8_t numberOfBits, MXM_41B_REG_BITS shift, uint8_t reg)
write a value to a register supplied as variable
MXM_41B_REG_BIT_VALUE mxm_41bReadValue(uint8_t reg, uint8_t numberOfBits, MXM_41B_REG_BITS position)
read a value from a register supplied as variable
Bit extraction function for MXM_17841b.
#define MXM_41B_KEEP_ALIVE
#define MXM_41B_RX_BUSY_STATUS
#define MXM_41B_REG_FALSE
#define MXM_41B_RX_EMPTY_STATUS
#define MXM_41B_RX_OVERFLOW_STATUS
uint8_t MXM_41B_REG_BIT_VALUE
Bit-values for registers.
#define MXM_41B_RX_STOP_STATUS
#define MXM_41B_RX_OVERFLOW_INT_ENABLE
#define MXM_41B_RX_ERROR
#define MXM_41B_TX_PREAMBLES
#define MXM_41B_REG_TRUE
STD_RETURN_TYPE_e MXM_ReceiveData(uint16_t *txBuffer, uint16_t *rxBuffer, uint16_t length)
Send and Receive data over SPI.
Definition: mxm_cfg.c:97
STD_RETURN_TYPE_e MXM_GetSPIStateReady(void)
Return whether SPI interface is ready.
Definition: mxm_cfg.c:84
void MXM_ShutDownBridgeIc(void)
Pulls the shutdown of the bridge IC low.
Definition: mxm_cfg.c:107
void MXM_EnableBridgeIc(void)
Pulls the shutdown of the bridge IC high.
Definition: mxm_cfg.c:111
STD_RETURN_TYPE_e MXM_SendData(uint16_t *txBuffer, uint16_t length)
Transmit data over SPI.
Definition: mxm_cfg.c:88
#define MXM_41B_CONFIG_3_DEFAULT_VALUE
Definition: mxm_cfg.h:104
#define MXM_41B_CONFIG_1_DEFAULT_VALUE
Definition: mxm_cfg.h:92
#define MXM_41B_CONFIG_2_DEFAULT_VALUE
Definition: mxm_cfg.h:98
#define MXM_41B_RX_INT_ENABLE_DEFAULT_VALUE
Definition: mxm_cfg.h:81
#define MXM_41B_RX_INT_FLAG_DEFAULT_VALUE
Definition: mxm_cfg.h:83
#define MXM_41B_TX_INT_ENABLE_DEFAULT_VALUE
Definition: mxm_cfg.h:82
#define MXM_41B_TX_INT_FLAG_DEFAULT_VALUE
Definition: mxm_cfg.h:84
bool OS_CheckTimeHasPassed(uint32_t oldTimeStamp_ms, uint32_t timeToPass_ms)
This function checks if timeToPass has passed since the last timestamp to now.
Definition: os.c:144
Declaration of the OS wrapper interface.
uint32_t OS_GetTickCount(void)
Returns OS based system tick value.
Definition: os_freertos.c:139
Struct for the state-variable of state-machine.
Definition: mxm_17841b.h:158
uint8_t regRXIntEnable
Definition: mxm_17841b.h:168
uint16_t * pRxBuffer
Definition: mxm_17841b.h:163
uint16_t * pPayload
Definition: mxm_17841b.h:161
uint8_t regTXIntEnable
Definition: mxm_17841b.h:169
uint8_t hwMaskRevision
Definition: mxm_17841b.h:178
uint16_t rxBufferLength
Definition: mxm_17841b.h:164
MXM_41B_STATE_REQUEST_STATUS_e * processed
Definition: mxm_17841b.h:165
uint16_t spiRXBuffer[MXM_SPI_RX_BUFFER_LENGTH]
Definition: mxm_17841b.h:180
uint16_t spiTXBuffer[MXM_SPI_TX_BUFFER_LENGTH]
Definition: mxm_17841b.h:181
uint32_t shutdownTimeStamp
Definition: mxm_17841b.h:179
MXM_41B_SUBSTATES_e substate
Definition: mxm_17841b.h:160
MXM_STATEMACH_41B_e state
Definition: mxm_17841b.h:159
uint8_t extendMessageBytes
Definition: mxm_17841b.h:166
uint8_t payloadLength
Definition: mxm_17841b.h:162