foxBMS - Unit Tests  1.4.0
The foxBMS Unit Tests API Documentation
mxm_41b_register_map.h
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41 
42 /**
43  * @file mxm_41b_register_map.h
44  * @author foxBMS Team
45  * @date 2020-06-25 (date of creation)
46  * @updated 2022-07-28 (date of last update)
47  * @version v1.4.0
48  * @ingroup DRIVERS
49  * @prefix MXM
50  *
51  * @brief Register map of the MAX17841 bridge IC
52  *
53  */
54 
55 #ifndef FOXBMS__MXM_41B_REGISTER_MAP_H_
56 #define FOXBMS__MXM_41B_REGISTER_MAP_H_
57 
58 /*========== Includes =======================================================*/
59 
60 /*========== Macros and Definitions =========================================*/
61 /**
62  * @brief Type for MAX17841B buffer transaction commands
63  *
64  * SPI commands for buffer transactions of the MAX17841B.
65  */
66 typedef uint8_t MXM_41B_BUF_CMD_t;
67 
68 /**
69  * @brief MAX17841B register addresses
70  *
71  * Register addresses for the MAX17841B.
72  * Valid register addresses range from 0x01 to 0x1B
73  * and 0x95 to 0x9B
74  * Odd addresses are read addresses and even addresses are
75  * write addresses. Read-only registers have no write address.
76  */
77 typedef uint8_t MXM_41B_REG_ADD_t;
78 
79 /* AXIVION Disable Style MisraC2012-2.5: For completeness, this section lists all register addresses even though the driver does not use them. */
80 /**
81  * @brief Reset transmit buffer to default state and clear TX_Q and LD_Q
82  */
83 #define MXM_BUF_CLR_TX_BUF ((MXM_41B_BUF_CMD_t)0x20u)
84 
85 /**
86  * @brief Read receive buffer starting at RX_RD_Pointer
87  */
88 #define MXM_BUF_RD_MSG ((MXM_41B_BUF_CMD_t)0x91u)
89 
90 /**
91  * @brief Read receive buffer starting at the oldest unread message
92  */
93 #define MXM_BUF_RD_NXT_MSG ((MXM_41B_BUF_CMD_t)0x93u)
94 
95 /**
96  * @brief Select next load queue and write starting from location 0
97  */
98 #define MXM_BUF_WR_NXT_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xB0u)
99 
100 /**
101  * @brief Select next load queue and write starting from location 1
102  */
103 #define MXM_BUF_WR_NXT_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xB2u)
104 
105 /**
106  * @brief Select next load queue and write starting from location 2
107  */
108 #define MXM_BUF_WR_NXT_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xB4u)
109 
110 /**
111  * @brief Select next load queue and write starting from location 3
112  */
113 #define MXM_BUF_WR_NXT_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xB6u)
114 
115 /**
116  * @brief Select next load queue and write starting from location 4
117  */
118 #define MXM_BUF_WR_NXT_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xB8u)
119 
120 /**
121  * @brief Select next load queue and write starting from location 5
122  */
123 #define MXM_BUF_WR_NXT_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xBAu)
124 
125 /**
126  * @brief Select next load queue and write starting from location 6
127  */
128 #define MXM_BUF_WR_NXT_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xBCu)
129 
130 /**
131  * @brief Write load queue starting from location 0
132  */
133 #define MXM_BUF_WR_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xC0u)
134 
135 /**
136  * @brief Write load queue starting from location 1
137  */
138 #define MXM_BUF_WR_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xC2u)
139 
140 /**
141  * @brief Write load queue starting from location 2
142  */
143 #define MXM_BUF_WR_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xC4u)
144 
145 /**
146  * @brief Write load queue starting from location 3
147  */
148 #define MXM_BUF_WR_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xC6u)
149 
150 /**
151  * @brief Write load queue starting from location 4
152  */
153 #define MXM_BUF_WR_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xC8u)
154 
155 /**
156  * @brief Write load queue starting from location 5
157  */
158 #define MXM_BUF_WR_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xCAu)
159 
160 /**
161  * @brief Write load queue starting from location 6
162  */
163 #define MXM_BUF_WR_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xCCu)
164 
165 /**
166  * @brief Read load queue starting from location 0
167  */
168 #define MXM_BUF_RD_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xC1u)
169 
170 /**
171  * @brief Read load queue starting from location 1
172  */
173 #define MXM_BUF_RD_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xC3u)
174 
175 /**
176  * @brief Read load queue starting from location 2
177  */
178 #define MXM_BUF_RD_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xC5u)
179 
180 /**
181  * @brief Read load queue starting from location 3
182  */
183 #define MXM_BUF_RD_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xC7u)
184 
185 /**
186  * @brief Read load queue starting from location 4
187  */
188 #define MXM_BUF_RD_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xC9u)
189 
190 /**
191  * @brief Read load queue starting from location 5
192  */
193 #define MXM_BUF_RD_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xCBu)
194 
195 /**
196  * @brief Read load queue starting from location 6
197  */
198 #define MXM_BUF_RD_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xCDu)
199 
200 /**
201  * @brief Reset receive buffer and pointers to default state
202  */
203 #define MXM_BUF_CLR_RX_BUF ((MXM_41B_BUF_CMD_t)0xE0u)
204 
205 /**
206  * @brief RX status register read address
207  */
208 #define MXM_REG_RX_STATUS_R ((MXM_41B_REG_ADD_t)0x01u)
209 
210 /**
211  * @brief TX status register read address
212  */
213 #define MXM_REG_TX_STATUS_R ((MXM_41B_REG_ADD_t)0x03u)
214 
215 /**
216  * @brief RX interrupt enable register read address
217  */
218 #define MXM_REG_RX_INTERRUPT_ENABLE_R ((MXM_41B_REG_ADD_t)0x05u)
219 
220 /**
221  * @brief RX interrupt enable register write address
222  */
223 #define MXM_REG_RX_INTERRUPT_ENABLE_W ((MXM_41B_REG_ADD_t)0x04u)
224 
225 /**
226  * @brief TX interrupt enable register read address
227  */
228 #define MXM_REG_TX_INTERRUPT_ENABLE_R ((MXM_41B_REG_ADD_t)0x07u)
229 
230 /**
231  * @brief TX interrupt enable register write address
232  */
233 #define MXM_REG_TX_INTERRUPT_ENABLE_W ((MXM_41B_REG_ADD_t)0x06u)
234 
235 /**
236  * @brief RX interrupt flags register read address
237  */
238 #define MXM_REG_RX_INTERRUPT_FLAGS_R ((MXM_41B_REG_ADD_t)0x09u)
239 
240 /**
241  * @brief RX interrupt flags register write address
242  */
243 #define MXM_REG_RX_INTERRUPT_FLAGS_W ((MXM_41B_REG_ADD_t)0x08u)
244 
245 /**
246  * @brief TX interrupt flags register read address
247  */
248 #define MXM_REG_TX_INTERRUPT_FLAGS_R ((MXM_41B_REG_ADD_t)0x0Bu)
249 
250 /**
251  * @brief TX interrupt flags register write address
252  */
253 #define MXM_REG_TX_INTERRUPT_FLAGS_W ((MXM_41B_REG_ADD_t)0x0Au)
254 
255 /**
256  * @brief Configuration 1 register read address
257  */
258 #define MXM_REG_CONFIGURATION_1_R ((MXM_41B_REG_ADD_t)0x0Du)
259 
260 /**
261  * @brief Configuration 1 register write address
262  */
263 #define MXM_REG_CONFIGURATION_1_W ((MXM_41B_REG_ADD_t)0x0Cu)
264 
265 /**
266  * @brief Configuration 2 register read address
267  */
268 #define MXM_REG_CONFIGURATION_2_R ((MXM_41B_REG_ADD_t)0x0Fu)
269 
270 /**
271  * @brief Configuration 2 register write address
272  */
273 #define MXM_REG_CONFIGURATION_2_W ((MXM_41B_REG_ADD_t)0x0Eu)
274 
275 /**
276  * @brief Configuration 3 register read address
277  */
278 #define MXM_REG_CONFIGURATION_3_R ((MXM_41B_REG_ADD_t)0x11u)
279 
280 /**
281  * @brief Configuration 3 register write address
282  */
283 #define MXM_REG_CONFIGURATION_3_W ((MXM_41B_REG_ADD_t)0x10u)
284 
285 /**
286  * @brief FMEA register read address
287  */
288 #define MXM_REG_FMEA_R ((MXM_41B_REG_ADD_t)0x13u)
289 
290 /**
291  * @brief Model register read address
292  */
293 #define MXM_REG_MODEL_R ((MXM_41B_REG_ADD_t)0x15u)
294 
295 /**
296  * @brief Version register read address
297  */
298 #define MXM_REG_VERSION_R ((MXM_41B_REG_ADD_t)0x17u)
299 
300 /**
301  * @brief RX byte register read address
302  */
303 #define MXM_REG_RX_BYTE_R ((MXM_41B_REG_ADD_t)0x19u)
304 
305 /**
306  * @brief RX space register read address
307  */
308 #define MXM_REG_RX_SPACE_R ((MXM_41B_REG_ADD_t)0x1Bu)
309 
310 /**
311  * @brief TX queue selects register read address
312  */
313 #define MXM_REG_TX_QUEUE_SELECTS_R ((MXM_41B_REG_ADD_t)0x95u)
314 
315 /**
316  * @brief RX read pointer register read address
317  */
318 #define MXM_REG_RX_READ_POINTER_R ((MXM_41B_REG_ADD_t)0x97u)
319 
320 /**
321  * @brief RX write pointer register read address
322  */
323 #define MXM_REG_RX_WRITE_POINTER_R ((MXM_41B_REG_ADD_t)0x99u)
324 
325 /**
326  * @brief RX next message register read address
327  */
328 #define MXM_REG_RX_NEXT_MESSAGE_R ((MXM_41B_REG_ADD_t)0x9Bu)
329 
330 /* AXIVION Enable Style MisraC2012-2.5: */
331 
332 /*========== Extern Constant and Variable Declarations ======================*/
333 
334 /*========== Extern Function Prototypes =====================================*/
335 
336 /*========== Externalized Static Functions Prototypes (Unit Test) ===========*/
337 
338 #endif /* FOXBMS__MXM_41B_REGISTER_MAP_H_ */
uint8_t MXM_41B_BUF_CMD_t
Type for MAX17841B buffer transaction commands.
uint8_t MXM_41B_REG_ADD_t
MAX17841B register addresses.