foxBMS - Unit Tests  1.2.0
The foxBMS Unit Tests API Documentation
nxpfs85xx.c File Reference

Driver for the SBC module. More...

#include "nxpfs85xx.h"
#include "HL_gio.h"
#include "HL_system.h"
#include "diag.h"
#include "fram.h"
#include "fsystem.h"
#include "io.h"
#include "masterinfo.h"
#include "mcu.h"
Include dependency graph for nxpfs85xx.c:

Go to the source code of this file.

Typedefs

typedef enum SBC_INIT_PHASE SBC_INIT_PHASE_e
 

Enumerations

enum  SBC_INIT_PHASE { SBC_UNINITIALIZED , SBC_FIN_TEST , SBC_RSTB_ASSERTION_TEST , SBC_INITIALIZED }
 

Functions

static STD_RETURN_TYPE_e SBC_CheckRegisterValues (uint32_t registerValue, uint32_t expectedRegisterValue)
 Checks register value against expected value. More...
 
static void SBC_UpdateRegister (FS85xx_STATE_s *pInstance, bool isFailSafe, uint32_t registerAddress, uint32_t registerValue)
 Updates register values. More...
 
static STD_RETURN_TYPE_e SBC_ReadBackRegister (FS85xx_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress)
 Reads SBC register value. More...
 
static STD_RETURN_TYPE_e SBC_WriteRegisterFsInit (FS85xx_STATE_s *pInstance, uint8_t registerAddress, uint16_t registerValue)
 Write to fail-safe register. More...
 
static STD_RETURN_TYPE_e SBC_WriteBackRegisterFsInit (FS85xx_STATE_s *pInstance, uint8_t registerAddress, uint16_t registerValue)
 Write to fail-safe register. More...
 
static STD_RETURN_TYPE_e SBC_ClearRegisterFlags (FS85xx_STATE_s *pInstance, uint8_t registerAddress, bool isFailSafe, uint16_t registerValue)
 Clears flags in register. More...
 
static STD_RETURN_TYPE_e SBC_ReadBackAllRegisters (FS85xx_STATE_s *pInstance)
 
static STD_RETURN_TYPE_e SBC_PerformPathCheckRSTB (FS85xx_STATE_s *pInstance)
 Perform RSTB safety path check. More...
 
static STD_RETURN_TYPE_e SBC_PerformPathCheckFS0B (FS85xx_STATE_s *pInstance)
 Perform FS0B safety path check. More...
 
STD_RETURN_TYPE_e FS85X_InitFS (FS85xx_STATE_s *pInstance)
 Configures SBC during INIT_FS phase. More...
 
STD_RETURN_TYPE_e FS85X_Init_ReqWDGRefreshes (FS85xx_STATE_s *pInstance, uint8_t *requiredWatchdogRefreshes)
 Calculates the number of required watchdog refresh to reset fault error counter. More...
 
STD_RETURN_TYPE_e FS85X_CheckFaultErrorCounter (FS85xx_STATE_s *pInstance)
 Checks if fault error counter is zero. More...
 
STD_RETURN_TYPE_e FS85X_SafetyPathChecks (FS85xx_STATE_s *pInstance)
 Performs SBC safety path checks. More...
 
UNIT_TEST_WEAK_IMPL fs8x_status_t MCU_SPI_TransferData (SPI_INTERFACE_CONFIG_s *pSpiInterface, uint8_t *txFrame, uint16_t frameLengthBytes, uint8_t *rxFrame)
 This function transfers single frame through blocking SPI communication in both directions. MCU specific. More...
 
STD_RETURN_TYPE_e SBC_TriggerWatchdog (FS85xx_STATE_s *pInstance)
 Trigger watchdog. More...
 

Variables

FS85xx_STATE_s fs85xx_mcuSupervisor
 

Detailed Description

Driver for the SBC module.

SPDX-License-Identifier: BSD-3-Clause

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

We kindly request you to use one or more of the following phrases to refer to foxBMS in your hardware, software, documentation or advertising materials:

  • ″This product uses parts of foxBMS®″
  • ″This product includes parts of foxBMS®″
  • ″This product is derived from foxBMS®″
Author
foxBMS Team
Date
2020-03-18 (date of creation)
Updated
2021-07-14 (date of last update)
Prefix
SBC

It must always be used when creating new c source files.

Definition in file nxpfs85xx.c.

Typedef Documentation

◆ SBC_INIT_PHASE_e

Enumeration Type Documentation

◆ SBC_INIT_PHASE

Enumerator
SBC_UNINITIALIZED 
SBC_FIN_TEST 
SBC_RSTB_ASSERTION_TEST 
SBC_INITIALIZED 

Definition at line 72 of file nxpfs85xx.c.

Function Documentation

◆ FS85X_CheckFaultErrorCounter()

STD_RETURN_TYPE_e FS85X_CheckFaultErrorCounter ( FS85xx_STATE_s pInstance)

Checks if fault error counter is zero.

Parameters
[in,out]pInstanceSBC instance where fault error counter is checked
Returns
STD_OK if fault error counter equals zero, otherwise STD_NOT_OK

Definition at line 898 of file nxpfs85xx.c.

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◆ FS85X_Init_ReqWDGRefreshes()

STD_RETURN_TYPE_e FS85X_Init_ReqWDGRefreshes ( FS85xx_STATE_s pInstance,
uint8_t *  requiredWatchdogRefreshes 
)

Calculates the number of required watchdog refresh to reset fault error counter.

Parameters
[in,out]pInstanceSBC instance that is initialized
[out]requiredWatchdogRefreshesnumber of required good watchdog refreshes
Returns
STD_OK if required watchdog refreshes were calculated successfully, otherwise STD_NOT_OK

Clear the fault error counter to 0 with consecutive good WD refreshes. The watchdog refresh counter is used to decrement the fault error counter. Each time the watchdog is properly refreshed, the watchdog refresh counter is incremented by '1'. Each time the watchdog refresh counter reaches its maximum value ('6' by default) and if next WD refresh is also good, the fault error counter is decremented by '1'. Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog, the watchdog refresh counter is reset to '0'.

Read out FS_I_WD_CFG register to get watchdog refresh counter limit and value

Get refresh counter value

Get refresh counter limit register value

Get fault error counter

Get number of required watchdog refreshes to clear fault error counter to 0

Definition at line 844 of file nxpfs85xx.c.

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◆ FS85X_InitFS()

STD_RETURN_TYPE_e FS85X_InitFS ( FS85xx_STATE_s pInstance)

Configures SBC during INIT_FS phase.

Checks first if SBC currently is in INIT_FS phase and if not transfers SBC back into INIT_FS. Verifies basic checks, configures fail-safe registers and closes INIT_FS afterwards.

Parameters
[in,out]pInstanceSBC instance that is initialized
Returns
STD_OK if all checks were successful and SBC configured correctly, otherwise STD_NOT_OK

First: Verify following conditions:

  1. Verify LBIST (logical-built-in-self-test) and ABIST1 (analog-built-in-self-test1) are pass
  2. Verify Debug mode is not activated
  3. Verify there is no OTP CRC error
  4. Verify PGOOD was released: PGOOD is connected to power-on-reset of the MCU

Second: Configure FS_I and FS_I_NOT registers

  • Write the desired data in the FS_I_Register_A (DATA)
  • Write the opposite in the FS_I_NOT_Register_A (DATA_NOT)
  • Only the utility bits must be inverted in the DATA_NOT content. The RESERVED bits are not considered and can be written at '0'. If the comparison result is correct, then the REG_CORRUPT is set to '0'. If the comparison result is wrong, then the REG_CORRUPT bit is set to '1'. The REG_CORRUPT monitoring is active as soon as the INIT_FS is closed by the first good watchdog refresh. INIT_FS must be closed by the first good watchdog refresh before 256ms timeout.
  1. Configure VCOREMON_OV_UV impact on RSTB and FS0B
  2. Configure VDDIO_OV_UV impact on RSTB and FS0B
  3. Configure VMONx_OV_UV impact on RSTB and FS0B
  4. Configure ABIST2 assignment
  5. Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and FS0B. Ensure that the configuration does not violate the FTTI requirement at system level.
  6. Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value
  7. Configure the RSTB pulse duration
  8. Configure MCU FCCU error monitoring and its impact on RSTB and FS0B
  9. Configure Ext. IC error monitoring and its impact on RSTB and FS0B 10.Configure FS0B short to high impact on RSTB

Third: Execute

  1. Close INIT_FS by sending the first good WD refresh
  2. Execute ABIST2 and verify it is pass
  3. Clear all the flags by writing in FS_DIAG_SAFETY, FS_OVUVREG_STATUS
  4. Clear the fault error counter to 0 with consecutive good WD refresh
  5. Perform RSTB path check (repeat steps 1 to 4 after RSTB is released)
  6. Release FS0B pin
  7. Perform FS0B safety path check
  8. Refresh the WD according to its configuration
  9. Check FS_GRL_FLAGS register after each WD refresh

The FS85 is now ready. If everything is OK for the MCU, it can release its own safety path and the ECU starts.

1.: Verify LBIST and ABIST1

Read FS STATES register

2.: Check if debug mode is active

3.: Verify that no OPT CRC error

-----— Second: Configure fail-safe init registers ---------------—

Check if SBC is in FS_INIT state, if not switch SBC in FS_INIT state. Specific configurations can only be done in FS_INIT state

1.: Configure VCOREMON_OV_UV impact on RSTB and FS0B

2.: Configure VDDIO_OV_UV impact on RSTB and FS0B

4.: Configure ABIST2 assignment

Select VCOREMON_OV options:

  • FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B
  • FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B_RSTB

Select VCOREMON_UV options:

  • FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B
  • FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B_RSTB

Select VDDIO_OV options:

  • FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B
  • FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B_RSTB

Select VDDIO_UV options:

  • FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B
  • FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B_RSTB

Select ABIST2 options:

  • VCOREMON
    • FS8X_FS_I_VCOREMON_ABIST2_NO_ABIST
    • FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST
  • VDDIO
    • FS8X_FS_I_VDDIO_ABIST2_NO_ABIST
    • FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST
  • VMONx (VMON1 - VMON4)
    • FS8X_FS_I_VMONx_ABIST2_NO_ABIST
    • FS8X_FS_I_VMONx_ABIST2_VMONx_BIST

3.: Configure VMONx_OV_UV impact on RSTB and FS0B

Select VMONx_OV options:

  • FS8X_FS_I_VMONx_OV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B
  • FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B_RSTB

Select VMONx_UV options:

  • FS8X_FS_I_VMONx_UV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B
  • FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B_RSTB

5.: Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and FS0B. Ensure that the configuration does not violate the FTTI requirement at system level.

WD window period options:

  • FS8X_FS_WD_WINDOW_DISABLE
  • FS8X_FS_WD_WINDOW_xxxxMS

WD window duty cycle options:

  • FS8X_FS_WDW_DC_31_25
  • FS8X_FS_WDW_DC_37_5
  • FS8X_FS_WDW_DC_50
  • FS8X_FS_WDW_DC_62_5
  • FS8X_FS_WDW_DC_68_75

WD fault recovery strategy

  • FS8X_FS_WDW_RECOVERY_DISABLE
  • FS8X_FS_WDW_RECOVERY_xxxxMS

6.: Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value

Configure the RSTB pulse duration

Configure FS0B short to high impact on RSTB

Fault Error Counter limit options:

  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_2
  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_4
  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_6
  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_8

Fault Error Counter impact options:

  • FS8X_FS_I_FLT_ERR_IMPACT_NO_EFFECT
  • FS8X_FS_I_FLT_ERR_IMPACT_FS0B
  • FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB

7.: RSTB pulse duration options:

  • FS8X_FS_I_RSTB_DUR_1MS
  • FS8X_FS_I_RSTB_DUR_10MS

10.: FS0B short to high impact on RSTB options:

  • FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION
  • FS8X_FS_I_FS0B_SC_HIGH_CFG_RESET_ASSERTED

After POR fault-error counter is set to 1 on default, it is reset after two consecutive good WD refreshes. This part of the register is read-only so a write access has no influence. Set this bit for a successful comparison between written and read register value

8.: Configure MCU FCCU error monitoring and its impact on RSTB and FS0B

9.: Configure Ext. IC error monitoring and its impact on RSTB and FS0B

MCU FCCU error monitoring options:

  • Input option:
    • FS8X_FS_I_FCCU_CFG_NO_MONITORING
    • FS8X_FS_I_FCCU_CFG_FCCU1_INPUT
    • FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_INPUT
    • FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_PAIR (bi-stable protocol)
  • Polarity option (independent):
    • FS8X_FS_I_FCCUx_FLT_POL_FCCUx_L
    • FS8X_FS_I_FCCUx_FLT_POL_FCCUx_H
  • Polarity option (bi-stable)
    • FS8X_FS_I_FCCU12_FLT_POL_FCCU1_L_FCCU2_H
    • FS8X_FS_I_FCCU12_FLT_POL_FCCU1_H_FCCU2_L
  • Impact option (independent)
    • FS8X_FS_I_FCCUx_FS_REACT_FS0B
    • FS8X_FS_I_FCCUx_FS_REACT_FS0B_RSTB
  • Impact option (bi-stable)
    • FS8X_FS_I_FCCU12_FS_IMPACT_FS0B
    • FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB

Ext. IC error monitoring options:

  • Polarity options:
    • FS8X_FS_I_ERRMON_FLT_POLARITY_NEGATIVE_EDGE
    • FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE
  • Error acknowledgment time options:
    • FS8X_FS_I_ERRMON_ACK_TIME_1MS
    • FS8X_FS_I_ERRMON_ACK_TIME_8MS
    • FS8X_FS_I_ERRMON_ACK_TIME_16MS
    • FS8X_FS_I_ERRMON_ACK_TIME_32MS
  • Error monitoring impact options:
    • FS8X_FS_I_ERRMON_FS_IMPACT_FS0B
    • FS8X_FS_I_ERRMON_FS_IMPACT_FS0B_RSTB

1.: Close INIT_FS by sending the first good WD refresh

2.: Execute ABIST2 and verify it is pass

ABIST2 is executed automatically after closing of INIT_FS, duration: 1.2ms max

3.: Clear all the flags by writing in FS_DIAG_SAFETY

Flags are cleared by writting '1' to register

Clear all the flags by writing in FS_OVUVREG_STATUS

Flags are cleared by writting '1' to register

Clear flags FLAG1 register

Clear flags FLAG2 register

Read out all registers for debug purpose

Definition at line 461 of file nxpfs85xx.c.

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◆ FS85X_SafetyPathChecks()

STD_RETURN_TYPE_e FS85X_SafetyPathChecks ( FS85xx_STATE_s pInstance)

Performs SBC safety path checks.

Function perform safety path checks for FIN, FS0B and RSTB to ensure that all pins work as expected

Parameters
[in,out]pInstancewhere the safety paths are checked
Returns
STD_OK if safety path check successful, otherwise STD_NOT_OK

Definition at line 910 of file nxpfs85xx.c.

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◆ SBC_CheckRegisterValues()

static STD_RETURN_TYPE_e SBC_CheckRegisterValues ( uint32_t  registerValue,
uint32_t  expectedRegisterValue 
)
static

Checks register value against expected value.

If actual register value equals expected value STD_OK is returned if this is not the case this indicates an error and STD_NOT_OK is returned.

Parameters
[in]registerValueactual register value of interest
[in]expectedRegisterValueexpected register value
Returns
STD_OK if register value equals expected, else STD_NOT_OK

Definition at line 205 of file nxpfs85xx.c.

◆ SBC_ClearRegisterFlags()

static STD_RETURN_TYPE_e SBC_ClearRegisterFlags ( FS85xx_STATE_s pInstance,
uint8_t  registerAddress,
bool  isFailSafe,
uint16_t  registerValue 
)
static

Clears flags in register.

Writes to register, reads back if clear process was successful and afterwards updates register value of passed SBC instance

Parameters
[in,out]pInstanceSBC instance that is updated
[in]registerAddressaddress of register
[in]isFailSafetrue if fail-safe register, false if main register
[in]registerValuevalue that is written into register
Returns
STD_OK if writting was successful, other STD_NOT_OK

Definition at line 426 of file nxpfs85xx.c.

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◆ SBC_PerformPathCheckFS0B()

static STD_RETURN_TYPE_e SBC_PerformPathCheckFS0B ( FS85xx_STATE_s pInstance)
static

Perform FS0B safety path check.

This functions performs a safety path check to make sure external components connected to FS0B are available to bring the safety critical outputs to known levels during operation.

Parameters
[in,out]pInstanceSBC instance for which the FS0B path is checked

Definition at line 1176 of file nxpfs85xx.c.

◆ SBC_PerformPathCheckRSTB()

static STD_RETURN_TYPE_e SBC_PerformPathCheckRSTB ( FS85xx_STATE_s pInstance)
static

Perform RSTB safety path check.

This functions performs a safety path check to make sure external components connected to RSTB are available to bring the safety critical outputs to known levels during operation.

Parameters
[in,out]pInstanceSBC instance for which the RSTB path is checked
Returns
STD_OK if path check was successful, other STD_NOT_OK

Assertion of RSTB pin will trigger reset, check if reset reason was power-cycle. If so, check if short circuit between FIN and RSTB pin exists

First check if FIN is used

Write to NVRAM to determine after reset and if short-circuit between RSTB and FIN present what exactly caused the reset.

MCU SBC is connected to ECLK1 -> privilege mode is required to access register

Last reset was caused by power-cycle

Set level of FIN pin low and check if this generates reset

Pulses longer than 2000ns trigger reset -> wait 10us to check if reset is triggered by short between RSTB and FIN

If we reach this line of code, no reset has taken place. Everything okay. Set level of FIN pin back to high

No further register access required -> leave privilege mode

FIN state okay, no short circuit. Update also in nvram struct

Continue with RSTB assertion test

Power-cycle but no FIN pin used -> continue with RSTB check

Last reset reason was external reset via nRST pin (EXT_RESET) Readout FRAM to determine in which state the SBC was prior to reset

Short-circuit between FIN and RSTB: Do not apply CLK on FIN

Update nvram FIN state

FIN state not okay, but still in SBC init phase after power-cycle continue now with RSTB assertion

Reset was triggered by SPI RSTB assertion test -> continue with SBC init phase

Diagnosis of the RSTB pin/event is available by reading the FS_SAFE_IOs register: RSTB_EVENT bit reports an activation of RSTB pin.

Check RSTB_EVENT if RSTB has been activated

RSTB pin should be sensed high and no RSTB short to high

Reset RSTB_EVENT flag

Update diag flag

RSTB has not been activated but this should have been the case

Reset was not caused by SBC initialization or power-cycle. Continue with SBC init phase as RSTB assertion is only tested after power-cycle occurred

Copy FIN state info from nvram variable into local state variable. This restores lost data from rest or updates local FIN state if short-circuit between FIN and RSTB has been detected

Reset was not caused by power-cycle or SBC. SBC has already been initialized successfully after detected power-cycle. Everything okay. Read FIN state from NVRAM and continue with normal operation

Verify the hardware connection between the MCU reset pin and the FS85 reset pin

Write to NVRAM to determine after reset and if RSTB was asserted correctly

Definition at line 1045 of file nxpfs85xx.c.

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◆ SBC_ReadBackAllRegisters()

static STD_RETURN_TYPE_e SBC_ReadBackAllRegisters ( FS85xx_STATE_s pInstance)
static

Definition at line 1005 of file nxpfs85xx.c.

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◆ SBC_ReadBackRegister()

static STD_RETURN_TYPE_e SBC_ReadBackRegister ( FS85xx_STATE_s pInstance,
bool  isFailSafe,
uint8_t  registerAddress 
)
static

Reads SBC register value.

Reads SBC register value from registerAddress and updates register in SBC state variable if reading was successful

Parameters
[in,out]pInstanceSBC instance that is updated
[in]isFailSafetrue if fail-safe register, false if main register
[in]registerAddressaddress of register that is read from
Returns
STD_OK if reading was successful, otherwise STD_NOT_OK

Definition at line 362 of file nxpfs85xx.c.

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◆ SBC_TriggerWatchdog()

STD_RETURN_TYPE_e SBC_TriggerWatchdog ( FS85xx_STATE_s pInstance)

Trigger watchdog.

Triggers watchdog of passed SBC instance and verify if it was good refresh within the configured window

Parameters
[in,out]pInstanceSBC instance where the watchdog is triggered
Returns
STD_OK if watchdog has been triggered successfully, otherwise STD_NOT_OK

Definition at line 973 of file nxpfs85xx.c.

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◆ SBC_UpdateRegister()

static void SBC_UpdateRegister ( FS85xx_STATE_s pInstance,
bool  isFailSafe,
uint32_t  registerAddress,
uint32_t  registerValue 
)
static

Updates register values.

Updates register value of passed SBC instance with new values

Parameters
[in,out]pInstanceSBC instance that is updated
[in]isFailSafetrue if fail-safe register, false if main register
[in]registerAddressaddress of register that is updated
[in]registerValueregister value

Definition at line 213 of file nxpfs85xx.c.

◆ SBC_WriteBackRegisterFsInit()

static STD_RETURN_TYPE_e SBC_WriteBackRegisterFsInit ( FS85xx_STATE_s pInstance,
uint8_t  registerAddress,
uint16_t  registerValue 
)
static

Write to fail-safe register.

Writes to fail-safe register (can be done during FS_INIT phase only), reads back if write process was successful and afterwards updates register value of passed SBC instance

Parameters
[in,out]pInstanceSBC instance that is updated
[in]registerAddressaddress of register
[in]registerValuevalue that is written into register
Returns
STD_OK if writting was successful, other STD_NOT_OK

Definition at line 396 of file nxpfs85xx.c.

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◆ SBC_WriteRegisterFsInit()

static STD_RETURN_TYPE_e SBC_WriteRegisterFsInit ( FS85xx_STATE_s pInstance,
uint8_t  registerAddress,
uint16_t  registerValue 
)
static

Write to fail-safe register.

Writes to fail-safe register (can be done during FS_INIT phase only)

Parameters
[in]pInstanceSBC instance that is updated
[in]registerAddressaddress of register
[in]registerValuevalue that is written into register
Returns
STD_OK if writting was successful, other STD_NOT_OK

Definition at line 378 of file nxpfs85xx.c.

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Variable Documentation

◆ fs85xx_mcuSupervisor

FS85xx_STATE_s fs85xx_mcuSupervisor
Initial value:
= {
.pSpiInterface = &spi_kSbcMcuInterface,
.configValues.watchdogSeed = FS8x_WD_SEED_DEFAULT,
.configValues.communicationMode = fs8xSPI,
.configValues.i2cAddressOtp = 0,
.fin.finUsed = true,
.fin.finState = STD_NOT_OK,
.fin.pGIOport = &(systemREG1->SYSPC4),
.fin.pin = 0,
.mainRegister = {0},
.fsRegister = {0},
.nvram.data = &fram_sbcInit,
.mode = SBC_NORMAL_MODE,
}
FRAM_SBC_INIT_s fram_sbcInit
Definition: fram_cfg.c:72
@ FRAM_BLOCK_ID_SBC_INIT_STATE
Definition: fram_cfg.h:90
@ STD_NOT_OK
Definition: fstd_types.h:73
@ fs8xSPI
@ SBC_NORMAL_MODE
Definition: nxpfs85xx.h:110
#define FS8x_WD_SEED_DEFAULT
Watchdog seed default value.
Definition: sbc_fs8x.h:59
SPI_INTERFACE_CONFIG_s spi_kSbcMcuInterface
Definition: spi_cfg.c:240

Definition at line 80 of file nxpfs85xx.c.