foxBMS  1.4.0
The foxBMS Battery Management System API Documentation
fram.c
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41 
42 /**
43  * @file fram.c
44  * @author foxBMS Team
45  * @date 2020-03-05 (date of creation)
46  * @updated 2022-07-28 (date of last update)
47  * @version v1.4.0
48  * @ingroup DRIVERS
49  * @prefix FRAM
50  *
51  * @brief Driver for the FRAM module
52  *
53  *
54  */
55 
56 /*========== Includes =======================================================*/
57 #include "fram.h"
58 
59 #include "crc.h"
60 #include "diag.h"
61 #include "io.h"
62 #include "mcu.h"
63 #include "spi.h"
64 
65 /*========== Macros and Definitions =========================================*/
66 
67 /** delay in µs after writing the FRAM */
68 #define FRAM_DELAY_AFTER_WRITE_ENABLE_US (5u)
69 
70 /** control commands for the FRAM */
71 /**@{*/
72 #define FRAM_WRITECOMMAND (0x02u)
73 #define FRAM_READCOMMAND (0x03u)
74 #define FRAM_WRITEENABLECOMMAND (0x06u)
75 /**@}*/
76 
77 /** maximal memory address of the FRAM */
78 #define FRAM_MAX_ADDRESS (0x3FFFFu)
79 
80 /*========== Static Constant and Variable Definitions =======================*/
81 
82 /*========== Extern Constant and Variable Definitions =======================*/
83 
84 /*========== Static Function Prototypes =====================================*/
85 
86 /*========== Static Function Implementations ================================*/
87 
88 /*========== Extern Function Implementations ================================*/
89 
90 extern void FRAM_Initialize(void) {
91  uint32_t address = 0u;
92 
93  /* Reset error flag at startup */
95  /* find address of all variables in FRAM by parsing length of data*/
96  for (uint16_t i = 0u; i < FRAM_BLOCK_MAX; i++) {
97  (fram_base_header[i]).address = address;
98  address += (fram_base_header[i]).datalength + FRAM_CRC_HEADER_SIZE;
99  }
100 
101  /* ASSERT that size of variables does not exceed FRAM size */
102  FAS_ASSERT(!(address > FRAM_MAX_ADDRESS));
103 }
104 
106  STD_RETURN_TYPE_e retVal = STD_OK;
107  for (uint16_t i = 0u; i < FRAM_BLOCK_MAX; i++) {
109  retVal = STD_OK;
110  }
111  }
112  return retVal;
113 }
114 
116  FAS_ASSERT(blockId < FRAM_BLOCK_MAX);
117 
118  uint16_t read = 0u;
119  uint64_t crc = 0u;
121 
122  /* FRAM must use SW Chip Select configuration*/
124 
125  uint32_t address = (fram_base_header[blockId]).address;
126  uint32_t size = (fram_base_header[blockId]).datalength;
127  uint8_t *pWrite = (uint8_t *)(fram_base_header[blockId].blockptr);
128 
129  STD_RETURN_TYPE_e crcRetVal = CRC_CalculateCrc(&crc, pWrite, size);
130 
131  if (crcRetVal == STD_OK) {
133 
134  if (spiRetVal == STD_OK) {
135  /* send write enable command */
137  uint16_t write = FRAM_WRITEENABLECOMMAND;
138  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
141 
142  /* send data to write */
143  /* set chip select low to start transmission */
145 
146  /* send write command */
147  write = FRAM_WRITECOMMAND;
148  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
149 
150  /* send upper part of address */
151  write = (address & 0x3F0000u) >> 16u;
152  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
153 
154  /* send middle part of address */
155  write = (address & 0xFF00u) >> 8u;
156  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
157 
158  /* send lower part of address */
159  write = address & 0xFFu;
160  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
161 
162  /* send CRC */
163  pWrite = (uint8_t *)(&crc);
164  for (uint8_t i = 0u; i < FRAM_CRC_HEADER_SIZE; i++) {
165  write = (uint16_t)(*pWrite);
166  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
167  pWrite++;
168  }
169 
170  pWrite = (uint8_t *)(fram_base_header[blockId].blockptr);
171 
172  /* send data */
173  while (size > 0u) {
174  write = (uint16_t)(*pWrite);
175  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
176  pWrite++;
177  size--;
178  }
179 
180  /* set chip select high to start transmission */
182 
184  } else {
185  retVal = FRAM_ACCESS_SPI_BUSY;
186  }
187  } else {
188  retVal = FRAM_ACCESS_CRC_BUSY;
189  }
190  return retVal;
191 }
192 
194  FAS_ASSERT(blockId < FRAM_BLOCK_MAX);
195 
196  uint16_t read = 0u;
198 
199  /* FRAM must use SW Chip Select configuration*/
201 
203 
204  if (spiRetVal == STD_OK) {
205  uint32_t address = (fram_base_header[blockId]).address;
206  uint32_t size = (fram_base_header[blockId]).datalength;
207 
208  /* get data to be read */
209  /* set chip select low to start transmission */
211 
212  /* send write command */
213  uint16_t write = FRAM_READCOMMAND;
214  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
215 
216  /* send upper part of address */
217  write = (address & 0x3F0000u) >> 16u;
218  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
219 
220  /* send middle part of address */
221  write = (address & 0xFF00u) >> 8u;
222  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
223 
224  /* send lower part of address */
225  write = address & 0xFFu;
226  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
227 
228  /* read CRC */
229  uint64_t crcRead = 0u;
230  uint8_t *pRead = (uint8_t *)(&crcRead);
231  for (uint8_t i = 0u; i < FRAM_CRC_HEADER_SIZE; i++) {
232  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
233  *pRead = (uint8_t)read;
234  pRead++;
235  }
236 
237  pRead = (uint8_t *)(fram_base_header[blockId].blockptr);
238 
239  /* read data */
240  write = 0;
241  while (size > 0u) {
242  SPI_FramTransmitReceiveData(&spi_framInterface, &write, &read, 1u);
243  *pRead = read & (uint8_t)UINT8_MAX;
244  pRead++;
245  size--;
246  }
247 
248  /* set chip select high to start transmission */
250 
252 
253  pRead = (uint8_t *)(fram_base_header[blockId].blockptr);
254  size = (fram_base_header[blockId]).datalength;
255  uint64_t crcCalculated = 0u;
256  STD_RETURN_TYPE_e crcRetVal = CRC_CalculateCrc(&crcCalculated, pRead, size);
257 
258  if (crcRetVal == STD_OK) {
259  if (crcRead != crcCalculated) {
261  retVal = FRAM_ACCESS_CRC_ERROR;
262  }
263  } else {
264  retVal = FRAM_ACCESS_CRC_BUSY;
265  }
266  } else {
267  retVal = FRAM_ACCESS_SPI_BUSY;
268  }
269 
270  return retVal;
271 }
272 
273 /*========== Externalized Static Function Implementations (Unit Test) =======*/
STD_RETURN_TYPE_e CRC_CalculateCrc(uint64_t *pCrc, uint8_t *pData, uint32_t lengthInBytes)
Computes CRC of data flow.
Definition: crc.c:71
crc module header
DIAG_RETURNTYPE_e DIAG_Handler(DIAG_ID_e diagId, DIAG_EVENT_e event, DIAG_IMPACT_LEVEL_e impact, uint32_t data)
DIAG_Handler provides generic error handling, based on diagnosis group.
Definition: diag.c:231
Diagnosis driver header.
@ DIAG_EVENT_NOT_OK
Definition: diag_cfg.h:239
@ DIAG_EVENT_OK
Definition: diag_cfg.h:238
@ DIAG_SYSTEM
Definition: diag_cfg.h:251
@ DIAG_ID_FRAM_READ_CRC_ERROR
Definition: diag_cfg.h:232
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:252
void FRAM_Initialize(void)
Initializes the addresses to be written in the FRAM.
Definition: fram.c:90
#define FRAM_DELAY_AFTER_WRITE_ENABLE_US
Definition: fram.c:68
#define FRAM_READCOMMAND
Definition: fram.c:73
STD_RETURN_TYPE_e FRAM_ReinitializeAllEntries(void)
Reinitialize all entries in the FRAM.
Definition: fram.c:105
#define FRAM_WRITECOMMAND
Definition: fram.c:72
FRAM_RETURN_TYPE_e FRAM_ReadData(FRAM_BLOCK_ID_e blockId)
Reads a variable from the FRAM.
Definition: fram.c:193
FRAM_RETURN_TYPE_e FRAM_WriteData(FRAM_BLOCK_ID_e blockId)
Writes a variable to the FRAM.
Definition: fram.c:115
#define FRAM_MAX_ADDRESS
Definition: fram.c:78
#define FRAM_WRITEENABLECOMMAND
Definition: fram.c:74
Header for the driver for the FRAM module.
FRAM_BASE_HEADER_s fram_base_header[]
Definition: fram_cfg.c:84
#define FRAM_CRC_HEADER_SIZE
Definition: fram_cfg.h:67
FRAM_RETURN_TYPE_e
Definition: fram_cfg.h:85
@ FRAM_ACCESS_SPI_BUSY
Definition: fram_cfg.h:87
@ FRAM_ACCESS_CRC_BUSY
Definition: fram_cfg.h:88
@ FRAM_ACCESS_CRC_ERROR
Definition: fram_cfg.h:89
@ FRAM_ACCESS_OK
Definition: fram_cfg.h:86
FRAM_BLOCK_ID_e
Definition: fram_cfg.h:100
@ FRAM_BLOCK_MAX
Definition: fram_cfg.h:108
STD_RETURN_TYPE_e
Definition: fstd_types.h:81
@ STD_OK
Definition: fstd_types.h:82
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:87
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:94
Header for the driver for the IO module.
void MCU_Delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:86
Headers for the driver for the MCU module.
void SPI_FramTransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA, wrappe for FRAM.
Definition: spi.c:206
STD_RETURN_TYPE_e SPI_Lock(uint8_t spi)
Locks SPI interfaces.
Definition: spi.c:329
void SPI_Unlock(uint8_t spi)
Unlocks SPI interfaces.
Definition: spi.c:346
uint8_t SPI_GetSpiIndex(spiBASE_t *pNode)
Returns index of SPI node.
Definition: spi.c:483
Headers for the driver for the SPI module.
SPI_INTERFACE_CONFIG_s spi_framInterface
Definition: spi_cfg.c:215
@ SPI_CHIP_SELECT_SOFTWARE
Definition: spi_cfg.h:117
SPI_CHIP_SELECT_TYPE_e csType
Definition: spi_cfg.h:128
volatile uint32_t * pGioPort
Definition: spi_cfg.h:126
spiBASE_t * pNode
Definition: spi_cfg.h:125