foxBMS  1.4.1
The foxBMS Battery Management System API Documentation
nxpfs85xx.c
Go to the documentation of this file.
1 /**
2  *
3  * @copyright © 2010 - 2022, Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright notice, this
12  * list of conditions and the following disclaimer.
13  *
14  * 2. Redistributions in binary form must reproduce the above copyright notice,
15  * this list of conditions and the following disclaimer in the documentation
16  * and/or other materials provided with the distribution.
17  *
18  * 3. Neither the name of the copyright holder nor the names of its
19  * contributors may be used to endorse or promote products derived from
20  * this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * We kindly request you to use one or more of the following phrases to refer to
34  * foxBMS in your hardware, software, documentation or advertising materials:
35  *
36  * - ″This product uses parts of foxBMS®″
37  * - ″This product includes parts of foxBMS®″
38  * - ″This product is derived from foxBMS®″
39  *
40  */
41 
42 /**
43  * @file nxpfs85xx.c
44  * @author foxBMS Team
45  * @date 2020-03-18 (date of creation)
46  * @updated 2022-10-27 (date of last update)
47  * @version v1.4.1
48  * @ingroup DRIVERS
49  * @prefix SBC
50  *
51  * @brief Driver for the SBC module
52  *
53  * @details It must always be used when creating new c source files.
54  *
55  */
56 
57 /*========== Includes =======================================================*/
58 #include "nxpfs85xx.h"
59 
60 #include "HL_gio.h"
61 #include "HL_system.h"
62 
63 #include "diag.h"
64 #include "fram.h"
65 #include "fsystem.h"
66 #include "io.h"
67 #include "masterinfo.h"
68 #include "mcu.h"
69 
70 /*========== Macros and Definitions =========================================*/
71 
72 /*========== Static Constant and Variable Definitions =======================*/
73 typedef enum {
79 
80 /*========== Extern Constant and Variable Definitions =======================*/
83  .configValues.watchdogSeed = FS8x_WD_SEED_DEFAULT,
84  .configValues.communicationMode = fs8xSPI,
85  .configValues.i2cAddressOtp = 0, /* Not used as SPI is selected */
86  .fin.finUsed = true,
87  .fin.finState = STD_NOT_OK,
88  .fin.pGIOport = &(systemREG1->SYSPC4), /* FIN connected to ECLK1 (ball A12): PRIVILEGE MODE REQUIRED! */
89  .fin.pin = 0,
90  .mainRegister = {0},
91  .fsRegister = {0},
92  .nvram.entry = FRAM_BLOCK_ID_SBC_INIT_STATE,
93  .nvram.data = &fram_sbcInit,
94  .mode = SBC_NORMAL_MODE, /* default value */
95 };
96 
97 /*========== Static Function Prototypes =====================================*/
98 /**
99  * @brief Checks register value against expected value
100  * @details If actual register value equals expected value #STD_OK is
101  * returned if this is not the case this indicates an error and
102  * #STD_NOT_OK is returned.
103  * @param[in] registerValue actual register value of interest
104  * @param[in] expectedRegisterValue expected register value
105  * @return #STD_OK if register value equals expected, else #STD_NOT_OK
106  */
107 static STD_RETURN_TYPE_e SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue);
108 
109 /**
110  * @brief Updates fail safe register values
111  * @details Updates fail safe register value of passed SBC instance
112  * with new values
113  * @param[in,out] pFsRegister pointer to fail-safe registers
114  * @param[in] registerAddress address of register that is updated
115  * @param[in] registerValue register value
116  */
117 static void SBC_UpdateFailSafeRegister(
118  FS85_FS_REGISTER_s *pFsRegister,
119  uint32_t registerAddress,
120  uint32_t registerValue);
121 
122 /**
123  * @brief Updates main register values
124  * @details Updates main register value of passed SBC instance with new
125  * values
126  * @param[in,out] pMainRegister pointer to main registers
127  * @param[in] registerAddress address of register that is updated
128  * @param[in] registerValue register value
129  */
130 static void SBC_UpdateMainRegister(
131  FS85_MAIN_REGISTERS_s *pMainRegister,
132  uint32_t registerAddress,
133  uint32_t registerValue);
134 
135 /**
136  * @brief Updates register values
137  * @details Updates register value of passed SBC instance with new
138  * values
139  * @param[in,out] pInstance SBC instance that is updated
140  * @param[in] isFailSafe true if fail-safe register, false if main register
141  * @param[in] registerAddress address of register that is updated
142  * @param[in] registerValue register value
143  */
144 static void SBC_UpdateRegister(
145  FS85_STATE_s *pInstance,
146  bool isFailSafe,
147  uint32_t registerAddress,
148  uint32_t registerValue);
149 
150 /**
151  * @brief Reads SBC register value
152  * @details Reads SBC register value from registerAddress and updates
153  * register in SBC state variable if reading was successful
154  * @param[in,out] pInstance SBC instance that is updated
155  * @param[in] isFailSafe true if fail-safe register, false if main
156  * register
157  * @param[in] registerAddress address of register that is read from
158  * @return #STD_OK if reading was successful, otherwise #STD_NOT_OK
159  */
160 static STD_RETURN_TYPE_e SBC_ReadBackRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress);
161 
162 /**
163  * @brief Write to fail-safe register
164  * @details Writes to fail-safe register (can be done during FS_INIT phase
165  * only)
166  * @param[in] pInstance SBC instance that is updated
167  * @param[in] registerAddress address of register
168  * @param[in] registerValue value that is written into register
169  * @return #STD_OK if writing was successful, other #STD_NOT_OK
170  */
172  FS85_STATE_s *pInstance,
173  uint8_t registerAddress,
174  uint16_t registerValue);
175 
176 /**
177  * @brief Write to fail-safe register
178  * @details Writes to fail-safe register (can be done during FS_INIT
179  * phase only), reads back if write process was successful and
180  * afterwards updates register value of passed SBC instance
181  * @param[in,out] pInstance SBC instance that is updated
182  * @param[in] registerAddress address of register
183  * @param[in] registerValue value that is written into register
184  * @return #STD_OK if writing was successful, other #STD_NOT_OK
185  */
187  FS85_STATE_s *pInstance,
188  uint8_t registerAddress,
189  uint16_t registerValue);
190 
191 /**
192  * @brief Clears flags in register
193  * @details Writes to register, reads back if clear process was
194  * successful and afterwards updates register value of passed
195  * SBC instance
196  * @param[in,out] pInstance SBC instance that is updated
197  * @param[in] registerAddress address of register
198  * @param[in] isFailSafe true if fail-safe register, false if main register
199  * @param[in] registerValue value that is written into register
200  * @return #STD_OK if writing was successful, other #STD_NOT_OK
201  */
203  FS85_STATE_s *pInstance,
204  uint8_t registerAddress,
205  bool isFailSafe,
206  uint16_t registerValue);
207 
209 
210 /**
211  * @brief Perform RSTB safety path check
212  * @details This functions performs a safety path check to make sure
213  * external components connected to RSTB are available to
214  * bring the safety critical outputs to known levels during
215  * operation.
216  * @param[in,out] pInstance SBC instance for which the RSTB path is checked
217  * @return #STD_OK if path check was successful, other #STD_NOT_OK
218  */
220 
221 /**
222  * @brief Perform FS0B safety path check
223  * @details This functions performs a safety path check to make sure
224  * external components connected to FS0B are available to
225  * bring the safety critical outputs to known levels during
226  * operation.
227  * @param[in,out] pInstance SBC instance for which the FS0B path is checked
228  */
230 
231 /*========== Static Function Implementations ================================*/
232 static STD_RETURN_TYPE_e SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue) {
233  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
234  /* AXIVION Routine Generic-MissingParameterAssert: expectedRegisterValue: parameter accepts whole range */
235  STD_RETURN_TYPE_e retval = STD_OK;
236  if (registerValue != expectedRegisterValue) {
237  retval = STD_NOT_OK;
238  }
239  return retval;
240 }
241 
243  FS85_FS_REGISTER_s *pFsRegister,
244  uint32_t registerAddress,
245  uint32_t registerValue) {
246  FAS_ASSERT(pFsRegister != NULL_PTR);
247  FAS_ASSERT(registerAddress <= FS8X_M_DEVICEID_ADDR);
248  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
249  switch (registerAddress) {
251  pFsRegister->grl_flags = registerValue;
252  break;
254  pFsRegister->iOvervoltageUndervoltageSafeReaction1 = registerValue;
255  break;
257  pFsRegister->iOvervoltageUndervoltageSafeReaction2 = registerValue;
258  break;
260  pFsRegister->iWatchdogConfiguration = registerValue;
261  break;
263  pFsRegister->i_safe_inputs = registerValue;
264  break;
265  case FS8X_FS_I_FSSM_ADDR:
266  pFsRegister->iFailSafeSateMachine = registerValue;
267  break;
268  case FS8X_FS_I_SVS_ADDR:
269  pFsRegister->i_svs = registerValue;
270  break;
272  pFsRegister->watchdogWindow = registerValue;
273  break;
275  pFsRegister->watchdogSeed = registerValue;
276  break;
278  pFsRegister->watchdogAnswer = registerValue;
279  break;
281  pFsRegister->overvoltageUndervoltageRegisterStatus = registerValue;
282  break;
284  pFsRegister->releaseFs0bPin = registerValue;
285  break;
287  pFsRegister->safeIos = registerValue;
288  break;
290  pFsRegister->diag_safety = registerValue;
291  break;
293  pFsRegister->intb_mask = registerValue;
294  break;
295  case FS8X_FS_STATES_ADDR:
296  pFsRegister->states = registerValue;
297  break;
298  default:
299  FAS_ASSERT(FAS_TRAP); /* This case should never be reached */
300  break;
301  }
302 }
303 
305  FS85_MAIN_REGISTERS_s *pMainRegister,
306  uint32_t registerAddress,
307  uint32_t registerValue) {
308  FAS_ASSERT(pMainRegister != NULL_PTR);
309  FAS_ASSERT(registerAddress <= FS8X_M_DEVICEID_ADDR);
310  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
311  switch (registerAddress) {
312  case FS8X_M_FLAG_ADDR:
313  pMainRegister->flag = registerValue;
314  break;
315  case FS8X_M_MODE_ADDR:
316  pMainRegister->mode = registerValue;
317  break;
319  pMainRegister->registerControl1 = registerValue;
320  break;
322  pMainRegister->registerControl2 = registerValue;
323  break;
324  case FS8X_M_AMUX_ADDR:
325  pMainRegister->analogMultiplexer = registerValue;
326  break;
327  case FS8X_M_CLOCK_ADDR:
328  pMainRegister->clock = registerValue;
329  break;
331  pMainRegister->int_mask1 = registerValue;
332  break;
334  pMainRegister->int_mask2 = registerValue;
335  break;
336  case FS8X_M_FLAG1_ADDR:
337  pMainRegister->flag1 = registerValue;
338  break;
339  case FS8X_M_FLAG2_ADDR:
340  pMainRegister->flag2 = registerValue;
341  break;
343  pMainRegister->vmon_regx = registerValue;
344  break;
346  pMainRegister->lvb1_svs = registerValue;
347  break;
348  case FS8X_M_MEMORY0_ADDR:
349  pMainRegister->memory0 = registerValue;
350  break;
351  case FS8X_M_MEMORY1_ADDR:
352  pMainRegister->memory1 = registerValue;
353  break;
355  pMainRegister->deviceId = registerValue;
356  break;
357  default:
358  FAS_ASSERT(FAS_TRAP); /* This case should never be reached */
359  break;
360  }
361 }
362 
363 static void SBC_UpdateRegister(
364  FS85_STATE_s *pInstance,
365  bool isFailSafe,
366  uint32_t registerAddress,
367  uint32_t registerValue) {
368  FAS_ASSERT(pInstance != NULL_PTR);
369  FAS_ASSERT((isFailSafe == true) || (isFailSafe == false));
370  FAS_ASSERT(registerAddress <= FS8X_M_DEVICEID_ADDR);
371  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
372 
373  /* Check if fail-safe or main register needs to be updated */
374  if (isFailSafe == true) { /* Update fail-safe register */
375  SBC_UpdateFailSafeRegister(&(pInstance->fsRegister), registerAddress, registerValue);
376  } else { /* Update main register */
377  SBC_UpdateMainRegister(&(pInstance->mainRegister), registerAddress, registerValue);
378  }
379 }
380 
381 static STD_RETURN_TYPE_e SBC_ReadBackRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress) {
382  FAS_ASSERT(pInstance != NULL_PTR);
383  FAS_ASSERT((isFailSafe == true) || (isFailSafe == false));
384  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
385 
386  STD_RETURN_TYPE_e retval = STD_NOT_OK;
387  fs8x_rx_frame_t rxTemp = {0};
388 
389  FAS_ASSERT(pInstance != NULL_PTR);
390 
391  if (fs8xStatusOk !=
392  FS8x_ReadRegister(pInstance->pSpiInterface, &(pInstance->configValues), isFailSafe, registerAddress, &rxTemp)) {
393  retval = STD_NOT_OK;
394  } else {
395  SBC_UpdateRegister(pInstance, isFailSafe, registerAddress, rxTemp.readData);
396  retval = STD_OK;
397  }
398  return retval;
399 }
400 
402  FS85_STATE_s *pInstance,
403  uint8_t registerAddress,
404  uint16_t registerValue) {
405  FAS_ASSERT(pInstance != NULL_PTR);
406  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
407  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
408 
409  STD_RETURN_TYPE_e retval = STD_OK;
410 
411  FAS_ASSERT(pInstance != NULL_PTR);
412 
413  /* Write to register */
414  if (fs8xStatusOk !=
415  FS8x_WriteRegisterInit(pInstance->pSpiInterface, &(pInstance->configValues), registerAddress, registerValue)) {
416  retval = STD_NOT_OK;
417  } else {
418  retval = STD_OK;
419  }
420  return retval;
421 }
422 
424  FS85_STATE_s *pInstance,
425  uint8_t registerAddress,
426  uint16_t registerValue) {
427  FAS_ASSERT(pInstance != NULL_PTR);
428  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
429  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
430 
431  STD_RETURN_TYPE_e retval = STD_OK;
432  fs8x_rx_frame_t rxTemp = {0};
433 
434  FAS_ASSERT(pInstance != NULL_PTR);
435 
436  /* Write to register */
437  if (fs8xStatusOk !=
438  FS8x_WriteRegisterInit(pInstance->pSpiInterface, &(pInstance->configValues), registerAddress, registerValue)) {
439  retval |= STD_NOT_OK;
440  } else {
441  /* Read back register value and check if write process was successful */
442  if (fs8xStatusOk !=
443  FS8x_ReadRegister(pInstance->pSpiInterface, &(pInstance->configValues), true, registerAddress, &rxTemp)) {
444  retval |= STD_NOT_OK;
445  } else {
446  if (rxTemp.readData == registerValue) {
447  /* Written register value equals read value */
448  SBC_UpdateRegister(pInstance, true, registerAddress, rxTemp.readData);
449  } else {
450  retval |= STD_NOT_OK;
451  }
452  }
453  }
454  return retval;
455 }
456 
458  FS85_STATE_s *pInstance,
459  uint8_t registerAddress,
460  bool isFailSafe,
461  uint16_t registerValue) {
462  FAS_ASSERT(pInstance != NULL_PTR);
463  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
464  /* AXIVION Routine Generic-MissingParameterAssert: isFailSafe: parameter accepts whole range */
465  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
466 
467  STD_RETURN_TYPE_e retval = STD_OK;
468  fs8x_rx_frame_t rxTemp = {0};
469 
470  FAS_ASSERT(pInstance != NULL_PTR);
471 
472  /* Write to register */
473  if (fs8xStatusOk !=
475  pInstance->pSpiInterface, &(pInstance->configValues), isFailSafe, registerAddress, registerValue)) {
476  retval |= STD_NOT_OK;
477  } else {
478  /* Read back register value and check if write process was successful */
479  if (fs8xStatusOk !=
481  pInstance->pSpiInterface, &(pInstance->configValues), isFailSafe, registerAddress, &rxTemp)) {
482  retval |= STD_NOT_OK;
483  } else {
484  /* Check if all flags have been cleared: '1' is written to registers to clear respective flags */
485  if ((rxTemp.readData & registerValue) == 0u) {
486  /* Written register value equals read value */
487  SBC_UpdateRegister(pInstance, isFailSafe, registerAddress, rxTemp.readData);
488  } else {
489  retval |= STD_NOT_OK;
490  }
491  }
492  }
493  return retval;
494 }
495 
496 /*========== Extern Function Implementations ================================*/
498  FAS_ASSERT(pInstance != NULL_PTR);
499 
500  STD_RETURN_TYPE_e retval = STD_OK;
501  uint16_t registerMask = 0u;
502  uint16_t expRegisterValue = 0u;
503  uint16_t registerValue = 0u;
504 
505  FAS_ASSERT(pInstance != NULL_PTR);
506  /* Default init value: #STD_NOT_OK, will be set to #STD_OK later in init if
507  no short-circuit between FIN and RSTB detected. Do not apply external
508  clock on this pin until finState == #STD_OK */
509  FAS_ASSERT(pInstance->fin.finState == STD_NOT_OK);
510 
511  /** First: Verify following conditions:
512  1. Verify LBIST (logical-built-in-self-test) and ABIST1 (analog-built-in-self-test1) are pass
513  2. Verify Debug mode is not activated
514  3. Verify there is no OTP CRC error
515  4. Verify PGOOD was released: PGOOD is connected to power-on-reset of the MCU
516 
517  Second: Configure FS_I and FS_I_NOT registers
518 
519  - Write the desired data in the FS_I_Register_A (DATA)
520  - Write the opposite in the FS_I_NOT_Register_A (DATA_NOT)
521  - Only the utility bits must be inverted in the DATA_NOT content. The RESERVED bits are not considered and can be
522  written at '0'. If the comparison result is correct, then the REG_CORRUPT is set to '0'. If the comparison result
523  is wrong, then the REG_CORRUPT bit is set to '1'. The REG_CORRUPT monitoring is active as soon as the INIT_FS is
524  closed by the first good watchdog refresh. INIT_FS must be closed by the first good watchdog refresh before 256ms
525  timeout.
526 
527  1. Configure VCOREMON_OV_UV impact on RSTB and FS0B
528  2. Configure VDDIO_OV_UV impact on RSTB and FS0B
529  3. Configure VMONx_OV_UV impact on RSTB and FS0B
530  4. Configure ABIST2 assignment
531  5. Configure the WD window period, the WD window duty cycle, the WD counters limits,
532  and its impact on RSTB and FS0B. Ensure that the configuration does not violate the
533  FTTI requirement at system level.
534  6. Configure the Fault Error Counter limit and its impact on RSTB and FS0B at
535  intermediate value
536  7. Configure the RSTB pulse duration
537  8. Configure MCU FCCU error monitoring and its impact on RSTB and FS0B
538  9. Configure Ext. IC error monitoring and its impact on RSTB and FS0B
539  10.Configure FS0B short to high impact on RSTB
540 
541  Third: Execute
542 
543  1. Close INIT_FS by sending the first good WD refresh
544  2. Execute ABIST2 and verify it is pass
545  3. Clear all the flags by writing in FS_DIAG_SAFETY, FS_OVUVREG_STATUS
546  4. Clear the fault error counter to 0 with consecutive good WD refresh
547  5. Perform RSTB path check (repeat steps 1 to 4 after RSTB is released)
548  6. Release FS0B pin
549  7. Perform FS0B safety path check
550  8. Refresh the WD according to its configuration
551  9. Check FS_GRL_FLAGS register after each WD refresh
552 
553  The FS85 is now ready. If everything is OK for the MCU, it can release its own
554  safety path and the ECU starts.
555  */
556 
557  /* --------------------- First: Verify --------------------------------- */
558 
559  /** 1.: Verify LBIST and ABIST1 */
560  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_DIAG_SAFETY_ADDR)) {
561  retval = STD_NOT_OK;
562  }
564  expRegisterValue = (FS8X_FS_LBIST_OK_PASS | FS8X_FS_ABIST1_OK_PASS);
565  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
566  retval = STD_NOT_OK;
567  }
568 
569  /** Read FS STATES register */
570  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR)) {
571  retval = STD_NOT_OK;
572  }
573 
574  /** 2.: Check if debug mode is active */
575  registerMask = FS8X_FS_DBG_MODE_MASK;
576  expRegisterValue = FS8X_FS_DBG_MODE_NO_DEBUG;
577  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
578  /* Debug mode active: this can only be the case if debugger connected */
580  pInstance->mode = SBC_DEBUG_MODE;
581  } else {
582  /* Debug mode not active: no debugger connected */
584  pInstance->mode = SBC_NORMAL_MODE;
585  }
586 
587  /** 3.: Verify that no OPT CRC error */
588  registerMask = FS8X_FS_OTP_CORRUPT_MASK;
589  expRegisterValue = FS8X_FS_OTP_CORRUPT_NO_ERROR;
590  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
591  retval = STD_NOT_OK;
592  }
593 
594  /** -------- Second: Configure fail-safe init registers ------------------*/
595  /** Check if SBC is in FS_INIT state, if not switch SBC in FS_INIT state.
596  * Specific configurations can only be done in FS_INIT state */
597  registerMask = FS8X_FS_FSM_STATE_MASK;
598  expRegisterValue = FS8X_FS_FSM_STATE_INIT_FS;
599  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
600  /* SBC not in FS_INIT state -> request FS_INIT state */
601  /* Write FS_STATE request */
603  if (STD_OK != SBC_WriteRegisterFsInit(pInstance, FS8X_FS_SAFE_IOS_ADDR, registerValue)) {
604  retval = STD_NOT_OK;
605  } else {
606  /* Check if SBC now in FS_STATE */
607  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR)) {
608  retval = STD_NOT_OK;
609  } else {
610  /* Read register now check if SBC in FS_INIT state */
611  if (STD_OK !=
612  SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
613  /* SBC not in FS_INIT state -> error */
614  retval = STD_NOT_OK;
615  }
616  }
617  }
618  }
619 
620  /** 1.: Configure VCOREMON_OV_UV impact on RSTB and FS0B */
621  /** 2.: Configure VDDIO_OV_UV impact on RSTB and FS0B */
622  /** 4.: Configure ABIST2 assignment */
623  registerValue = 0;
624 
625  /** Select VCOREMON_OV options:
626  * - FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT
627  * - FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B
628  * - FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B_RSTB */
630 
631  /** Select VCOREMON_UV options:
632  * - FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT
633  * - FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B
634  * - FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B_RSTB */
636 
637  /** Select VDDIO_OV options:
638  * - FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT
639  * - FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B
640  * - FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B_RSTB */
642 
643  /** Select VDDIO_UV options:
644  * - FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT
645  * - FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B
646  * - FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B_RSTB */
648 
649  /** Select ABIST2 options:
650  * + VCOREMON
651  * - FS8X_FS_I_VCOREMON_ABIST2_NO_ABIST
652  * - FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST
653  * + VDDIO
654  * - FS8X_FS_I_VDDIO_ABIST2_NO_ABIST
655  * - FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST
656  * + VMONx (VMON1 - VMON4)
657  * - FS8X_FS_I_VMONx_ABIST2_NO_ABIST
658  * - FS8X_FS_I_VMONx_ABIST2_VMONx_BIST */
660  registerValue |= FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST;
661  registerValue |= FS8X_FS_I_VMON1_ABIST2_VMON1_BIST;
662  registerValue |= FS8X_FS_I_VMON2_ABIST2_VMON2_BIST;
663  registerValue |= FS8X_FS_I_VMON3_ABIST2_VMON3_BIST;
664  registerValue |= FS8X_FS_I_VMON4_ABIST2_VMON4_BIST;
665 
666  /* Write register */
667  if (STD_OK != SBC_WriteBackRegisterFsInit(pInstance, FS8X_FS_I_OVUV_SAFE_REACTION1_ADDR, registerValue)) {
668  retval = STD_NOT_OK;
669  }
670 
671  /** 3.: Configure VMONx_OV_UV impact on RSTB and FS0B */
672  registerValue = 0;
673  /** Select VMONx_OV options:
674  * - FS8X_FS_I_VMONx_OV_FS_IMPACT_NO_EFFECT
675  * - FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B
676  * - FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B_RSTB */
681 
682  /** Select VMONx_UV options:
683  * - FS8X_FS_I_VMONx_UV_FS_IMPACT_NO_EFFECT
684  * - FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B
685  * - FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B_RSTB */
690 
691  /* Write register */
692  if (STD_OK != SBC_WriteBackRegisterFsInit(pInstance, FS8X_FS_I_OVUV_SAFE_REACTION2_ADDR, registerValue)) {
693  retval = STD_NOT_OK;
694  }
695 
696  /** 5.: Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and
697  FS0B. Ensure that the configuration does not violate the FTTI requirement at system level. */
698  registerValue = 0;
699 
700  /** WD window period options:
701  * - FS8X_FS_WD_WINDOW_DISABLE
702  * - FS8X_FS_WD_WINDOW_xxxxMS */
703  registerValue |= FS8X_FS_WD_WINDOW_128MS;
704 
705  /** WD window duty cycle options:
706  * - FS8X_FS_WDW_DC_31_25
707  * - FS8X_FS_WDW_DC_37_5
708  * - FS8X_FS_WDW_DC_50
709  * - FS8X_FS_WDW_DC_62_5
710  * - FS8X_FS_WDW_DC_68_75 */
711  registerValue |= FS8X_FS_WDW_DC_50;
712 
713  /** WD fault recovery strategy
714  * - FS8X_FS_WDW_RECOVERY_DISABLE
715  * - FS8X_FS_WDW_RECOVERY_xxxxMS */
716  registerValue |= FS8X_FS_WDW_RECOVERY_128MS;
717 
718  /* Write register */
719  if (STD_OK != SBC_WriteBackRegisterFsInit(pInstance, FS8X_FS_WD_WINDOW_ADDR, registerValue)) {
720  retval = STD_NOT_OK;
721  }
722 
723  /** 6.: Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value */
724  /** Configure the RSTB pulse duration */
725  /** Configure FS0B short to high impact on RSTB */
726  registerValue = 0;
727 
728  /** Fault Error Counter limit options:
729  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_2
730  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_4
731  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_6
732  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_8 */
733  registerValue |= FS8X_FS_I_FLT_ERR_CNT_LIMIT_8;
734 
735  /** Fault Error Counter impact options:
736  * - FS8X_FS_I_FLT_ERR_IMPACT_NO_EFFECT
737  * - FS8X_FS_I_FLT_ERR_IMPACT_FS0B
738  * - FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB */
739  registerValue |= FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB;
740 
741  /** 7.: RSTB pulse duration options:
742  * - FS8X_FS_I_RSTB_DUR_1MS
743  * - FS8X_FS_I_RSTB_DUR_10MS */
744  registerValue |= FS8X_FS_I_RSTB_DUR_10MS;
745 
746  /** 10.: FS0B short to high impact on RSTB options:
747  * - FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION
748  * - FS8X_FS_I_FS0B_SC_HIGH_CFG_RESET_ASSERTED */
750 
751  /** After POR fault-error counter is set to 1 on default, it is reset after two consecutive good WD refreshes. This
752  part of the register is read-only so a write access has no influence. Set this bit for a successful comparison
753  between written and read register value */
754  registerValue |= FS8X_FS_I_FLT_ERR_CNT_1;
755 
756  /* Write register */
757  if (STD_OK != SBC_WriteRegisterFsInit(pInstance, FS8X_FS_I_FSSM_ADDR, registerValue)) {
758  retval = STD_NOT_OK;
759  }
760 
761  /** 8.: Configure MCU FCCU error monitoring and its impact on RSTB and FS0B */
762  /** 9.: Configure Ext. IC error monitoring and its impact on RSTB and FS0B */
763  registerValue = 0;
764 
765  /** MCU FCCU error monitoring options:
766  * + Input option:
767  * - FS8X_FS_I_FCCU_CFG_NO_MONITORING
768  * - FS8X_FS_I_FCCU_CFG_FCCU1_INPUT
769  * - FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_INPUT
770  * - FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_PAIR (bi-stable protocol)
771  * + Polarity option (independent):
772  * - FS8X_FS_I_FCCUx_FLT_POL_FCCUx_L
773  * - FS8X_FS_I_FCCUx_FLT_POL_FCCUx_H
774  * + Polarity option (bi-stable)
775  * - FS8X_FS_I_FCCU12_FLT_POL_FCCU1_L_FCCU2_H
776  * - FS8X_FS_I_FCCU12_FLT_POL_FCCU1_H_FCCU2_L
777  * + Impact option (independent)
778  * - FS8X_FS_I_FCCUx_FS_REACT_FS0B
779  * - FS8X_FS_I_FCCUx_FS_REACT_FS0B_RSTB
780  * + Impact option (bi-stable)
781  * - FS8X_FS_I_FCCU12_FS_IMPACT_FS0B
782  * - FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB
783  */
784  registerValue |= FS8X_FS_I_FCCU_CFG_NO_MONITORING;
785  registerValue |= FS8X_FS_I_FCCU1_FLT_POL_FCCU1_L;
786  registerValue |= FS8X_FS_I_FCCU1_FS_REACT_FS0B;
787 
788  /** Ext. IC error monitoring options:
789  * + Polarity options:
790  * - FS8X_FS_I_ERRMON_FLT_POLARITY_NEGATIVE_EDGE
791  * - FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE
792  * + Error acknowledgment time options:
793  * - FS8X_FS_I_ERRMON_ACK_TIME_1MS
794  * - FS8X_FS_I_ERRMON_ACK_TIME_8MS
795  * - FS8X_FS_I_ERRMON_ACK_TIME_16MS
796  * - FS8X_FS_I_ERRMON_ACK_TIME_32MS
797  * + Error monitoring impact options:
798  * - FS8X_FS_I_ERRMON_FS_IMPACT_FS0B
799  * - FS8X_FS_I_ERRMON_FS_IMPACT_FS0B_RSTB */
801  registerValue |= FS8X_FS_I_ERRMON_ACK_TIME_32MS;
802  registerValue |= FS8X_FS_I_ERRMON_FS_IMPACT_FS0B;
803 
804  /* Write register */
805  if (STD_OK != SBC_WriteRegisterFsInit(pInstance, FS8X_FS_I_SAFE_INPUTS_ADDR, registerValue)) {
806  retval = STD_NOT_OK;
807  }
808 
809  /* -------------------- Third: Execute --------------------------------- */
810 
811  /** 1.: Close INIT_FS by sending the first good WD refresh */
812  if (STD_OK != SBC_TriggerWatchdog(pInstance)) {
813  retval = STD_NOT_OK;
814  }
815  /** 2.: Execute ABIST2 and verify it is pass */
816  /** ABIST2 is executed automatically after closing of INIT_FS, duration: 1.2ms max */
817  MCU_Delay_us(1200u);
818 
819  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_DIAG_SAFETY_ADDR)) {
820  retval = STD_NOT_OK;
821  }
822  registerMask = FS8X_FS_ABIST2_OK_MASK;
823  expRegisterValue = FS8X_FS_ABIST2_OK_MASK;
824  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
825  retval = STD_NOT_OK;
826  }
827 
828  /** 3.: Clear all the flags by writing in FS_DIAG_SAFETY */
829  registerValue = 0;
830  /** Flags are cleared by writing '1' to register */
832  registerValue |= FS8X_FS_ERRMON_ERROR_DETECTED;
834  registerValue |=
838  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_FS_DIAG_SAFETY_ADDR, true, registerValue)) {
839  retval = STD_NOT_OK;
840  }
841 
842  /** Clear all the flags by writing in FS_OVUVREG_STATUS */
843  registerValue = 0;
844  /** Flags are cleared by writing '1' to register */
847  registerValue |=
853  registerValue |= FS8X_FS_FS_OSC_DRIFT_OSCILLATOR_DRIFT;
854  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_FS_OVUVREG_STATUS_ADDR, true, registerValue)) {
855  retval = STD_NOT_OK;
856  }
857 
858  /** Clear flags FLAG1 register */
859  registerValue = FS8X_M_VBOSUVH_EVENT_OCCURRED;
860  registerValue |= FS8X_M_VBOOSTUVH_EVENT_OCCURRED;
861  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_M_FLAG1_ADDR, false, registerValue)) {
862  retval = STD_NOT_OK;
863  }
864 
865  /** Clear flags FLAG2 register */
866  registerValue = FS8X_M_VSUPUV7_EVENT_OCCURRED;
867  registerValue |=
870  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_M_FLAG2_ADDR, false, registerValue)) {
871  retval = STD_NOT_OK;
872  }
873 
874  /** Read out all registers for debug purpose */
875  if (STD_OK != SBC_ReadBackAllRegisters(pInstance)) {
876  retval = STD_OK;
877  }
878 
879  return retval;
880 }
881 
883  FS85_STATE_s *pInstance,
884  uint8_t *requiredWatchdogRefreshes) {
885  FAS_ASSERT(pInstance != NULL_PTR);
886  FAS_ASSERT(requiredWatchdogRefreshes != NULL_PTR);
887 
888  STD_RETURN_TYPE_e retval = STD_OK;
889 
890  /** Clear the fault error counter to 0 with consecutive good WD refreshes.
891  * The watchdog refresh counter is used to decrement the fault error counter. Each time the watchdog is properly
892  * refreshed, the watchdog refresh counter is incremented by '1'. Each time the watchdog refresh counter reaches
893  * its maximum value ('6' by default) and if next WD refresh is also good, the fault error counter is decremented
894  * by '1'. Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog,
895  * the watchdog refresh counter is reset to '0'. */
896 
897  /** Read out FS_I_WD_CFG register to get watchdog refresh counter limit and value */
898  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_WD_CFG_ADDR)) {
899  retval = STD_NOT_OK;
900  }
901 
902  /** Get refresh counter value */
903  uint8_t watchdogRefreshLimit = 0;
904  uint8_t watchdogRefreshCounter = FS8x_BO_GET_REG_VALUE(
906 
907  /** Get refresh counter limit register value */
911  watchdogRefreshLimit = 6u;
912  } else if (
916  watchdogRefreshLimit = 4u;
917  } else if (
921  watchdogRefreshLimit = 2u;
922  } else {
923  watchdogRefreshLimit = 1u;
924  }
925 
926  /** Get fault error counter */
927  uint8_t faultCounter = 0u;
928  if (fs8xStatusOk !=
929  FS8x_GetFaultErrorCounterValue(pInstance->pSpiInterface, &(pInstance->configValues), &faultCounter)) {
930  retval = STD_NOT_OK;
931  }
932 
933  /** Get number of required watchdog refreshes to clear fault error counter to 0 */
934  *requiredWatchdogRefreshes = faultCounter + (watchdogRefreshLimit - watchdogRefreshCounter);
935 
936  return retval;
937 }
938 
940  FAS_ASSERT(pInstance != NULL_PTR);
941  /* AXIVION Routine Generic-MissingParameterAssert: parameters without assertion accept whole range of data type */
942 
943  STD_RETURN_TYPE_e retval = STD_OK;
944 
945  /* Check fault error counter */
946  uint8_t faultCounter = 0u;
947  retval |= FS8x_GetFaultErrorCounterValue(pInstance->pSpiInterface, &(pInstance->configValues), &faultCounter);
948  if (faultCounter != 0u) {
949  retval = STD_NOT_OK;
950  }
951  return retval;
952 }
953 
955  FAS_ASSERT(pInstance != NULL_PTR);
956 
957  STD_RETURN_TYPE_e retval = STD_OK;
958 
959  /* Perform RSTB path check (repeat steps 1 to 4 after RSTB is released) */
960  if (STD_OK != SBC_PerformPathCheckRstb(pInstance)) {
961  retval = STD_NOT_OK;
962  }
963 
964  /* FS0B pin can not be released in debug mode */
965  if (pInstance->mode != SBC_DEBUG_MODE) {
966  /* Release FS0B pin */
967  if (fs8xStatusOk != FS8x_FS0B_Release(pInstance->pSpiInterface, &(pInstance->configValues))) {
968  retval = STD_NOT_OK;
969  }
970  }
971 
972  /* Perform FS0B safety path check */
973  if (STD_OK != SBC_PerformPathCheckFs0b(pInstance)) {
974  retval = STD_NOT_OK;
975  }
976 
977  /* Init finished successfully if retval still okay */
978  if (retval == STD_OK) {
979  pInstance->nvram.data->phase = (uint8_t)SBC_INITIALIZED;
980  FRAM_WriteData(pInstance->nvram.entry);
981  }
982  return retval;
983 }
984 
985 /* AXIVION Next Codeline Style CodingStyle-Naming.Function: The name is pre-defined by the driver provided by NXP. */
987  SPI_INTERFACE_CONFIG_s *pSpiInterface,
988  uint8_t *txFrame,
989  uint16_t frameLengthBytes,
990  uint8_t *rxFrame) {
991  FAS_ASSERT(pSpiInterface != NULL_PTR);
992  FAS_ASSERT(txFrame != NULL_PTR);
993  FAS_ASSERT(rxFrame != NULL_PTR);
994  /* AXIVION Routine Generic-MissingParameterAssert: frameLengthBytes: parameter accepts whole range */
995 
996  uint16_t sbc_txBuffer[FS8x_COMM_FRAME_SIZE];
997  uint16_t sbc_rxBuffer[FS8x_COMM_FRAME_SIZE];
998  fs8x_status_t spiCommunicationState = fs8xStatusError;
999 
1000  /* Copy TX data in TX array, reset RX array */
1001  for (uint8_t i = 0u; i < FS8x_COMM_FRAME_SIZE; i++) {
1002  sbc_txBuffer[FS8x_COMM_FRAME_SIZE - 1u - i] = (uint16_t)txFrame[i]; /* txFrame[0] will be sent last */
1003  sbc_rxBuffer[i] = 0;
1004  }
1005 
1006  STD_RETURN_TYPE_e spiRetval =
1007  SPI_TransmitReceiveData(pSpiInterface, sbc_txBuffer, sbc_rxBuffer, FS8x_COMM_FRAME_SIZE);
1008 
1009  if (spiRetval == STD_OK) {
1010  /* No error flag set - copy RX data in RX array */
1011  for (uint8_t i = 0u; i < FS8x_COMM_FRAME_SIZE; i++) {
1012  rxFrame[i] = (uint8_t)sbc_rxBuffer[FS8x_COMM_FRAME_SIZE - 1u - i];
1013  }
1014  spiCommunicationState = fs8xStatusOk;
1015  }
1016 
1017  return spiCommunicationState;
1018 }
1019 
1021  FAS_ASSERT(pInstance != NULL_PTR);
1022 
1023  STD_RETURN_TYPE_e retval = STD_NOT_OK;
1024  if (fs8xStatusOk == FS8x_WD_Refresh(pInstance->pSpiInterface, &(pInstance->configValues))) {
1025  /* Check GRL_FLAGS register if watchdog refresh was valid */
1026  if (STD_OK == SBC_ReadBackRegister(pInstance, true, FS8X_FS_GRL_FLAGS_ADDR)) {
1027  uint16_t registerMask = FS8X_FS_FS_WD_G_MASK;
1028  uint16_t expRegisterValue = FS8X_FS_FS_WD_G_GOOD_WD_REFRESH;
1029  if (STD_OK == SBC_CheckRegisterValues((pInstance->fsRegister.grl_flags & registerMask), expRegisterValue)) {
1030  /* GOOD watchdog refresh */
1031  retval = STD_OK;
1032  } else {
1033  /* BAD watchdog refresh: get reason */
1034  if (STD_OK == SBC_ReadBackRegister(pInstance, true, FS8X_FS_DIAG_SAFETY_ADDR)) {
1035  registerMask = FS8X_FS_BAD_WD_TIMING_MASK;
1036  expRegisterValue = FS8X_FS_BAD_WD_TIMING_BAD_WD_REFRESH;
1037  if (STD_OK ==
1038  SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
1039  /* TODO: Notify someone: bad watchdog refresh was caused by wrong window or in timeout */
1040  }
1041  registerMask = FS8X_FS_BAD_WD_DATA_MASK;
1042  expRegisterValue = FS8X_FS_BAD_WD_DATA_BAD_WD_REFRESH;
1043  if (STD_OK ==
1044  SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
1045  /* TODO: Notify someone: bad watchdog refresh was caused by error in data */
1046  }
1047  }
1048  }
1049  }
1050  }
1051  return retval;
1052 }
1053 
1055  FAS_ASSERT(pInstance != NULL_PTR);
1056 
1057  STD_RETURN_TYPE_e retval = STD_OK;
1058 
1059  /* Read all fail-safe registers */
1060  SBC_ReadBackRegister(pInstance, true, FS8X_FS_GRL_FLAGS_ADDR);
1063  SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_WD_CFG_ADDR);
1065  SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_FSSM_ADDR);
1066  SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_SVS_ADDR);
1067  SBC_ReadBackRegister(pInstance, true, FS8X_FS_WD_WINDOW_ADDR);
1068  SBC_ReadBackRegister(pInstance, true, FS8X_FS_WD_SEED_ADDR);
1069  SBC_ReadBackRegister(pInstance, true, FS8X_FS_WD_ANSWER_ADDR);
1072  SBC_ReadBackRegister(pInstance, true, FS8X_FS_SAFE_IOS_ADDR);
1074  SBC_ReadBackRegister(pInstance, true, FS8X_FS_INTB_MASK_ADDR);
1075  SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR);
1076 
1077  /* Read main registers */
1078  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_FLAG_ADDR);
1079  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_MODE_ADDR);
1080  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_REG_CTRL1_ADDR);
1081  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_REG_CTRL2_ADDR);
1082  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_AMUX_ADDR);
1083  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_CLOCK_ADDR);
1084  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_INT_MASK1_ADDR);
1085  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_INT_MASK2_ADDR);
1086  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_FLAG1_ADDR);
1087  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_FLAG2_ADDR);
1088  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_VMON_REGX_ADDR);
1089  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_LVB1_SVS_ADDR);
1090  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_MEMORY0_ADDR);
1091  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_MEMORY1_ADDR);
1092  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_DEVICEID_ADDR);
1093  return retval;
1094 }
1095 
1097  FAS_ASSERT(pInstance != NULL_PTR);
1098 
1099  STD_RETURN_TYPE_e retval = STD_OK;
1100  resetSource_t rstReason = MINFO_GetResetSource();
1101  bool test_assertionRSTB = false; /* Do not test RSTB assertion on default */
1102 
1103  /** Assertion of RSTB pin will trigger reset, check if reset reason was power-cycle.
1104  If so, check if short circuit between FIN and RSTB pin exists */
1105  if (rstReason == POWERON_RESET) {
1106  /** First check if FIN is used */
1107  if (pInstance->fin.finUsed == true) {
1108  /** Write to NVRAM to determine after reset and if short-circuit
1109  * between RSTB and FIN present what exactly caused the reset. */
1110  pInstance->nvram.data->phase = (uint8_t)SBC_FIN_TEST;
1111  FRAM_WriteData(pInstance->nvram.entry);
1112 
1113  /** MCU SBC is connected to ECLK1 -> privilege mode is required to access register */
1115 
1116  /** Last reset was caused by power-cycle */
1117  /** Set level of FIN pin low and check if this generates reset */
1118  IO_PinReset(pInstance->fin.pGIOport, pInstance->fin.pin);
1119 
1120  /** Pulses longer than 2000ns trigger reset -> wait 10us to check if
1121  reset is triggered by short between RSTB and FIN */
1122  MCU_Delay_us(10u);
1123 
1124  /** If we reach this line of code, no reset has taken place.
1125  Everything okay. Set level of FIN pin back to high */
1126  IO_PinSet(pInstance->fin.pGIOport, pInstance->fin.pin);
1127 
1128  /** No further register access required -> leave privilege mode */
1130 
1131  /** FIN state okay, no short circuit. Update also in nvram struct */
1133  pInstance->fin.finState = STD_OK;
1134  pInstance->nvram.data->finState = STD_OK;
1135 
1136  /** Continue with RSTB assertion test */
1137  test_assertionRSTB = true;
1138  } else {
1139  /** Power-cycle but no FIN pin used -> continue with RSTB check */
1140  test_assertionRSTB = true;
1141  }
1142  } else if (rstReason == EXT_RESET) {
1143  /** Last reset reason was external reset via nRST pin (EXT_RESET)
1144  Readout FRAM to determine in which state the SBC was prior to reset */
1145  FRAM_ReadData(pInstance->nvram.entry);
1146  if ((SBC_INIT_PHASE_e)pInstance->nvram.data->phase == SBC_FIN_TEST) {
1147  /** Short-circuit between FIN and RSTB: Do not apply CLK on FIN */
1148  /** Update nvram FIN state */
1149  pInstance->nvram.data->finState = STD_NOT_OK;
1150  /** FIN state not okay, but still in SBC init phase after power-cycle
1151  * continue now with RSTB assertion */
1152  test_assertionRSTB = true;
1153  } else if ((SBC_INIT_PHASE_e)pInstance->nvram.data->phase == SBC_RSTB_ASSERTION_TEST) {
1154  /** Reset was triggered by SPI RSTB assertion test -> continue with SBC init phase */
1155  test_assertionRSTB = false;
1156 
1157  /** Diagnosis of the RSTB pin/event is available by reading the FS_SAFE_IOs register:
1158  * RSTB_EVENT bit reports an activation of RSTB pin. */
1159  SBC_ReadBackRegister(pInstance, true, FS8X_FS_SAFE_IOS_ADDR);
1160 
1161  /** Check RSTB_EVENT if RSTB has been activated */
1162  if (STD_OK ==
1165  /** RSTB pin should be sensed high and no RSTB short to high */
1167  uint16_t expRegisterValue =
1170  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.safeIos & mask), expRegisterValue)) {
1171  retval = STD_NOT_OK;
1172  }
1173  /** Reset RSTB_EVENT flag */
1175  /** Update diag flag */
1177  } else {
1178  /** RSTB has not been activated but this should have been the case */
1179  retval = STD_NOT_OK;
1181  }
1182  } else {
1183  /** Reset was not caused by SBC initialization or power-cycle.
1184  * Continue with SBC init phase as RSTB assertion is only tested
1185  * after power-cycle occurred */
1186  test_assertionRSTB = false;
1187  }
1188  /** Copy FIN state info from nvram variable into local state variable. This restores lost data from rest or
1189  updates local FIN state if short-circuit between FIN and RSTB has been detected */
1190  pInstance->fin.finState = pInstance->nvram.data->finState;
1191  if (pInstance->fin.finState == STD_OK) {
1193  } else {
1195  }
1196  } else {
1197  /** Reset was not caused by power-cycle or SBC. SBC has already been initialized successfully after detected
1198  * power-cycle. Everything okay. Read FIN state from NVRAM and continue with normal operation */
1199  FRAM_ReadData(pInstance->nvram.entry);
1200  test_assertionRSTB = false;
1201  pInstance->fin.finState = pInstance->nvram.data->finState;
1202  if (pInstance->fin.finState == STD_OK) {
1204  } else {
1206  }
1207  }
1208 
1209  /** Verify the hardware connection between the MCU reset pin and the FS85 reset pin */
1210  if (test_assertionRSTB == true) {
1211  /** Write to NVRAM to determine after reset and if RSTB was asserted correctly */
1212  pInstance->nvram.data->phase = (uint8_t)SBC_RSTB_ASSERTION_TEST;
1213  FRAM_WriteData(pInstance->nvram.entry);
1214 
1215  SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR);
1216 
1217  uint16_t registerValue = FS8X_FS_RSTB_REQ_RSTB_ASSERTION;
1218  SBC_WriteRegisterFsInit(pInstance, FS8X_FS_SAFE_IOS_ADDR, registerValue);
1219 
1220  while (true) {
1221  ;
1222  }
1223 
1224  /* Controller should never reach this point as reset via RSTB is requested */
1225  }
1226  return retval;
1227 }
1228 
1230  FAS_ASSERT(pInstance != NULL_PTR);
1231 
1232  STD_RETURN_TYPE_e retval = STD_OK;
1233  /* TBD */
1234  return retval;
1235 }
1236 
1237 /*========== Externalized Static Function Implementations (Unit Test) =======*/
1238 #ifdef UNITY_UNIT_TEST
1239 extern STD_RETURN_TYPE_e TEST_SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue) {
1240  return SBC_CheckRegisterValues(registerValue, expectedRegisterValue);
1241 }
1242 
1243 extern void TEST_SBC_UpdateRegister(
1244  FS85_STATE_s *pInstance,
1245  bool isFailSafe,
1246  uint32_t registerAddress,
1247  uint32_t registerValue) {
1248  return SBC_UpdateRegister(pInstance, isFailSafe, registerAddress, registerValue);
1249 }
1250 
1251 extern void TEST_SBC_UpdateFailSafeRegister(
1252  FS85_FS_REGISTER_s *pFsRegister,
1253  uint32_t registerAddress,
1254  uint32_t registerValue) {
1255  return SBC_UpdateFailSafeRegister(pFsRegister, registerAddress, registerValue);
1256 }
1257 
1258 extern void TEST_SBC_UpdateMainRegister(
1259  FS85_MAIN_REGISTERS_s *pMainRegister,
1260  uint32_t registerAddress,
1261  uint32_t registerValue) {
1262  return SBC_UpdateMainRegister(pMainRegister, registerAddress, registerValue);
1263 }
1264 
1265 #endif
DIAG_RETURNTYPE_e DIAG_Handler(DIAG_ID_e diagId, DIAG_EVENT_e event, DIAG_IMPACT_LEVEL_e impact, uint32_t data)
DIAG_Handler provides generic error handling, based on diagnosis group.
Definition: diag.c:243
Diagnosis driver header.
@ DIAG_EVENT_NOT_OK
Definition: diag_cfg.h:258
@ DIAG_EVENT_OK
Definition: diag_cfg.h:257
@ DIAG_SYSTEM
Definition: diag_cfg.h:270
@ DIAG_ID_SBC_RSTB_STATE
Definition: diag_cfg.h:234
@ DIAG_ID_SBC_FIN_STATE
Definition: diag_cfg.h:233
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:252
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:126
FRAM_RETURN_TYPE_e FRAM_ReadData(FRAM_BLOCK_ID_e blockId)
Reads a variable from the FRAM.
Definition: fram.c:193
FRAM_RETURN_TYPE_e FRAM_WriteData(FRAM_BLOCK_ID_e blockId)
Writes a variable to the FRAM.
Definition: fram.c:115
Header for the driver for the FRAM module.
FRAM_SBC_INIT_s fram_sbcInit
Definition: fram_cfg.c:71
@ FRAM_BLOCK_ID_SBC_INIT_STATE
Definition: fram_cfg.h:103
STD_RETURN_TYPE_e
Definition: fstd_types.h:81
@ STD_NOT_OK
Definition: fstd_types.h:83
@ STD_OK
Definition: fstd_types.h:82
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:76
Function to switch between user mode and privilege mode.
#define FSYS_SWITCH_TO_USER_MODE()
Switch back to user mode.
Definition: fsystem.h:129
long FSYS_RaisePrivilege(void)
Raise privilege.
#define UNIT_TEST_WEAK_IMPL
Definition: general.h:97
fs8x_status_t FS8x_GetFaultErrorCounterValue(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData, uint8_t *faultErrorCounterValue)
Reads actual Fault Error Counter value.
Definition: sbc_fs8x.c:270
fs8x_status_t FS8x_WD_Refresh(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData)
Performs the watchdog refresh.
Definition: sbc_fs8x.c:160
fs8x_status_t FS8x_WriteRegisterInit(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, uint8_t address, uint16_t writeData)
Performs a write to a single FS8x FS init register (during the INIT_FS phase only).
fs8x_status_t FS8x_WriteRegister(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, bool isFailSafe, uint8_t address, uint16_t writeData)
Sends write command to the FS8x.
fs8x_status_t FS8x_FS0B_Release(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData)
FS0B release routine.
Definition: sbc_fs8x.c:184
fs8x_status_t FS8x_ReadRegister(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, bool isFailSafe, uint8_t address, fs8x_rx_frame_t *rxData)
Performs a read from a single FS8x register.
fs8x_status_t
Status return codes.
@ fs8xSPI
@ fs8xStatusOk
@ fs8xStatusError
UNIT_TEST_WEAK_IMPL fs8x_status_t MCU_SPI_TransferData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint8_t *txFrame, uint16_t frameLengthBytes, uint8_t *rxFrame)
This function transfers single frame through blocking SPI communication in both directions....
Definition: nxpfs85xx.c:986
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:87
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:94
Header for the driver for the IO module.
resetSource_t MINFO_GetResetSource(void)
Get reason for last reset.
Definition: masterinfo.c:84
void MINFO_SetDebugProbeConnectionState(MINFO_DEBUG_PROBE_CONNECTION_STATE_e state)
Check if debug probe is connected.
Definition: masterinfo.c:88
General foxBMS-master system information.
@ MINFO_DEBUG_PROBE_CONNECTED
Definition: masterinfo.h:68
@ MINFO_DEBUG_PROBE_NOT_CONNECTED
Definition: masterinfo.h:67
void MCU_Delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:86
Headers for the driver for the MCU module.
static void SBC_UpdateMainRegister(FS85_MAIN_REGISTERS_s *pMainRegister, uint32_t registerAddress, uint32_t registerValue)
Updates main register values.
Definition: nxpfs85xx.c:304
static void SBC_UpdateRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint32_t registerAddress, uint32_t registerValue)
Updates register values.
Definition: nxpfs85xx.c:363
STD_RETURN_TYPE_e FS85_InitializeNumberOfRequiredWatchdogRefreshes(FS85_STATE_s *pInstance, uint8_t *requiredWatchdogRefreshes)
Calculates the number of required watchdog refresh to reset fault error counter.
Definition: nxpfs85xx.c:882
static void SBC_UpdateFailSafeRegister(FS85_FS_REGISTER_s *pFsRegister, uint32_t registerAddress, uint32_t registerValue)
Updates fail safe register values.
Definition: nxpfs85xx.c:242
static STD_RETURN_TYPE_e SBC_ReadBackRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress)
Reads SBC register value.
Definition: nxpfs85xx.c:381
static STD_RETURN_TYPE_e SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue)
Checks register value against expected value.
Definition: nxpfs85xx.c:232
FS85_STATE_s fs85xx_mcuSupervisor
Definition: nxpfs85xx.c:81
STD_RETURN_TYPE_e FS85_InitializeFsPhase(FS85_STATE_s *pInstance)
Configures SBC during INIT_FS phase.
Definition: nxpfs85xx.c:497
static STD_RETURN_TYPE_e SBC_PerformPathCheckRstb(FS85_STATE_s *pInstance)
Perform RSTB safety path check.
Definition: nxpfs85xx.c:1096
static STD_RETURN_TYPE_e SBC_PerformPathCheckFs0b(FS85_STATE_s *pInstance)
Perform FS0B safety path check.
Definition: nxpfs85xx.c:1229
STD_RETURN_TYPE_e SBC_TriggerWatchdog(FS85_STATE_s *pInstance)
Trigger watchdog.
Definition: nxpfs85xx.c:1020
static STD_RETURN_TYPE_e SBC_WriteRegisterFsInit(FS85_STATE_s *pInstance, uint8_t registerAddress, uint16_t registerValue)
Write to fail-safe register.
Definition: nxpfs85xx.c:401
static STD_RETURN_TYPE_e SBC_ClearRegisterFlags(FS85_STATE_s *pInstance, uint8_t registerAddress, bool isFailSafe, uint16_t registerValue)
Clears flags in register.
Definition: nxpfs85xx.c:457
static STD_RETURN_TYPE_e SBC_ReadBackAllRegisters(FS85_STATE_s *pInstance)
Definition: nxpfs85xx.c:1054
STD_RETURN_TYPE_e FS85_SafetyPathChecks(FS85_STATE_s *pInstance)
Performs SBC safety path checks.
Definition: nxpfs85xx.c:954
SBC_INIT_PHASE_e
Definition: nxpfs85xx.c:73
@ SBC_UNINITIALIZED
Definition: nxpfs85xx.c:74
@ SBC_FIN_TEST
Definition: nxpfs85xx.c:75
@ SBC_INITIALIZED
Definition: nxpfs85xx.c:77
@ SBC_RSTB_ASSERTION_TEST
Definition: nxpfs85xx.c:76
static STD_RETURN_TYPE_e SBC_WriteBackRegisterFsInit(FS85_STATE_s *pInstance, uint8_t registerAddress, uint16_t registerValue)
Write to fail-safe register.
Definition: nxpfs85xx.c:423
STD_RETURN_TYPE_e FS85_CheckFaultErrorCounter(FS85_STATE_s *pInstance)
Checks if fault error counter is zero.
Definition: nxpfs85xx.c:939
Header for the driver for the FRAM module.
@ SBC_DEBUG_MODE
Definition: nxpfs85xx.h:112
@ SBC_NORMAL_MODE
Definition: nxpfs85xx.h:111
#define FS8x_WD_SEED_DEFAULT
Watchdog seed default value.
Definition: sbc_fs8x.h:59
#define FS8x_BO_GET_REG_VALUE(value, mask, shift)
Macro for getting value from register.
#define FS8x_COMM_FRAME_SIZE
#define FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB
#define FS8X_FS_VDDIO_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_I_WD_RFR_CNT_MASK
#define FS8X_FS_BAD_WD_TIMING_MASK
#define FS8X_FS_VMON2_OV_OVERVOLTAGE_REPORTED
#define FS8X_M_VBOOSTUVH_EVENT_OCCURRED
#define FS8X_FS_I_ERRMON_FS_IMPACT_FS0B
#define FS8X_FS_VCOREMON_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_FCCU1_ERROR_DETECTED
#define FS8X_FS_RSTB_DIAG_MASK
#define FS8X_FS_I_FCCU_CFG_NO_MONITORING
#define FS8X_FS_RSTB_REQ_RSTB_ASSERTION
#define FS8X_M_WK2FLG_EVENT_OCCURRED
#define FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE
#define FS8X_M_INT_MASK2_ADDR
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I_ERRMON_ACK_TIME_32MS
#define FS8X_FS_WDW_DC_50
#define FS8X_FS_FSM_STATE_INIT_FS
#define FS8X_FS_I_FCCU1_FLT_POL_FCCU1_L
#define FS8X_FS_ABIST1_OK_PASS
#define FS8X_FS_I_VMON2_ABIST2_VMON2_BIST
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_DBG_MODE_MASK
#define FS8X_M_MEMORY1_ADDR
#define FS8X_FS_ABIST2_OK_MASK
#define FS8X_FS_I_VMON3_ABIST2_VMON3_BIST
#define FS8X_FS_RSTB_EVENT_MASK
#define FS8X_FS_SPI_FS_CRC_ERROR_DETECTED
#define FS8X_FS_I_WD_RFR_LIMIT_2
#define FS8X_FS_SPI_FS_CLK_WRONG_NUMBER_OF_CLOCK_CYCLES
#define FS8X_FS_LBIST_OK_MASK
#define FS8X_FS_BAD_WD_DATA_BAD_WD_REFRESH
#define FS8X_FS_I2C_FS_CRC_ERROR_DETECTED
#define FS8X_FS_WD_ANSWER_ADDR
#define FS8X_FS_VMON3_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_FSM_STATE_MASK
#define FS8X_M_REG_CTRL2_ADDR
Definition: sbc_fs8x_map.h:696
#define FS8X_M_VBOSUVH_EVENT_OCCURRED
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_RSTB_DIAG_NO_FAILURE
#define FS8X_FS_RSTB_EVENT_RESET_OCCURRED
#define FS8X_FS_RELEASE_FS0B_ADDR
#define FS8X_FS_WD_WINDOW_ADDR
#define FS8X_FS_VCOREMON_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT
#define FS8X_M_DEVICEID_ADDR
#define FS8X_M_FLAG1_ADDR
#define FS8X_FS_BAD_WD_TIMING_BAD_WD_REFRESH
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I2C_FS_REQ_I2C_VIOLATION
#define FS8X_M_VMON_REGX_ADDR
#define FS8X_FS_I_RSTB_DUR_10MS
#define FS8X_FS_I_WD_RFR_LIMIT_SHIFT
#define FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST
#define FS8X_M_VSUPUVL_EVENT_OCCURRED
#define FS8X_FS_I_VMON4_ABIST2_VMON4_BIST
#define FS8X_FS_ERRMON_ERROR_DETECTED
#define FS8X_M_REG_CTRL1_ADDR
Definition: sbc_fs8x_map.h:432
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_RSTB_SNS_PAD_SENSED_HIGH
#define FS8X_FS_VMON4_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I_FLT_ERR_CNT_1
#define FS8X_M_FLAG_ADDR
Definition: sbc_fs8x_map.h:57
#define FS8X_FS_WD_SEED_ADDR
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I_WD_RFR_LIMIT_6
#define FS8X_M_MODE_ADDR
Definition: sbc_fs8x_map.h:304
#define FS8X_FS_VMON4_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_RSTB_DRV_COMMAND_SENSED_HIGH
#define FS8X_FS_I_WD_RFR_LIMIT_MASK
#define FS8X_FS_DBG_MODE_NO_DEBUG
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_OTP_CORRUPT_MASK
#define FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION
#define FS8X_FS_I_VMON1_ABIST2_VMON1_BIST
#define FS8X_FS_WD_WINDOW_128MS
#define FS8X_FS_I_SAFE_INPUTS_ADDR
#define FS8X_FS_INTB_MASK_ADDR
#define FS8X_FS_SAFE_IOS_ADDR
#define FS8X_M_CLOCK_ADDR
#define FS8X_FS_I_OVUV_SAFE_REACTION1_ADDR
#define FS8X_M_VSUPUVH_EVENT_OCCURRED
#define FS8X_FS_OVUVREG_STATUS_ADDR
#define FS8X_FS_I_FSSM_ADDR
#define FS8X_FS_FS_OSC_DRIFT_OSCILLATOR_DRIFT
#define FS8X_FS_I_WD_CFG_ADDR
#define FS8X_FS_VMON2_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_FS_DIG_REF_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_FS_WD_G_MASK
#define FS8X_FS_DIAG_SAFETY_ADDR
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_FCCU12_ERROR_DETECTED
#define FS8X_FS_VMON1_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_RSTB_DRV_MASK
#define FS8X_M_VPREUVH_EVENT_OCCURRED
#define FS8X_FS_VMON1_UV_UNDERVOLTAGE_REPORTED
#define FS8X_M_VSUPUV7_EVENT_OCCURRED
#define FS8X_M_INT_MASK1_ADDR
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_VMON3_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_WDW_RECOVERY_128MS
#define FS8X_FS_RSTB_SNS_MASK
#define FS8X_FS_I_SVS_ADDR
#define FS8X_FS_VDDIO_OV_OVERVOLTAGE_REPORTED
#define FS8X_M_LVB1_SVS_ADDR
#define FS8X_FS_I_FCCU1_FS_REACT_FS0B
#define FS8X_FS_SPI_FS_REQ_SPI_VIOLATION
#define FS8X_M_FLAG2_ADDR
#define FS8X_FS_I_WD_RFR_CNT_SHIFT
#define FS8X_FS_FS_WD_G_GOOD_WD_REFRESH
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_8
#define FS8X_FS_GO_TO_INITFS_GO_BACK_TO_INIT_FS
#define FS8X_FS_I_OVUV_SAFE_REACTION2_ADDR
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_NO_EFFECT
#define FS8X_M_VPREUVL_EVENT_OCCURRED
#define FS8X_FS_OTP_CORRUPT_NO_ERROR
#define FS8X_FS_ABIST1_OK_MASK
#define FS8X_FS_LBIST_OK_PASS
#define FS8X_FS_BAD_WD_DATA_MASK
#define FS8X_FS_I_WD_RFR_LIMIT_4
#define FS8X_M_AMUX_ADDR
Definition: sbc_fs8x_map.h:882
#define FS8X_FS_STATES_ADDR
#define FS8X_M_MEMORY0_ADDR
#define FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST
#define FS8X_FS_GRL_FLAGS_ADDR
#define FS8X_FS_FCCU2_ERROR_DETECTED
STD_RETURN_TYPE_e SPI_TransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:148
SPI_INTERFACE_CONFIG_s spi_kSbcMcuInterface
Definition: spi_cfg.c:251
uint8_t phase
Definition: fram_cfg.h:125
STD_RETURN_TYPE_e finState
Definition: fram_cfg.h:126
volatile uint32_t * pGIOport
Definition: nxpfs85xx.h:119
STD_RETURN_TYPE_e finState
Definition: nxpfs85xx.h:118
uint16_t diag_safety
Definition: nxpfs85xx.h:85
uint16_t releaseFs0bPin
Definition: nxpfs85xx.h:83
uint16_t i_svs
Definition: nxpfs85xx.h:78
uint16_t iWatchdogConfiguration
Definition: nxpfs85xx.h:75
uint16_t watchdogAnswer
Definition: nxpfs85xx.h:81
uint16_t overvoltageUndervoltageRegisterStatus
Definition: nxpfs85xx.h:82
uint16_t i_safe_inputs
Definition: nxpfs85xx.h:76
uint16_t iOvervoltageUndervoltageSafeReaction2
Definition: nxpfs85xx.h:74
uint16_t safeIos
Definition: nxpfs85xx.h:84
uint16_t watchdogSeed
Definition: nxpfs85xx.h:80
uint16_t iFailSafeSateMachine
Definition: nxpfs85xx.h:77
uint16_t grl_flags
Definition: nxpfs85xx.h:72
uint16_t watchdogWindow
Definition: nxpfs85xx.h:79
uint16_t states
Definition: nxpfs85xx.h:87
uint16_t intb_mask
Definition: nxpfs85xx.h:86
uint16_t iOvervoltageUndervoltageSafeReaction1
Definition: nxpfs85xx.h:73
uint16_t registerControl1
Definition: nxpfs85xx.h:95
uint16_t registerControl2
Definition: nxpfs85xx.h:96
uint16_t analogMultiplexer
Definition: nxpfs85xx.h:97
FRAM_BLOCK_ID_e entry
Definition: nxpfs85xx.h:125
FRAM_SBC_INIT_s * data
Definition: nxpfs85xx.h:126
FS85_MAIN_REGISTERS_s mainRegister
Definition: nxpfs85xx.h:134
FS85_OPERATION_MODE_e mode
Definition: nxpfs85xx.h:137
FS85_FS_REGISTER_s fsRegister
Definition: nxpfs85xx.h:135
FS85_NVRAM_INFO_s nvram
Definition: nxpfs85xx.h:136
FS85_FIN_CONFIGURATION_s fin
Definition: nxpfs85xx.h:133
fs8x_drv_data_t configValues
Definition: nxpfs85xx.h:132
SPI_INTERFACE_CONFIG_s * pSpiInterface
Definition: nxpfs85xx.h:131
Structure representing received data frame.
uint16_t readData
Content of a read register.