foxBMS  1.3.0
The foxBMS Battery Management System API Documentation
nxpfs85xx.c
Go to the documentation of this file.
1 /**
2  *
3  * @copyright © 2010 - 2022, Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright notice, this
12  * list of conditions and the following disclaimer.
13  *
14  * 2. Redistributions in binary form must reproduce the above copyright notice,
15  * this list of conditions and the following disclaimer in the documentation
16  * and/or other materials provided with the distribution.
17  *
18  * 3. Neither the name of the copyright holder nor the names of its
19  * contributors may be used to endorse or promote products derived from
20  * this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * We kindly request you to use one or more of the following phrases to refer to
34  * foxBMS in your hardware, software, documentation or advertising materials:
35  *
36  * - ″This product uses parts of foxBMS®″
37  * - ″This product includes parts of foxBMS®″
38  * - ″This product is derived from foxBMS®″
39  *
40  */
41 
42 /**
43  * @file nxpfs85xx.c
44  * @author foxBMS Team
45  * @date 2020-03-18 (date of creation)
46  * @updated 2022-05-30 (date of last update)
47  * @version v1.3.0
48  * @ingroup DRIVERS
49  * @prefix SBC
50  *
51  * @brief Driver for the SBC module
52  *
53  * @details It must always be used when creating new c source files.
54  *
55  */
56 
57 /*========== Includes =======================================================*/
58 #include "nxpfs85xx.h"
59 
60 #include "HL_gio.h"
61 #include "HL_system.h"
62 
63 #include "diag.h"
64 #include "fram.h"
65 #include "fsystem.h"
66 #include "io.h"
67 #include "masterinfo.h"
68 #include "mcu.h"
69 
70 /*========== Macros and Definitions =========================================*/
71 
72 /*========== Static Constant and Variable Definitions =======================*/
73 typedef enum {
79 
80 /*========== Extern Constant and Variable Definitions =======================*/
83  .configValues.watchdogSeed = FS8x_WD_SEED_DEFAULT,
84  .configValues.communicationMode = fs8xSPI,
85  .configValues.i2cAddressOtp = 0, /* Not used as SPI is selected */
86  .fin.finUsed = true,
87  .fin.finState = STD_NOT_OK,
88  .fin.pGIOport = &(systemREG1->SYSPC4), /* FIN connected to ECLK1 (ball A12): PRIVILEGE MODE REQUIRED! */
89  .fin.pin = 0,
90  .mainRegister = {0},
91  .fsRegister = {0},
92  .nvram.entry = FRAM_BLOCK_ID_SBC_INIT_STATE,
93  .nvram.data = &fram_sbcInit,
94  .mode = SBC_NORMAL_MODE, /* default value */
95 };
96 
97 /*========== Static Function Prototypes =====================================*/
98 /**
99  * @brief Checks register value against expected value
100  * @details If actual register value equals expected value #STD_OK is
101  * returned if this is not the case this indicates an error and
102  * #STD_NOT_OK is returned.
103  * @param[in] registerValue actual register value of interest
104  * @param[in] expectedRegisterValue expected register value
105  * @return #STD_OK if register value equals expected, else #STD_NOT_OK
106  */
107 static STD_RETURN_TYPE_e SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue);
108 
109 /**
110  * @brief Updates register values
111  * @details Updates register value of passed SBC instance with new
112  * values
113  * @param[in,out] pInstance SBC instance that is updated
114  * @param[in] isFailSafe true if fail-safe register, false if main register
115  * @param[in] registerAddress address of register that is updated
116  * @param[in] registerValue register value
117  */
118 static void SBC_UpdateRegister(
119  FS85_STATE_s *pInstance,
120  bool isFailSafe,
121  uint32_t registerAddress,
122  uint32_t registerValue);
123 
124 /**
125  * @brief Reads SBC register value
126  * @details Reads SBC register value from registerAddress and updates
127  * register in SBC state variable if reading was successful
128  * @param[in,out] pInstance SBC instance that is updated
129  * @param[in] isFailSafe true if fail-safe register, false if main
130  * register
131  * @param[in] registerAddress address of register that is read from
132  * @return #STD_OK if reading was successful, otherwise #STD_NOT_OK
133  */
134 static STD_RETURN_TYPE_e SBC_ReadBackRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress);
135 
136 /**
137  * @brief Write to fail-safe register
138  * @details Writes to fail-safe register (can be done during FS_INIT phase
139  * only)
140  * @param[in] pInstance SBC instance that is updated
141  * @param[in] registerAddress address of register
142  * @param[in] registerValue value that is written into register
143  * @return #STD_OK if writting was successful, other #STD_NOT_OK
144  */
146  FS85_STATE_s *pInstance,
147  uint8_t registerAddress,
148  uint16_t registerValue);
149 
150 /**
151  * @brief Write to fail-safe register
152  * @details Writes to fail-safe register (can be done during FS_INIT
153  * phase only), reads back if write process was successful and
154  * afterwards updates register value of passed SBC instance
155  * @param[in,out] pInstance SBC instance that is updated
156  * @param[in] registerAddress address of register
157  * @param[in] registerValue value that is written into register
158  * @return #STD_OK if writting was successful, other #STD_NOT_OK
159  */
161  FS85_STATE_s *pInstance,
162  uint8_t registerAddress,
163  uint16_t registerValue);
164 
165 /**
166  * @brief Clears flags in register
167  * @details Writes to register, reads back if clear process was
168  * successful and afterwards updates register value of passed
169  * SBC instance
170  * @param[in,out] pInstance SBC instance that is updated
171  * @param[in] registerAddress address of register
172  * @param[in] isFailSafe true if fail-safe register, false if main register
173  * @param[in] registerValue value that is written into register
174  * @return #STD_OK if writting was successful, other #STD_NOT_OK
175  */
177  FS85_STATE_s *pInstance,
178  uint8_t registerAddress,
179  bool isFailSafe,
180  uint16_t registerValue);
181 
183 
184 /**
185  * @brief Perform RSTB safety path check
186  * @details This functions performs a safety path check to make sure
187  * external components connected to RSTB are available to
188  * bring the safety critical outputs to known levels during
189  * operation.
190  * @param[in,out] pInstance SBC instance for which the RSTB path is checked
191  * @return #STD_OK if path check was successful, other #STD_NOT_OK
192  */
194 
195 /**
196  * @brief Perform FS0B safety path check
197  * @details This functions performs a safety path check to make sure
198  * external components connected to FS0B are available to
199  * bring the safety critical outputs to known levels during
200  * operation.
201  * @param[in,out] pInstance SBC instance for which the FS0B path is checked
202  */
204 
205 /*========== Static Function Implementations ================================*/
206 static STD_RETURN_TYPE_e SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue) {
207  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
208  /* AXIVION Routine Generic-MissingParameterAssert: expectedRegisterValue: parameter accepts whole range */
209  STD_RETURN_TYPE_e retval = STD_OK;
210  if (registerValue != expectedRegisterValue) {
211  retval = STD_NOT_OK;
212  }
213  return retval;
214 }
215 
216 static void SBC_UpdateRegister(
217  FS85_STATE_s *pInstance,
218  bool isFailSafe,
219  uint32_t registerAddress,
220  uint32_t registerValue) {
221  FAS_ASSERT(pInstance != NULL_PTR);
222  FAS_ASSERT((isFailSafe == true) || (isFailSafe == false));
223  FAS_ASSERT(registerAddress <= FS8X_M_DEVICEID_ADDR);
224  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
225 
226  /* Check if fail-safe or main register needs to be updated */
227  if (isFailSafe == true) {
228  /* Update fail-safe register */
229  switch (registerAddress) {
231  pInstance->fsRegister.grl_flags = registerValue;
232  break;
233 
235  pInstance->fsRegister.iOvervoltageUndervolateSafeReaction1 = registerValue;
236  break;
237 
239  pInstance->fsRegister.iOvervoltageUndervolateSafeReaction2 = registerValue;
240  break;
241 
243  pInstance->fsRegister.iWatchdogConfiguration = registerValue;
244  break;
245 
247  pInstance->fsRegister.i_safe_inputs = registerValue;
248  break;
249 
250  case FS8X_FS_I_FSSM_ADDR:
251  pInstance->fsRegister.iFailSafeSateMachine = registerValue;
252  break;
253 
254  case FS8X_FS_I_SVS_ADDR:
255  pInstance->fsRegister.i_svs = registerValue;
256  break;
257 
259  pInstance->fsRegister.watchdogWindow = registerValue;
260  break;
261 
263  pInstance->fsRegister.watchdogSeed = registerValue;
264  break;
265 
267  pInstance->fsRegister.watchdogAnswer = registerValue;
268  break;
269 
271  pInstance->fsRegister.overvoltageUndervoltageRegisterStatus = registerValue;
272  break;
273 
275  pInstance->fsRegister.releaseFs0bPin = registerValue;
276  break;
277 
279  pInstance->fsRegister.safeIos = registerValue;
280  break;
281 
283  pInstance->fsRegister.diag_safety = registerValue;
284  break;
285 
287  pInstance->fsRegister.intb_mask = registerValue;
288  break;
289 
290  case FS8X_FS_STATES_ADDR:
291  pInstance->fsRegister.states = registerValue;
292  break;
293 
294  default:
295  FAS_ASSERT(FAS_TRAP); /* This case should never be reached */
296  break;
297  }
298  } else {
299  /* Update main register */
300  switch (registerAddress) {
301  case FS8X_M_FLAG_ADDR:
302  pInstance->mainRegister.flag = registerValue;
303  break;
304 
305  case FS8X_M_MODE_ADDR:
306  pInstance->mainRegister.mode = registerValue;
307  break;
308 
310  pInstance->mainRegister.registerControl1 = registerValue;
311  break;
312 
314  pInstance->mainRegister.registerControl2 = registerValue;
315  break;
316 
317  case FS8X_M_AMUX_ADDR:
318  pInstance->mainRegister.analogMultiplexer = registerValue;
319  break;
320 
321  case FS8X_M_CLOCK_ADDR:
322  pInstance->mainRegister.clock = registerValue;
323  break;
324 
326  pInstance->mainRegister.int_mask1 = registerValue;
327  break;
328 
330  pInstance->mainRegister.int_mask2 = registerValue;
331  break;
332 
333  case FS8X_M_FLAG1_ADDR:
334  pInstance->mainRegister.flag1 = registerValue;
335  break;
336 
337  case FS8X_M_FLAG2_ADDR:
338  pInstance->mainRegister.flag2 = registerValue;
339  break;
340 
342  pInstance->mainRegister.vmon_regx = registerValue;
343  break;
344 
346  pInstance->mainRegister.lvb1_svs = registerValue;
347  break;
348 
349  case FS8X_M_MEMORY0_ADDR:
350  pInstance->mainRegister.memory0 = registerValue;
351  break;
352 
353  case FS8X_M_MEMORY1_ADDR:
354  pInstance->mainRegister.memory1 = registerValue;
355  break;
356 
358  pInstance->mainRegister.deviceId = registerValue;
359  break;
360 
361  default:
362  FAS_ASSERT(FAS_TRAP); /* This case should never be reached */
363  break;
364  }
365  }
366 }
367 
368 static STD_RETURN_TYPE_e SBC_ReadBackRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress) {
369  FAS_ASSERT(pInstance != NULL_PTR);
370  FAS_ASSERT((isFailSafe == true) || (isFailSafe == false));
371  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
372 
373  STD_RETURN_TYPE_e retval = STD_NOT_OK;
374  fs8x_rx_frame_t rxTemp = {0};
375 
376  FAS_ASSERT(pInstance != NULL_PTR);
377 
378  if (fs8xStatusOk !=
379  FS8x_ReadRegister(pInstance->pSpiInterface, &(pInstance->configValues), isFailSafe, registerAddress, &rxTemp)) {
380  retval = STD_NOT_OK;
381  } else {
382  SBC_UpdateRegister(pInstance, isFailSafe, registerAddress, rxTemp.readData);
383  retval = STD_OK;
384  }
385  return retval;
386 }
387 
389  FS85_STATE_s *pInstance,
390  uint8_t registerAddress,
391  uint16_t registerValue) {
392  FAS_ASSERT(pInstance != NULL_PTR);
393  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
394  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
395 
396  STD_RETURN_TYPE_e retval = STD_OK;
397 
398  FAS_ASSERT(pInstance != NULL_PTR);
399 
400  /* Write to register */
401  if (fs8xStatusOk !=
402  FS8x_WriteRegisterInit(pInstance->pSpiInterface, &(pInstance->configValues), registerAddress, registerValue)) {
403  retval = STD_NOT_OK;
404  } else {
405  retval = STD_OK;
406  }
407  return retval;
408 }
409 
411  FS85_STATE_s *pInstance,
412  uint8_t registerAddress,
413  uint16_t registerValue) {
414  FAS_ASSERT(pInstance != NULL_PTR);
415  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
416  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
417 
418  STD_RETURN_TYPE_e retval = STD_OK;
419  fs8x_rx_frame_t rxTemp = {0};
420 
421  FAS_ASSERT(pInstance != NULL_PTR);
422 
423  /* Write to register */
424  if (fs8xStatusOk !=
425  FS8x_WriteRegisterInit(pInstance->pSpiInterface, &(pInstance->configValues), registerAddress, registerValue)) {
426  retval |= STD_NOT_OK;
427  } else {
428  /* Read back register value and check if write process was successful */
429  if (fs8xStatusOk !=
430  FS8x_ReadRegister(pInstance->pSpiInterface, &(pInstance->configValues), true, registerAddress, &rxTemp)) {
431  retval |= STD_NOT_OK;
432  } else {
433  if (rxTemp.readData == registerValue) {
434  /* Written register value equals read value */
435  SBC_UpdateRegister(pInstance, true, registerAddress, rxTemp.readData);
436  } else {
437  retval |= STD_NOT_OK;
438  }
439  }
440  }
441  return retval;
442 }
443 
445  FS85_STATE_s *pInstance,
446  uint8_t registerAddress,
447  bool isFailSafe,
448  uint16_t registerValue) {
449  FAS_ASSERT(pInstance != NULL_PTR);
450  /* AXIVION Routine Generic-MissingParameterAssert: registerAddress: parameter accepts whole range */
451  /* AXIVION Routine Generic-MissingParameterAssert: isFailSafe: parameter accepts whole range */
452  /* AXIVION Routine Generic-MissingParameterAssert: registerValue: parameter accepts whole range */
453 
454  STD_RETURN_TYPE_e retval = STD_OK;
455  fs8x_rx_frame_t rxTemp = {0};
456 
457  FAS_ASSERT(pInstance != NULL_PTR);
458 
459  /* Write to register */
460  if (fs8xStatusOk !=
462  pInstance->pSpiInterface, &(pInstance->configValues), isFailSafe, registerAddress, registerValue)) {
463  retval |= STD_NOT_OK;
464  } else {
465  /* Read back register value and check if write process was successful */
466  if (fs8xStatusOk !=
468  pInstance->pSpiInterface, &(pInstance->configValues), isFailSafe, registerAddress, &rxTemp)) {
469  retval |= STD_NOT_OK;
470  } else {
471  /* Check if all flags have been cleared: '1' is written to registers to clear respective flags */
472  if ((rxTemp.readData & registerValue) == 0u) {
473  /* Written register value equals read value */
474  SBC_UpdateRegister(pInstance, isFailSafe, registerAddress, rxTemp.readData);
475  } else {
476  retval |= STD_NOT_OK;
477  }
478  }
479  }
480  return retval;
481 }
482 
483 /*========== Extern Function Implementations ================================*/
485  FAS_ASSERT(pInstance != NULL_PTR);
486 
487  STD_RETURN_TYPE_e retval = STD_OK;
488  uint16_t registerMask = 0u;
489  uint16_t expRegisterValue = 0u;
490  uint16_t registerValue = 0u;
491 
492  FAS_ASSERT(pInstance != NULL_PTR);
493  /* Default init value: #STD_NOT_OK, will be set to #STD_OK later in init if
494  no short-circuit between FIN and RSTB detected. Do not apply external
495  clock on this pin until finState == #STD_OK */
496  FAS_ASSERT(pInstance->fin.finState == STD_NOT_OK);
497 
498  /** First: Verify following conditions:
499  1. Verify LBIST (logical-built-in-self-test) and ABIST1 (analog-built-in-self-test1) are pass
500  2. Verify Debug mode is not activated
501  3. Verify there is no OTP CRC error
502  4. Verify PGOOD was released: PGOOD is connected to power-on-reset of the MCU
503 
504  Second: Configure FS_I and FS_I_NOT registers
505 
506  - Write the desired data in the FS_I_Register_A (DATA)
507  - Write the opposite in the FS_I_NOT_Register_A (DATA_NOT)
508  - Only the utility bits must be inverted in the DATA_NOT content. The RESERVED bits are not considered and can be
509  written at '0'. If the comparison result is correct, then the REG_CORRUPT is set to '0'. If the comparison result
510  is wrong, then the REG_CORRUPT bit is set to '1'. The REG_CORRUPT monitoring is active as soon as the INIT_FS is
511  closed by the first good watchdog refresh. INIT_FS must be closed by the first good watchdog refresh before 256ms
512  timeout.
513 
514  1. Configure VCOREMON_OV_UV impact on RSTB and FS0B
515  2. Configure VDDIO_OV_UV impact on RSTB and FS0B
516  3. Configure VMONx_OV_UV impact on RSTB and FS0B
517  4. Configure ABIST2 assignment
518  5. Configure the WD window period, the WD window duty cycle, the WD counters limits,
519  and its impact on RSTB and FS0B. Ensure that the configuration does not violate the
520  FTTI requirement at system level.
521  6. Configure the Fault Error Counter limit and its impact on RSTB and FS0B at
522  intermediate value
523  7. Configure the RSTB pulse duration
524  8. Configure MCU FCCU error monitoring and its impact on RSTB and FS0B
525  9. Configure Ext. IC error monitoring and its impact on RSTB and FS0B
526  10.Configure FS0B short to high impact on RSTB
527 
528  Third: Execute
529 
530  1. Close INIT_FS by sending the first good WD refresh
531  2. Execute ABIST2 and verify it is pass
532  3. Clear all the flags by writing in FS_DIAG_SAFETY, FS_OVUVREG_STATUS
533  4. Clear the fault error counter to 0 with consecutive good WD refresh
534  5. Perform RSTB path check (repeat steps 1 to 4 after RSTB is released)
535  6. Release FS0B pin
536  7. Perform FS0B safety path check
537  8. Refresh the WD according to its configuration
538  9. Check FS_GRL_FLAGS register after each WD refresh
539 
540  The FS85 is now ready. If everything is OK for the MCU, it can release its own
541  safety path and the ECU starts.
542  */
543 
544  /* --------------------- First: Verify --------------------------------- */
545 
546  /** 1.: Verify LBIST and ABIST1 */
547  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_DIAG_SAFETY_ADDR)) {
548  retval = STD_NOT_OK;
549  }
551  expRegisterValue = (FS8X_FS_LBIST_OK_PASS | FS8X_FS_ABIST1_OK_PASS);
552  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
553  retval = STD_NOT_OK;
554  }
555 
556  /** Read FS STATES register */
557  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR)) {
558  retval = STD_NOT_OK;
559  }
560 
561  /** 2.: Check if debug mode is active */
562  registerMask = FS8X_FS_DBG_MODE_MASK;
563  expRegisterValue = FS8X_FS_DBG_MODE_NO_DEBUG;
564  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
565  /* Debug mode active: this can only be the case if debugger connected */
567  pInstance->mode = SBC_DEBUG_MODE;
568  } else {
569  /* Debug mode not active: no debugger connected */
571  pInstance->mode = SBC_NORMAL_MODE;
572  }
573 
574  /** 3.: Verify that no OPT CRC error */
575  registerMask = FS8X_FS_OTP_CORRUPT_MASK;
576  expRegisterValue = FS8X_FS_OTP_CORRUPT_NO_ERROR;
577  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
578  retval = STD_NOT_OK;
579  }
580 
581  /** -------- Second: Configure fail-safe init registers ------------------*/
582  /** Check if SBC is in FS_INIT state, if not switch SBC in FS_INIT state.
583  * Specific configurations can only be done in FS_INIT state */
584  registerMask = FS8X_FS_FSM_STATE_MASK;
585  expRegisterValue = FS8X_FS_FSM_STATE_INIT_FS;
586  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
587  /* SBC not in FS_INIT state -> request FS_INIT state */
588  /* Write FS_STATE request */
590  if (STD_OK != SBC_WriteRegisterFsInit(pInstance, FS8X_FS_SAFE_IOS_ADDR, registerValue)) {
591  retval = STD_NOT_OK;
592  } else {
593  /* Check if SBC now in FS_STATE */
594  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR)) {
595  retval = STD_NOT_OK;
596  } else {
597  /* Read register now check if SBC in FS_INIT state */
598  if (STD_OK !=
599  SBC_CheckRegisterValues((pInstance->fsRegister.states & registerMask), expRegisterValue)) {
600  /* SBC not in FS_INIT state -> error */
601  retval = STD_NOT_OK;
602  }
603  }
604  }
605  }
606 
607  /** 1.: Configure VCOREMON_OV_UV impact on RSTB and FS0B */
608  /** 2.: Configure VDDIO_OV_UV impact on RSTB and FS0B */
609  /** 4.: Configure ABIST2 assignment */
610  registerValue = 0;
611 
612  /** Select VCOREMON_OV options:
613  * - FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT
614  * - FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B
615  * - FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B_RSTB */
617 
618  /** Select VCOREMON_UV options:
619  * - FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT
620  * - FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B
621  * - FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B_RSTB */
623 
624  /** Select VDDIO_OV options:
625  * - FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT
626  * - FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B
627  * - FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B_RSTB */
629 
630  /** Select VDDIO_UV options:
631  * - FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT
632  * - FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B
633  * - FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B_RSTB */
635 
636  /** Select ABIST2 options:
637  * + VCOREMON
638  * - FS8X_FS_I_VCOREMON_ABIST2_NO_ABIST
639  * - FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST
640  * + VDDIO
641  * - FS8X_FS_I_VDDIO_ABIST2_NO_ABIST
642  * - FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST
643  * + VMONx (VMON1 - VMON4)
644  * - FS8X_FS_I_VMONx_ABIST2_NO_ABIST
645  * - FS8X_FS_I_VMONx_ABIST2_VMONx_BIST */
647  registerValue |= FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST;
648  registerValue |= FS8X_FS_I_VMON1_ABIST2_VMON1_BIST;
649  registerValue |= FS8X_FS_I_VMON2_ABIST2_VMON2_BIST;
650  registerValue |= FS8X_FS_I_VMON3_ABIST2_VMON3_BIST;
651  registerValue |= FS8X_FS_I_VMON4_ABIST2_VMON4_BIST;
652 
653  /* Write register */
654  if (STD_OK != SBC_WriteBackRegisterFsInit(pInstance, FS8X_FS_I_OVUV_SAFE_REACTION1_ADDR, registerValue)) {
655  retval = STD_NOT_OK;
656  }
657 
658  /** 3.: Configure VMONx_OV_UV impact on RSTB and FS0B */
659  registerValue = 0;
660  /** Select VMONx_OV options:
661  * - FS8X_FS_I_VMONx_OV_FS_IMPACT_NO_EFFECT
662  * - FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B
663  * - FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B_RSTB */
668 
669  /** Select VMONx_UV options:
670  * - FS8X_FS_I_VMONx_UV_FS_IMPACT_NO_EFFECT
671  * - FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B
672  * - FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B_RSTB */
677 
678  /* Write register */
679  if (STD_OK != SBC_WriteBackRegisterFsInit(pInstance, FS8X_FS_I_OVUV_SAFE_REACTION2_ADDR, registerValue)) {
680  retval = STD_NOT_OK;
681  }
682 
683  /** 5.: Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and
684  FS0B. Ensure that the configuration does not violate the FTTI requirement at system level. */
685  registerValue = 0;
686 
687  /** WD window period options:
688  * - FS8X_FS_WD_WINDOW_DISABLE
689  * - FS8X_FS_WD_WINDOW_xxxxMS */
690  registerValue |= FS8X_FS_WD_WINDOW_128MS;
691 
692  /** WD window duty cycle options:
693  * - FS8X_FS_WDW_DC_31_25
694  * - FS8X_FS_WDW_DC_37_5
695  * - FS8X_FS_WDW_DC_50
696  * - FS8X_FS_WDW_DC_62_5
697  * - FS8X_FS_WDW_DC_68_75 */
698  registerValue |= FS8X_FS_WDW_DC_50;
699 
700  /** WD fault recovery strategy
701  * - FS8X_FS_WDW_RECOVERY_DISABLE
702  * - FS8X_FS_WDW_RECOVERY_xxxxMS */
703  registerValue |= FS8X_FS_WDW_RECOVERY_128MS;
704 
705  /* Write register */
706  if (STD_OK != SBC_WriteBackRegisterFsInit(pInstance, FS8X_FS_WD_WINDOW_ADDR, registerValue)) {
707  retval = STD_NOT_OK;
708  }
709 
710  /** 6.: Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value */
711  /** Configure the RSTB pulse duration */
712  /** Configure FS0B short to high impact on RSTB */
713  registerValue = 0;
714 
715  /** Fault Error Counter limit options:
716  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_2
717  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_4
718  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_6
719  * - FS8X_FS_I_FLT_ERR_CNT_LIMIT_8 */
720  registerValue |= FS8X_FS_I_FLT_ERR_CNT_LIMIT_8;
721 
722  /** Fault Error Counter impact options:
723  * - FS8X_FS_I_FLT_ERR_IMPACT_NO_EFFECT
724  * - FS8X_FS_I_FLT_ERR_IMPACT_FS0B
725  * - FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB */
726  registerValue |= FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB;
727 
728  /** 7.: RSTB pulse duration options:
729  * - FS8X_FS_I_RSTB_DUR_1MS
730  * - FS8X_FS_I_RSTB_DUR_10MS */
731  registerValue |= FS8X_FS_I_RSTB_DUR_10MS;
732 
733  /** 10.: FS0B short to high impact on RSTB options:
734  * - FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION
735  * - FS8X_FS_I_FS0B_SC_HIGH_CFG_RESET_ASSERTED */
737 
738  /** After POR fault-error counter is set to 1 on default, it is reset after two consecutive good WD refreshes. This
739  part of the register is read-only so a write access has no influence. Set this bit for a successful comparison
740  between written and read register value */
741  registerValue |= FS8X_FS_I_FLT_ERR_CNT_1;
742 
743  /* Write register */
744  if (STD_OK != SBC_WriteRegisterFsInit(pInstance, FS8X_FS_I_FSSM_ADDR, registerValue)) {
745  retval = STD_NOT_OK;
746  }
747 
748  /** 8.: Configure MCU FCCU error monitoring and its impact on RSTB and FS0B */
749  /** 9.: Configure Ext. IC error monitoring and its impact on RSTB and FS0B */
750  registerValue = 0;
751 
752  /** MCU FCCU error monitoring options:
753  * + Input option:
754  * - FS8X_FS_I_FCCU_CFG_NO_MONITORING
755  * - FS8X_FS_I_FCCU_CFG_FCCU1_INPUT
756  * - FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_INPUT
757  * - FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_PAIR (bi-stable protocol)
758  * + Polarity option (independent):
759  * - FS8X_FS_I_FCCUx_FLT_POL_FCCUx_L
760  * - FS8X_FS_I_FCCUx_FLT_POL_FCCUx_H
761  * + Polarity option (bi-stable)
762  * - FS8X_FS_I_FCCU12_FLT_POL_FCCU1_L_FCCU2_H
763  * - FS8X_FS_I_FCCU12_FLT_POL_FCCU1_H_FCCU2_L
764  * + Impact option (independent)
765  * - FS8X_FS_I_FCCUx_FS_REACT_FS0B
766  * - FS8X_FS_I_FCCUx_FS_REACT_FS0B_RSTB
767  * + Impact option (bi-stable)
768  * - FS8X_FS_I_FCCU12_FS_IMPACT_FS0B
769  * - FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB
770  */
771  registerValue |= FS8X_FS_I_FCCU_CFG_NO_MONITORING;
772  registerValue |= FS8X_FS_I_FCCU1_FLT_POL_FCCU1_L;
773  registerValue |= FS8X_FS_I_FCCU1_FS_REACT_FS0B;
774 
775  /** Ext. IC error monitoring options:
776  * + Polarity options:
777  * - FS8X_FS_I_ERRMON_FLT_POLARITY_NEGATIVE_EDGE
778  * - FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE
779  * + Error acknowledgment time options:
780  * - FS8X_FS_I_ERRMON_ACK_TIME_1MS
781  * - FS8X_FS_I_ERRMON_ACK_TIME_8MS
782  * - FS8X_FS_I_ERRMON_ACK_TIME_16MS
783  * - FS8X_FS_I_ERRMON_ACK_TIME_32MS
784  * + Error monitoring impact options:
785  * - FS8X_FS_I_ERRMON_FS_IMPACT_FS0B
786  * - FS8X_FS_I_ERRMON_FS_IMPACT_FS0B_RSTB */
788  registerValue |= FS8X_FS_I_ERRMON_ACK_TIME_32MS;
789  registerValue |= FS8X_FS_I_ERRMON_FS_IMPACT_FS0B;
790 
791  /* Write register */
792  if (STD_OK != SBC_WriteRegisterFsInit(pInstance, FS8X_FS_I_SAFE_INPUTS_ADDR, registerValue)) {
793  retval = STD_NOT_OK;
794  }
795 
796  /* -------------------- Third: Execute --------------------------------- */
797 
798  /** 1.: Close INIT_FS by sending the first good WD refresh */
799  if (STD_OK != SBC_TriggerWatchdog(pInstance)) {
800  retval = STD_NOT_OK;
801  }
802  /** 2.: Execute ABIST2 and verify it is pass */
803  /** ABIST2 is executed automatically after closing of INIT_FS, duration: 1.2ms max */
804  MCU_Delay_us(1200u);
805 
806  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_DIAG_SAFETY_ADDR)) {
807  retval = STD_NOT_OK;
808  }
809  registerMask = FS8X_FS_ABIST2_OK_MASK;
810  expRegisterValue = FS8X_FS_ABIST2_OK_MASK;
811  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
812  retval = STD_NOT_OK;
813  }
814 
815  /** 3.: Clear all the flags by writing in FS_DIAG_SAFETY */
816  registerValue = 0;
817  /** Flags are cleared by writting '1' to register */
819  registerValue |= FS8X_FS_ERRMON_ERROR_DETECTED;
821  registerValue |=
825  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_FS_DIAG_SAFETY_ADDR, true, registerValue)) {
826  retval = STD_NOT_OK;
827  }
828 
829  /** Clear all the flags by writing in FS_OVUVREG_STATUS */
830  registerValue = 0;
831  /** Flags are cleared by writting '1' to register */
834  registerValue |=
840  registerValue |= FS8X_FS_FS_OSC_DRIFT_OSCILLATOR_DRIFT;
841  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_FS_OVUVREG_STATUS_ADDR, true, registerValue)) {
842  retval = STD_NOT_OK;
843  }
844 
845  /** Clear flags FLAG1 register */
846  registerValue = FS8X_M_VBOSUVH_EVENT_OCCURRED;
847  registerValue |= FS8X_M_VBOOSTUVH_EVENT_OCCURRED;
848  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_M_FLAG1_ADDR, false, registerValue)) {
849  retval = STD_NOT_OK;
850  }
851 
852  /** Clear flags FLAG2 register */
853  registerValue = FS8X_M_VSUPUV7_EVENT_OCCURRED;
854  registerValue |=
857  if (STD_OK != SBC_ClearRegisterFlags(pInstance, FS8X_M_FLAG2_ADDR, false, registerValue)) {
858  retval = STD_NOT_OK;
859  }
860 
861  /** Read out all registers for debug purpose */
862  if (STD_OK != SBC_ReadBackAllRegisters(pInstance)) {
863  retval = STD_OK;
864  }
865 
866  return retval;
867 }
868 
870  FS85_STATE_s *pInstance,
871  uint8_t *requiredWatchdogRefreshes) {
872  FAS_ASSERT(pInstance != NULL_PTR);
873  FAS_ASSERT(requiredWatchdogRefreshes != NULL_PTR);
874 
875  STD_RETURN_TYPE_e retval = STD_OK;
876 
877  /** Clear the fault error counter to 0 with consecutive good WD refreshes.
878  * The watchdog refresh counter is used to decrement the fault error counter. Each time the watchdog is properly
879  * refreshed, the watchdog refresh counter is incremented by '1'. Each time the watchdog refresh counter reaches
880  * its maximum value ('6' by default) and if next WD refresh is also good, the fault error counter is decremented
881  * by '1'. Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog,
882  * the watchdog refresh counter is reset to '0'. */
883 
884  /** Read out FS_I_WD_CFG register to get watchdog refresh counter limit and value */
885  if (STD_OK != SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_WD_CFG_ADDR)) {
886  retval = STD_NOT_OK;
887  }
888 
889  /** Get refresh counter value */
890  uint8_t watchdogRefreshLimit = 0;
891  uint8_t watchdogRefreshCounter = FS8x_BO_GET_REG_VALUE(
893 
894  /** Get refresh counter limit register value */
898  watchdogRefreshLimit = 6u;
899  } else if (
903  watchdogRefreshLimit = 4u;
904  } else if (
908  watchdogRefreshLimit = 2u;
909  } else {
910  watchdogRefreshLimit = 1u;
911  }
912 
913  /** Get fault error counter */
914  uint8_t faultCounter = 0u;
915  if (fs8xStatusOk !=
916  FS8x_GetFaultErrorCounterValue(pInstance->pSpiInterface, &(pInstance->configValues), &faultCounter)) {
917  retval = STD_NOT_OK;
918  }
919 
920  /** Get number of required watchdog refreshes to clear fault error counter to 0 */
921  *requiredWatchdogRefreshes = faultCounter + (watchdogRefreshLimit - watchdogRefreshCounter);
922 
923  return retval;
924 }
925 
927  FAS_ASSERT(pInstance != NULL_PTR);
928  /* AXIVION Routine Generic-MissingParameterAssert: parameters without assertion accept whole range of data type */
929 
930  STD_RETURN_TYPE_e retval = STD_OK;
931 
932  /* Check fault error counter */
933  uint8_t faultCounter = 0u;
934  retval |= FS8x_GetFaultErrorCounterValue(pInstance->pSpiInterface, &(pInstance->configValues), &faultCounter);
935  if (faultCounter != 0u) {
936  retval = STD_NOT_OK;
937  }
938  return retval;
939 }
940 
942  FAS_ASSERT(pInstance != NULL_PTR);
943 
944  STD_RETURN_TYPE_e retval = STD_OK;
945 
946  /* Perform RSTB path check (repeat steps 1 to 4 after RSTB is released) */
947  if (STD_OK != SBC_PerformPathCheckRstb(pInstance)) {
948  retval = STD_NOT_OK;
949  }
950 
951  /* FS0B pin can not be released in debug mode */
952  if (pInstance->mode != SBC_DEBUG_MODE) {
953  /* Release FS0B pin */
954  if (fs8xStatusOk != FS8x_FS0B_Release(pInstance->pSpiInterface, &(pInstance->configValues))) {
955  retval = STD_NOT_OK;
956  }
957  }
958 
959  /* Perform FS0B safety path check */
960  if (STD_OK != SBC_PerformPathCheckFs0b(pInstance)) {
961  retval = STD_NOT_OK;
962  }
963 
964  /* Init finished successfully if retval still okay */
965  if (retval == STD_OK) {
966  pInstance->nvram.data->phase = (uint8_t)SBC_INITIALIZED;
967  FRAM_WriteData(pInstance->nvram.entry);
968  }
969  return retval;
970 }
971 
972 /* AXIVION Next Line Style CodingStyle-Naming: The function name is pre-defined by the driver provided by NXP */
974  SPI_INTERFACE_CONFIG_s *pSpiInterface,
975  uint8_t *txFrame,
976  uint16_t frameLengthBytes,
977  uint8_t *rxFrame) {
978  FAS_ASSERT(pSpiInterface != NULL_PTR);
979  FAS_ASSERT(txFrame != NULL_PTR);
980  FAS_ASSERT(rxFrame != NULL_PTR);
981  /* AXIVION Routine Generic-MissingParameterAssert: frameLengthBytes: parameter accepts whole range */
982 
983  uint16_t sbc_txBuffer[FS8x_COMM_FRAME_SIZE];
984  uint16_t sbc_rxBuffer[FS8x_COMM_FRAME_SIZE];
985  fs8x_status_t spiCommunicationState = fs8xStatusError;
986 
987  /* Copy TX data in TX array, reset RX array */
988  for (uint8_t i = 0u; i < FS8x_COMM_FRAME_SIZE; i++) {
989  sbc_txBuffer[FS8x_COMM_FRAME_SIZE - 1u - i] = (uint16_t)txFrame[i]; /* txFrame[0] will be sent last */
990  sbc_rxBuffer[i] = 0;
991  }
992 
993  STD_RETURN_TYPE_e spiRetval =
994  SPI_TransmitReceiveData(pSpiInterface, sbc_txBuffer, sbc_rxBuffer, FS8x_COMM_FRAME_SIZE);
995 
996  if (spiRetval == STD_OK) {
997  /* No error flag set - copy RX data in RX array */
998  for (uint8_t i = 0u; i < FS8x_COMM_FRAME_SIZE; i++) {
999  rxFrame[i] = (uint8_t)sbc_rxBuffer[FS8x_COMM_FRAME_SIZE - 1u - i];
1000  }
1001  spiCommunicationState = fs8xStatusOk;
1002  }
1003 
1004  return spiCommunicationState;
1005 }
1006 
1008  FAS_ASSERT(pInstance != NULL_PTR);
1009 
1010  STD_RETURN_TYPE_e retval = STD_NOT_OK;
1011  if (fs8xStatusOk == FS8x_WD_Refresh(pInstance->pSpiInterface, &(pInstance->configValues))) {
1012  /* Check GRL_FLAGS register if watchdog refresh was valid */
1013  if (STD_OK == SBC_ReadBackRegister(pInstance, true, FS8X_FS_GRL_FLAGS_ADDR)) {
1014  uint16_t registerMask = FS8X_FS_FS_WD_G_MASK;
1015  uint16_t expRegisterValue = FS8X_FS_FS_WD_G_GOOD_WD_REFRESH;
1016  if (STD_OK == SBC_CheckRegisterValues((pInstance->fsRegister.grl_flags & registerMask), expRegisterValue)) {
1017  /* GOOD watchdog refresh */
1018  retval = STD_OK;
1019  } else {
1020  /* BAD watchdog refresh: get reason */
1021  if (STD_OK == SBC_ReadBackRegister(pInstance, true, FS8X_FS_DIAG_SAFETY_ADDR)) {
1022  registerMask = FS8X_FS_BAD_WD_TIMING_MASK;
1023  expRegisterValue = FS8X_FS_BAD_WD_TIMING_BAD_WD_REFRESH;
1024  if (STD_OK ==
1025  SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
1026  /* TODO: Notify someone: bad watchdog refresh was caused by wrong window or in timeout */
1027  }
1028  registerMask = FS8X_FS_BAD_WD_DATA_MASK;
1029  expRegisterValue = FS8X_FS_BAD_WD_DATA_BAD_WD_REFRESH;
1030  if (STD_OK ==
1031  SBC_CheckRegisterValues((pInstance->fsRegister.diag_safety & registerMask), expRegisterValue)) {
1032  /* TODO: Notify someone: bad watchdog refresh was caused by error in data */
1033  }
1034  }
1035  }
1036  }
1037  }
1038  return retval;
1039 }
1040 
1042  FAS_ASSERT(pInstance != NULL_PTR);
1043 
1044  STD_RETURN_TYPE_e retval = STD_OK;
1045 
1046  /* Read all fail-safe registers */
1047  SBC_ReadBackRegister(pInstance, true, FS8X_FS_GRL_FLAGS_ADDR);
1050  SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_WD_CFG_ADDR);
1052  SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_FSSM_ADDR);
1053  SBC_ReadBackRegister(pInstance, true, FS8X_FS_I_SVS_ADDR);
1054  SBC_ReadBackRegister(pInstance, true, FS8X_FS_WD_WINDOW_ADDR);
1055  SBC_ReadBackRegister(pInstance, true, FS8X_FS_WD_SEED_ADDR);
1056  SBC_ReadBackRegister(pInstance, true, FS8X_FS_WD_ANSWER_ADDR);
1059  SBC_ReadBackRegister(pInstance, true, FS8X_FS_SAFE_IOS_ADDR);
1061  SBC_ReadBackRegister(pInstance, true, FS8X_FS_INTB_MASK_ADDR);
1062  SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR);
1063 
1064  /* Read main registers */
1065  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_FLAG_ADDR);
1066  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_MODE_ADDR);
1067  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_REG_CTRL1_ADDR);
1068  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_REG_CTRL2_ADDR);
1069  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_AMUX_ADDR);
1070  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_CLOCK_ADDR);
1071  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_INT_MASK1_ADDR);
1072  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_INT_MASK2_ADDR);
1073  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_FLAG1_ADDR);
1074  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_FLAG2_ADDR);
1075  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_VMON_REGX_ADDR);
1076  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_LVB1_SVS_ADDR);
1077  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_MEMORY0_ADDR);
1078  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_MEMORY1_ADDR);
1079  SBC_ReadBackRegister(pInstance, FALSE, FS8X_M_DEVICEID_ADDR);
1080  return retval;
1081 }
1082 
1084  FAS_ASSERT(pInstance != NULL_PTR);
1085 
1086  STD_RETURN_TYPE_e retval = STD_OK;
1087  resetSource_t rstReason = MINFO_GetResetSource();
1088  bool test_assertionRSTB = false; /* Do not test RSTB assertion on default */
1089 
1090  /** Assertion of RSTB pin will trigger reset, check if reset reason was power-cycle.
1091  If so, check if short circuit between FIN and RSTB pin exists */
1092  if (rstReason == POWERON_RESET) {
1093  /** First check if FIN is used */
1094  if (pInstance->fin.finUsed == true) {
1095  /** Write to NVRAM to determine after reset and if short-circuit
1096  * between RSTB and FIN present what exactly caused the reset. */
1097  pInstance->nvram.data->phase = (uint8_t)SBC_FIN_TEST;
1098  FRAM_WriteData(pInstance->nvram.entry);
1099 
1100  /** MCU SBC is connected to ECLK1 -> privilege mode is required to access register */
1102 
1103  /** Last reset was caused by power-cycle */
1104  /** Set level of FIN pin low and check if this generates reset */
1105  IO_PinReset(pInstance->fin.pGIOport, pInstance->fin.pin);
1106 
1107  /** Pulses longer than 2000ns trigger reset -> wait 10us to check if
1108  reset is triggered by short between RSTB and FIN */
1109  MCU_Delay_us(10u);
1110 
1111  /** If we reach this line of code, no reset has taken place.
1112  Everything okay. Set level of FIN pin back to high */
1113  IO_PinSet(pInstance->fin.pGIOport, pInstance->fin.pin);
1114 
1115  /** No further register access required -> leave privilege mode */
1117 
1118  /** FIN state okay, no short circuit. Update also in nvram struct */
1120  pInstance->fin.finState = STD_OK;
1121  pInstance->nvram.data->finState = STD_OK;
1122 
1123  /** Continue with RSTB assertion test */
1124  test_assertionRSTB = true;
1125  } else {
1126  /** Power-cycle but no FIN pin used -> continue with RSTB check */
1127  test_assertionRSTB = true;
1128  }
1129  } else if (rstReason == EXT_RESET) {
1130  /** Last reset reason was external reset via nRST pin (EXT_RESET)
1131  Readout FRAM to determine in which state the SBC was prior to reset */
1132  FRAM_ReadData(pInstance->nvram.entry);
1133  if ((SBC_INIT_PHASE_e)pInstance->nvram.data->phase == SBC_FIN_TEST) {
1134  /** Short-circuit between FIN and RSTB: Do not apply CLK on FIN */
1135  /** Update nvram FIN state */
1136  pInstance->nvram.data->finState = STD_NOT_OK;
1137  /** FIN state not okay, but still in SBC init phase after power-cycle
1138  * continue now with RSTB assertion */
1139  test_assertionRSTB = true;
1140  } else if ((SBC_INIT_PHASE_e)pInstance->nvram.data->phase == SBC_RSTB_ASSERTION_TEST) {
1141  /** Reset was triggered by SPI RSTB assertion test -> continue with SBC init phase */
1142  test_assertionRSTB = false;
1143 
1144  /** Diagnosis of the RSTB pin/event is available by reading the FS_SAFE_IOs register:
1145  * RSTB_EVENT bit reports an activation of RSTB pin. */
1146  SBC_ReadBackRegister(pInstance, true, FS8X_FS_SAFE_IOS_ADDR);
1147 
1148  /** Check RSTB_EVENT if RSTB has been activated */
1149  if (STD_OK ==
1152  /** RSTB pin should be sensed high and no RSTB short to high */
1154  uint16_t expRegisterValue =
1157  if (STD_OK != SBC_CheckRegisterValues((pInstance->fsRegister.safeIos & mask), expRegisterValue)) {
1158  retval = STD_NOT_OK;
1159  }
1160  /** Reset RSTB_EVENT flag */
1162  /** Update diag flag */
1164  } else {
1165  /** RSTB has not been activated but this should have been the case */
1166  retval = STD_NOT_OK;
1168  }
1169  } else {
1170  /** Reset was not caused by SBC initialization or power-cycle.
1171  * Continue with SBC init phase as RSTB assertion is only tested
1172  * after power-cycle occurred */
1173  test_assertionRSTB = false;
1174  }
1175  /** Copy FIN state info from nvram variable into local state variable. This restores lost data from rest or
1176  updates local FIN state if short-circuit between FIN and RSTB has been detected */
1177  pInstance->fin.finState = pInstance->nvram.data->finState;
1178  if (pInstance->fin.finState == STD_OK) {
1180  } else {
1182  }
1183  } else {
1184  /** Reset was not caused by power-cycle or SBC. SBC has already been initialized successfully after detected
1185  * power-cycle. Everything okay. Read FIN state from NVRAM and continue with normal operation */
1186  FRAM_ReadData(pInstance->nvram.entry);
1187  test_assertionRSTB = false;
1188  pInstance->fin.finState = pInstance->nvram.data->finState;
1189  if (pInstance->fin.finState == STD_OK) {
1191  } else {
1193  }
1194  }
1195 
1196  /** Verify the hardware connection between the MCU reset pin and the FS85 reset pin */
1197  if (test_assertionRSTB == true) {
1198  /** Write to NVRAM to determine after reset and if RSTB was asserted correctly */
1199  pInstance->nvram.data->phase = (uint8_t)SBC_RSTB_ASSERTION_TEST;
1200  FRAM_WriteData(pInstance->nvram.entry);
1201 
1202  SBC_ReadBackRegister(pInstance, true, FS8X_FS_STATES_ADDR);
1203 
1204  uint16_t registerValue = FS8X_FS_RSTB_REQ_RSTB_ASSERTION;
1205  SBC_WriteRegisterFsInit(pInstance, FS8X_FS_SAFE_IOS_ADDR, registerValue);
1206 
1207  while (true) {
1208  ;
1209  }
1210 
1211  /* Controller should never reach this point as reset via RSTB is requested */
1212  }
1213  return retval;
1214 }
1215 
1217  FAS_ASSERT(pInstance != NULL_PTR);
1218 
1219  STD_RETURN_TYPE_e retval = STD_OK;
1220  /* TBD */
1221  return retval;
1222 }
1223 
1224 /*========== Externalized Static Function Implementations (Unit Test) =======*/
DIAG_RETURNTYPE_e DIAG_Handler(DIAG_ID_e diag_id, DIAG_EVENT_e event, DIAG_IMPACT_LEVEL_e impact, uint32_t data)
DIAG_Handler provides generic error handling, based on diagnosis group.
Definition: diag.c:229
Diagnosis driver header.
@ DIAG_EVENT_NOT_OK
Definition: diag_cfg.h:239
@ DIAG_EVENT_OK
Definition: diag_cfg.h:238
@ DIAG_SYSTEM
Definition: diag_cfg.h:251
@ DIAG_ID_SBC_RSTB_STATE
Definition: diag_cfg.h:216
@ DIAG_ID_SBC_FIN_STATE
Definition: diag_cfg.h:215
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:241
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:115
FRAM_RETURN_TYPE_e FRAM_ReadData(FRAM_BLOCK_ID_e blockId)
Reads a variable from the FRAM.
Definition: fram.c:193
FRAM_RETURN_TYPE_e FRAM_WriteData(FRAM_BLOCK_ID_e blockId)
Writes a variable to the FRAM.
Definition: fram.c:115
Header for the driver for the FRAM module.
FRAM_SBC_INIT_s fram_sbcInit
Definition: fram_cfg.c:73
@ FRAM_BLOCK_ID_SBC_INIT_STATE
Definition: fram_cfg.h:103
STD_RETURN_TYPE_e
Definition: fstd_types.h:81
@ STD_NOT_OK
Definition: fstd_types.h:83
@ STD_OK
Definition: fstd_types.h:82
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:76
Function to switch between user mode and privilege mode.
#define FSYS_SwitchToUserMode()
Switch back to user mode.
Definition: fsystem.h:114
long FSYS_RaisePrivilege(void)
raise privilege
#define UNIT_TEST_WEAK_IMPL
Definition: general.h:97
fs8x_status_t FS8x_GetFaultErrorCounterValue(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData, uint8_t *faultErrorCounterValue)
Reads actual Fault Error Counter value.
Definition: sbc_fs8x.c:270
fs8x_status_t FS8x_WD_Refresh(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData)
Performs the watchdog refresh.
Definition: sbc_fs8x.c:160
fs8x_status_t FS8x_WriteRegisterInit(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, uint8_t address, uint16_t writeData)
Performs a write to a single FS8x FS init register (during the INIT_FS phase only).
fs8x_status_t FS8x_WriteRegister(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, bool isFailSafe, uint8_t address, uint16_t writeData)
Sends write command to the FS8x.
fs8x_status_t FS8x_FS0B_Release(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData)
FS0B release routine.
Definition: sbc_fs8x.c:184
fs8x_status_t FS8x_ReadRegister(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, bool isFailSafe, uint8_t address, fs8x_rx_frame_t *rxData)
Performs a read from a single FS8x register.
fs8x_status_t
Status return codes.
@ fs8xSPI
@ fs8xStatusOk
@ fs8xStatusError
UNIT_TEST_WEAK_IMPL fs8x_status_t MCU_SPI_TransferData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint8_t *txFrame, uint16_t frameLengthBytes, uint8_t *rxFrame)
This function transfers single frame through blocking SPI communication in both directions....
Definition: nxpfs85xx.c:973
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:87
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:94
Header for the driver for the IO module.
resetSource_t MINFO_GetResetSource(void)
Get reason for last reset.
Definition: masterinfo.c:84
void MINFO_SetDebugProbeConnectionState(MINFO_DEBUG_PROBE_CONNECTION_STATE_e state)
Check if debug probe is connected.
Definition: masterinfo.c:88
General foxBMS-master system information.
@ MINFO_DEBUG_PROBE_CONNECTED
Definition: masterinfo.h:68
@ MINFO_DEBUG_PROBE_NOT_CONNECTED
Definition: masterinfo.h:67
void MCU_Delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:86
Headers for the driver for the MCU module.
static void SBC_UpdateRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint32_t registerAddress, uint32_t registerValue)
Updates register values.
Definition: nxpfs85xx.c:216
STD_RETURN_TYPE_e FS85_InitializeNumberOfRequiredWatchdogRefreshes(FS85_STATE_s *pInstance, uint8_t *requiredWatchdogRefreshes)
Calculates the number of required watchdog refresh to reset fault error counter.
Definition: nxpfs85xx.c:869
static STD_RETURN_TYPE_e SBC_ReadBackRegister(FS85_STATE_s *pInstance, bool isFailSafe, uint8_t registerAddress)
Reads SBC register value.
Definition: nxpfs85xx.c:368
static STD_RETURN_TYPE_e SBC_CheckRegisterValues(uint32_t registerValue, uint32_t expectedRegisterValue)
Checks register value against expected value.
Definition: nxpfs85xx.c:206
FS85_STATE_s fs85xx_mcuSupervisor
Definition: nxpfs85xx.c:81
STD_RETURN_TYPE_e FS85_InitializeFsPhase(FS85_STATE_s *pInstance)
Configures SBC during INIT_FS phase.
Definition: nxpfs85xx.c:484
static STD_RETURN_TYPE_e SBC_PerformPathCheckRstb(FS85_STATE_s *pInstance)
Perform RSTB safety path check.
Definition: nxpfs85xx.c:1083
static STD_RETURN_TYPE_e SBC_PerformPathCheckFs0b(FS85_STATE_s *pInstance)
Perform FS0B safety path check.
Definition: nxpfs85xx.c:1216
STD_RETURN_TYPE_e SBC_TriggerWatchdog(FS85_STATE_s *pInstance)
Trigger watchdog.
Definition: nxpfs85xx.c:1007
static STD_RETURN_TYPE_e SBC_WriteRegisterFsInit(FS85_STATE_s *pInstance, uint8_t registerAddress, uint16_t registerValue)
Write to fail-safe register.
Definition: nxpfs85xx.c:388
static STD_RETURN_TYPE_e SBC_ClearRegisterFlags(FS85_STATE_s *pInstance, uint8_t registerAddress, bool isFailSafe, uint16_t registerValue)
Clears flags in register.
Definition: nxpfs85xx.c:444
static STD_RETURN_TYPE_e SBC_ReadBackAllRegisters(FS85_STATE_s *pInstance)
Definition: nxpfs85xx.c:1041
STD_RETURN_TYPE_e FS85_SafetyPathChecks(FS85_STATE_s *pInstance)
Performs SBC safety path checks.
Definition: nxpfs85xx.c:941
SBC_INIT_PHASE_e
Definition: nxpfs85xx.c:73
@ SBC_UNINITIALIZED
Definition: nxpfs85xx.c:74
@ SBC_FIN_TEST
Definition: nxpfs85xx.c:75
@ SBC_INITIALIZED
Definition: nxpfs85xx.c:77
@ SBC_RSTB_ASSERTION_TEST
Definition: nxpfs85xx.c:76
static STD_RETURN_TYPE_e SBC_WriteBackRegisterFsInit(FS85_STATE_s *pInstance, uint8_t registerAddress, uint16_t registerValue)
Write to fail-safe register.
Definition: nxpfs85xx.c:410
STD_RETURN_TYPE_e FS85_CheckFaultErrorCounter(FS85_STATE_s *pInstance)
Checks if fault error counter is zero.
Definition: nxpfs85xx.c:926
Header for the driver for the FRAM module.
@ SBC_DEBUG_MODE
Definition: nxpfs85xx.h:112
@ SBC_NORMAL_MODE
Definition: nxpfs85xx.h:111
#define FS8x_WD_SEED_DEFAULT
Watchdog seed default value.
Definition: sbc_fs8x.h:59
#define FS8x_BO_GET_REG_VALUE(value, mask, shift)
Macro for getting value from register.
#define FS8x_COMM_FRAME_SIZE
#define FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB
#define FS8X_FS_VDDIO_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_I_WD_RFR_CNT_MASK
#define FS8X_FS_BAD_WD_TIMING_MASK
#define FS8X_FS_VMON2_OV_OVERVOLTAGE_REPORTED
#define FS8X_M_VBOOSTUVH_EVENT_OCCURRED
#define FS8X_FS_I_ERRMON_FS_IMPACT_FS0B
#define FS8X_FS_VCOREMON_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_FCCU1_ERROR_DETECTED
#define FS8X_FS_RSTB_DIAG_MASK
#define FS8X_FS_I_FCCU_CFG_NO_MONITORING
#define FS8X_FS_RSTB_REQ_RSTB_ASSERTION
#define FS8X_M_WK2FLG_EVENT_OCCURRED
#define FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE
#define FS8X_M_INT_MASK2_ADDR
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I_ERRMON_ACK_TIME_32MS
#define FS8X_FS_WDW_DC_50
#define FS8X_FS_FSM_STATE_INIT_FS
#define FS8X_FS_I_FCCU1_FLT_POL_FCCU1_L
#define FS8X_FS_ABIST1_OK_PASS
#define FS8X_FS_I_VMON2_ABIST2_VMON2_BIST
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_DBG_MODE_MASK
#define FS8X_M_MEMORY1_ADDR
#define FS8X_FS_ABIST2_OK_MASK
#define FS8X_FS_I_VMON3_ABIST2_VMON3_BIST
#define FS8X_FS_RSTB_EVENT_MASK
#define FS8X_FS_SPI_FS_CRC_ERROR_DETECTED
#define FS8X_FS_I_WD_RFR_LIMIT_2
#define FS8X_FS_SPI_FS_CLK_WRONG_NUMBER_OF_CLOCK_CYCLES
#define FS8X_FS_LBIST_OK_MASK
#define FS8X_FS_BAD_WD_DATA_BAD_WD_REFRESH
#define FS8X_FS_I2C_FS_CRC_ERROR_DETECTED
#define FS8X_FS_WD_ANSWER_ADDR
#define FS8X_FS_VMON3_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_FSM_STATE_MASK
#define FS8X_M_REG_CTRL2_ADDR
Definition: sbc_fs8x_map.h:696
#define FS8X_M_VBOSUVH_EVENT_OCCURRED
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_RSTB_DIAG_NO_FAILURE
#define FS8X_FS_RSTB_EVENT_RESET_OCCURRED
#define FS8X_FS_RELEASE_FS0B_ADDR
#define FS8X_FS_WD_WINDOW_ADDR
#define FS8X_FS_VCOREMON_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT
#define FS8X_M_DEVICEID_ADDR
#define FS8X_M_FLAG1_ADDR
#define FS8X_FS_BAD_WD_TIMING_BAD_WD_REFRESH
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I2C_FS_REQ_I2C_VIOLATION
#define FS8X_M_VMON_REGX_ADDR
#define FS8X_FS_I_RSTB_DUR_10MS
#define FS8X_FS_I_WD_RFR_LIMIT_SHIFT
#define FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST
#define FS8X_M_VSUPUVL_EVENT_OCCURRED
#define FS8X_FS_I_VMON4_ABIST2_VMON4_BIST
#define FS8X_FS_ERRMON_ERROR_DETECTED
#define FS8X_M_REG_CTRL1_ADDR
Definition: sbc_fs8x_map.h:432
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_RSTB_SNS_PAD_SENSED_HIGH
#define FS8X_FS_VMON4_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I_FLT_ERR_CNT_1
#define FS8X_M_FLAG_ADDR
Definition: sbc_fs8x_map.h:57
#define FS8X_FS_WD_SEED_ADDR
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_I_WD_RFR_LIMIT_6
#define FS8X_M_MODE_ADDR
Definition: sbc_fs8x_map.h:304
#define FS8X_FS_VMON4_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_RSTB_DRV_COMMAND_SENSED_HIGH
#define FS8X_FS_I_WD_RFR_LIMIT_MASK
#define FS8X_FS_DBG_MODE_NO_DEBUG
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_OTP_CORRUPT_MASK
#define FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION
#define FS8X_FS_I_VMON1_ABIST2_VMON1_BIST
#define FS8X_FS_WD_WINDOW_128MS
#define FS8X_FS_I_SAFE_INPUTS_ADDR
#define FS8X_FS_INTB_MASK_ADDR
#define FS8X_FS_SAFE_IOS_ADDR
#define FS8X_M_CLOCK_ADDR
#define FS8X_FS_I_OVUV_SAFE_REACTION1_ADDR
#define FS8X_M_VSUPUVH_EVENT_OCCURRED
#define FS8X_FS_OVUVREG_STATUS_ADDR
#define FS8X_FS_I_FSSM_ADDR
#define FS8X_FS_FS_OSC_DRIFT_OSCILLATOR_DRIFT
#define FS8X_FS_I_WD_CFG_ADDR
#define FS8X_FS_VMON2_UV_UNDERVOLTAGE_REPORTED
#define FS8X_FS_FS_DIG_REF_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_FS_WD_G_MASK
#define FS8X_FS_DIAG_SAFETY_ADDR
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_FCCU12_ERROR_DETECTED
#define FS8X_FS_VMON1_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_RSTB_DRV_MASK
#define FS8X_M_VPREUVH_EVENT_OCCURRED
#define FS8X_FS_VMON1_UV_UNDERVOLTAGE_REPORTED
#define FS8X_M_VSUPUV7_EVENT_OCCURRED
#define FS8X_M_INT_MASK1_ADDR
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_NO_EFFECT
#define FS8X_FS_VMON3_OV_OVERVOLTAGE_REPORTED
#define FS8X_FS_WDW_RECOVERY_128MS
#define FS8X_FS_RSTB_SNS_MASK
#define FS8X_FS_I_SVS_ADDR
#define FS8X_FS_VDDIO_OV_OVERVOLTAGE_REPORTED
#define FS8X_M_LVB1_SVS_ADDR
#define FS8X_FS_I_FCCU1_FS_REACT_FS0B
#define FS8X_FS_SPI_FS_REQ_SPI_VIOLATION
#define FS8X_M_FLAG2_ADDR
#define FS8X_FS_I_WD_RFR_CNT_SHIFT
#define FS8X_FS_FS_WD_G_GOOD_WD_REFRESH
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_8
#define FS8X_FS_GO_TO_INITFS_GO_BACK_TO_INIT_FS
#define FS8X_FS_I_OVUV_SAFE_REACTION2_ADDR
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_NO_EFFECT
#define FS8X_M_VPREUVL_EVENT_OCCURRED
#define FS8X_FS_OTP_CORRUPT_NO_ERROR
#define FS8X_FS_ABIST1_OK_MASK
#define FS8X_FS_LBIST_OK_PASS
#define FS8X_FS_BAD_WD_DATA_MASK
#define FS8X_FS_I_WD_RFR_LIMIT_4
#define FS8X_M_AMUX_ADDR
Definition: sbc_fs8x_map.h:882
#define FS8X_FS_STATES_ADDR
#define FS8X_M_MEMORY0_ADDR
#define FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST
#define FS8X_FS_GRL_FLAGS_ADDR
#define FS8X_FS_FCCU2_ERROR_DETECTED
STD_RETURN_TYPE_e SPI_TransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:145
SPI_INTERFACE_CONFIG_s spi_kSbcMcuInterface
Definition: spi_cfg.c:253
uint8_t phase
Definition: fram_cfg.h:125
STD_RETURN_TYPE_e finState
Definition: fram_cfg.h:126
volatile uint32_t * pGIOport
Definition: nxpfs85xx.h:119
STD_RETURN_TYPE_e finState
Definition: nxpfs85xx.h:118
uint16_t diag_safety
Definition: nxpfs85xx.h:85
uint16_t releaseFs0bPin
Definition: nxpfs85xx.h:83
uint16_t i_svs
Definition: nxpfs85xx.h:78
uint16_t iWatchdogConfiguration
Definition: nxpfs85xx.h:75
uint16_t watchdogAnswer
Definition: nxpfs85xx.h:81
uint16_t overvoltageUndervoltageRegisterStatus
Definition: nxpfs85xx.h:82
uint16_t i_safe_inputs
Definition: nxpfs85xx.h:76
uint16_t safeIos
Definition: nxpfs85xx.h:84
uint16_t watchdogSeed
Definition: nxpfs85xx.h:80
uint16_t iFailSafeSateMachine
Definition: nxpfs85xx.h:77
uint16_t iOvervoltageUndervolateSafeReaction1
Definition: nxpfs85xx.h:73
uint16_t grl_flags
Definition: nxpfs85xx.h:72
uint16_t iOvervoltageUndervolateSafeReaction2
Definition: nxpfs85xx.h:74
uint16_t watchdogWindow
Definition: nxpfs85xx.h:79
uint16_t states
Definition: nxpfs85xx.h:87
uint16_t intb_mask
Definition: nxpfs85xx.h:86
uint16_t registerControl1
Definition: nxpfs85xx.h:95
uint16_t registerControl2
Definition: nxpfs85xx.h:96
uint16_t analogMultiplexer
Definition: nxpfs85xx.h:97
FRAM_BLOCK_ID_e entry
Definition: nxpfs85xx.h:125
FRAM_SBC_INIT_s * data
Definition: nxpfs85xx.h:126
FS85_MAIN_REGISTERS_s mainRegister
Definition: nxpfs85xx.h:134
FS85_OPERATION_MODE_e mode
Definition: nxpfs85xx.h:137
FS85_FS_REGISTER_s fsRegister
Definition: nxpfs85xx.h:135
FS85_NVRAM_INFO_s nvram
Definition: nxpfs85xx.h:136
FS85_FIN_CONFIGURATION_s fin
Definition: nxpfs85xx.h:133
fs8x_drv_data_t configValues
Definition: nxpfs85xx.h:132
SPI_INTERFACE_CONFIG_s * pSpiInterface
Definition: nxpfs85xx.h:131
Structure representing received data frame.
uint16_t readData
Content of a read register.