foxBMS - Unit Tests  1.4.1
The foxBMS Unit Tests API Documentation
spi.c
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41 
42 /**
43  * @file spi.c
44  * @author foxBMS Team
45  * @date 2019-12-12 (date of creation)
46  * @updated 2022-10-27 (date of last update)
47  * @version v1.4.1
48  * @ingroup DRIVERS
49  * @prefix SPI
50  *
51  * @brief Driver for the SPI module.
52  *
53  */
54 
55 /*========== Includes =======================================================*/
56 #include "spi.h"
57 
58 #include "HL_reg_spi.h"
59 #include "HL_spi.h"
60 #include "HL_sys_common.h"
61 
62 #include "dma.h"
63 #include "fsystem.h"
64 #include "io.h"
65 #include "os.h"
66 
68 
69 /*========== Macros and Definitions =========================================*/
70 /** Bitfield to check for transmission errors in SPI FLAG register */
71 #define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS (0x5Fu)
72 
73 /*========== Static Constant and Variable Definitions =======================*/
74 
75 /*========== Extern Constant and Variable Definitions =======================*/
76 
77 bool spi_txFinished = false;
78 bool spi_rxFinished = false;
79 
80 /*========== Static Function Prototypes =====================================*/
81 
82 /*========== Static Function Implementations ================================*/
83 
84 /*========== Extern Function Implementations ================================*/
85 
86 extern STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay) {
87  FAS_ASSERT(pSpiInterface != NULL_PTR);
88  /* AXIVION Routine Generic-MissingParameterAssert: delay: parameter accepts whole range */
89 
90  uint16_t txDummy[1] = {0x00};
91  STD_RETURN_TYPE_e retVal = SPI_TransmitData(pSpiInterface, txDummy, 1u);
92  MCU_Delay_us(delay);
93  return retVal;
94 }
95 
96 extern STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint32 frameLength) {
97  FAS_ASSERT(pSpiInterface != NULL_PTR);
98  FAS_ASSERT(pTxBuff != NULL_PTR);
99  FAS_ASSERT(frameLength > 0u);
100  STD_RETURN_TYPE_e retval = STD_NOT_OK;
101 
102  /* Lock SPI hardware to prevent concurrent read/write commands */
103  if (STD_OK == SPI_Lock(SPI_GetSpiIndex(pSpiInterface->pNode))) {
104  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
105 
106  /** SW Chip Select */
107  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
108  /** Set SPI Chip Select pins as GIOs */
109  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
110  /** Activate Chip Select */
111  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
112  }
113  /** HW Chip Select */
114  if (pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE) {
115  /**
116  * Activate HW Chip Select according to bitmask register CSNR
117  * by setting pins as SPI functional pins
118  */
119  /** First deactivate all HW Chip Selects */
120  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
121  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
122  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
123  /** Bitmask = 0 --> HW CS active
124  * --> write to PC0 to set pin as SPI pin (and not GIO)
125  */
126  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
127  }
128  }
129  }
130  uint32_t spiRetval = spiTransmitData(pSpiInterface->pNode, pSpiInterface->pConfig, frameLength, pTxBuff);
131  /** SW Chip Select */
132  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
133  /** Deactivate Chip Select */
134  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
135  }
136 
137  /* Unlock SPI hardware */
138  SPI_Unlock(SPI_GetSpiIndex(pSpiInterface->pNode));
139 
140  /* Transmission successful */
141  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
142  retval = STD_OK;
143  }
144  }
145  return retval;
146 }
147 
149  SPI_INTERFACE_CONFIG_s *pSpiInterface,
150  uint16 *pTxBuff,
151  uint16 *pRxBuff,
152  uint32 frameLength) {
153  FAS_ASSERT(pSpiInterface != NULL_PTR);
154  FAS_ASSERT(pTxBuff != NULL_PTR);
155  FAS_ASSERT(pRxBuff != NULL_PTR);
156  FAS_ASSERT(frameLength > 0u);
157  STD_RETURN_TYPE_e retval = STD_NOT_OK;
158 
159  /* Lock SPI hardware to prevent concurrent read/write commands */
160  if (STD_OK == SPI_Lock(SPI_GetSpiIndex(pSpiInterface->pNode))) {
161  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
162 
163  /** SW Chip Select */
164  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
165  /** Set SPI Chip Select pins as GIOs */
166  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
167  /** Activate Chip Select */
168  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
169  }
170  /** HW Chip Select */
171  if (pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE) {
172  /**
173  * Activate HW Chip Select according to bitmask register CSNR
174  * by setting pins as SPI functional pins
175  */
176  /** First deactivate all HW Chip Selects */
177  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
178  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
179  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
180  /** Bitmask = 0 --> HW CS active
181  * --> write to PC0 to set pin as SPI pin (and not GIO)
182  */
183  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
184  }
185  }
186  }
187  uint32_t spiRetval =
188  spiTransmitAndReceiveData(pSpiInterface->pNode, pSpiInterface->pConfig, frameLength, pTxBuff, pRxBuff);
189  /** SW Chip Select */
190  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
191  /** Deactivate Chip Select */
192  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
193  }
194 
195  /* Unlock SPI hardware */
196  SPI_Unlock(SPI_GetSpiIndex(pSpiInterface->pNode));
197 
198  /* Transmission successful */
199  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
200  retval = STD_OK;
201  }
202  }
203  return retval;
204 }
205 
207  SPI_INTERFACE_CONFIG_s *pSpiInterface,
208  uint16 *pTxBuff,
209  uint16 *pRxBuff,
210  uint32 frameLength) {
211  FAS_ASSERT(pSpiInterface != NULL_PTR);
212  FAS_ASSERT(pTxBuff != NULL_PTR);
213  FAS_ASSERT(pRxBuff != NULL_PTR);
214  FAS_ASSERT(frameLength > 0u);
215 
216  (void)spiTransmitAndReceiveData(pSpiInterface->pNode, pSpiInterface->pConfig, frameLength, pTxBuff, pRxBuff);
217 }
218 
220  SPI_INTERFACE_CONFIG_s *pSpiInterface,
221  uint16_t *pTxBuff,
222  uint16_t *pRxBuff,
223  uint32_t frameLength) {
224  FAS_ASSERT(frameLength > 2u);
225  FAS_ASSERT(pSpiInterface != NULL_PTR);
226  FAS_ASSERT(pTxBuff != NULL_PTR);
227  FAS_ASSERT(pRxBuff != NULL_PTR);
228  /** SPI over DMA currently only compatible with HW Chip Select */
229  FAS_ASSERT(pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE);
230  const uint8_t spiIndex = SPI_GetSpiIndex(pSpiInterface->pNode);
231  FAS_ASSERT(spiIndex < spi_nrBusyFlags);
232 
233  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
234 
236  /* Lock SPI hardware to prevent concurrent read/write commands */
237  if (spi_busyFlags[spiIndex] == SPI_IDLE) {
238  spi_busyFlags[spiIndex] = SPI_BUSY;
239 
240  /* Check that not SPI transmission over DMA is taking place */
241  if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
242  /**
243  * Activate HW Chip Select according to bitmask register CSNR
244  * by setting pins as SPI functional pins
245  */
246  /** First deactivate all HW Chip Selects */
247  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
248  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
249  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
250  /** Bitmask = 0 --> HW CS active
251  * --> write to PC0 to set pin as SPI pin (and not GIO)
252  */
253  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
254  }
255  }
256 
257  /* The upper 16 bits will be written in the SPI DAT1 register where they serve as configuration */
258  uint32 Chip_Select_Hold = 0u;
259  if (pSpiInterface->pConfig->CS_HOLD == TRUE) {
260  Chip_Select_Hold = SPI_CSHOLD_BIT;
261  } else {
262  Chip_Select_Hold = 0U;
263  }
264  uint32 WDelay = 0u;
265  if (pSpiInterface->pConfig->WDEL == TRUE) {
266  WDelay = SPI_WDEL_BIT;
267  } else {
268  WDelay = 0U;
269  }
270  SPIDATAFMT_t DataFormat = pSpiInterface->pConfig->DFSEL;
271  uint8 ChipSelect = pSpiInterface->pConfig->CSNR;
272 
273  /* Go to privilege mode to write DMA config registers */
274  (void)FSYS_RaisePrivilege();
275 
276  spi_txLastWord[spiIndex] = pTxBuff[frameLength - 1u];
277  spi_txLastWord[spiIndex] |= ((uint32)DataFormat << SPI_DATA_FORMAT_FIELD_POSITION) |
278  ((uint32)ChipSelect << SPI_HARDWARE_CHIP_SELECT_FIELD_POSITION) | (WDelay);
279 
280  /* Set Tx buffer address */
281  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[spiIndex].txChannel].ISADDR =
282  (uint32_t)(&pTxBuff[1u]); /* First word sent manually to write configuration in SPIDAT1 register */
283  /**
284  * Set number of Tx words to send
285  * Last word sent in ISR to set CSHOLD = 0
286  */
287  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[spiIndex].txChannel].ITCOUNT =
288  ((frameLength - 2u) << 16U) | 1U; /* Last word sent manually to write CSHOLD in SPIDAT1 register */
289 
290  /* Set Rx buffer address */
291  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[spiIndex].rxChannel].IDADDR = (uint32_t)pRxBuff;
292  /* Set number of Rx words to receive */
293  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[spiIndex].rxChannel].ITCOUNT = (frameLength << 16U) | 1U;
294 
295  /* Re-enable channels; because auto-init is disabled */
296  /* Disable otherwise transmission is constantly ongoing */
297  dmaSetChEnable((dmaChannel_t)dma_spiDmaChannels[spiIndex].txChannel, (dmaTriggerType_t)DMA_HW);
298  dmaSetChEnable((dmaChannel_t)dma_spiDmaChannels[spiIndex].rxChannel, (dmaTriggerType_t)DMA_HW);
299 
300  /* DMA config registers written, leave privilege mode */
302 
303  /* DMA_REQ_Enable */
304  /* Starts DMA requests if SPIEN is also set to 1 */
305  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
306  uint32_t txBuffer = pTxBuff[0u];
307  txBuffer |= ((uint32)DataFormat << 24U) | ((uint32)ChipSelect << 16U) | (WDelay) | (Chip_Select_Hold);
308  /**
309  * Send first word without DMA because when writing config to DAT1
310  * the HW CS pin are asserted immediately, even if SPIEN bit in GCR1 is 0.
311  * The C2TDELAY is then taken into account before the transmission.
312  */
313  pSpiInterface->pNode->DAT1 = txBuffer;
314  uint32_t timeoutIterations = SPI_TX_EMPTY_TIMEOUT_ITERATIONS;
315  while (((pSpiInterface->pNode->FLG & (uint32)((uint32_t)1u << SPI_TX_BUFFER_EMPTY_FLAG_POSITION)) == 0u) &&
316  (timeoutIterations > 0u)) {
317  timeoutIterations--;
318  }
319  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
320 
321  retVal = STD_OK;
322  }
323  }
325 
326  return retVal;
327 }
328 
329 extern STD_RETURN_TYPE_e SPI_Lock(uint8_t spi) {
330  /* AXIVION Routine Generic-MissingParameterAssert: spi: parameter accepts whole range */
331 
332  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
333 
335  if ((spi < spi_nrBusyFlags) && (spi_busyFlags[spi] == SPI_IDLE)) {
336  spi_busyFlags[spi] = SPI_BUSY;
337  retVal = STD_OK;
338  } else {
339  retVal = STD_NOT_OK;
340  }
342 
343  return retVal;
344 }
345 
346 extern void SPI_Unlock(uint8_t spi) {
347  /* AXIVION Routine Generic-MissingParameterAssert: spi: parameter accepts whole range */
348 
350  if (spi < spi_nrBusyFlags) {
351  spi_busyFlags[spi] = SPI_IDLE;
352  }
354 }
355 
356 extern void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled) {
357  FAS_ASSERT(pNode != NULL_PTR);
358  FAS_ASSERT(bit <= (enum spiPinSelect)MCU_LARGEST_PIN_NUMBER);
359 
360  /* retrieve current configuration */
361  spi_config_reg_t configRegisterBuffer = {0};
362  if (pNode == spiREG1) {
363  spi1GetConfigValue(&configRegisterBuffer, CurrentValue);
364  } else if (pNode == spiREG2) {
365  spi2GetConfigValue(&configRegisterBuffer, CurrentValue);
366  } else if (pNode == spiREG3) {
367  spi3GetConfigValue(&configRegisterBuffer, CurrentValue);
368  } else if (pNode == spiREG4) {
369  spi4GetConfigValue(&configRegisterBuffer, CurrentValue);
370  } else if (pNode == spiREG5) {
371  spi5GetConfigValue(&configRegisterBuffer, CurrentValue);
372  } else {
373  /* invalid SPI node */
375  }
376  uint32_t newPc0 = configRegisterBuffer.CONFIG_PC0;
377 
378  if (hardwareControlled == false) {
379  /* bit has to be cleared */
380  newPc0 &= ~(uint32_t)((uint32_t)1u << (uint8_t)(bit));
381  } else {
382  /* bit has to be set */
383  newPc0 |= (uint32_t)((uint32_t)1u << (uint8_t)(bit));
384  }
385 
386  /* set new port value */
387  spiSetFunctional(pNode, newPc0);
388 }
389 
391  SPI_INTERFACE_CONFIG_s *pSpiInterface,
392  uint16_t *pTxBuff,
393  uint16_t *pRxBuff,
394  uint32_t frameLength) {
395  FAS_ASSERT(pSpiInterface != NULL_PTR);
396  FAS_ASSERT(pTxBuff != NULL_PTR);
397  FAS_ASSERT(pRxBuff != NULL_PTR);
398  FAS_ASSERT(frameLength > 0u);
399  /** SPI receive works only with HW Chip Select */
400  FAS_ASSERT(pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE);
401 
402  STD_RETURN_TYPE_e retVal = STD_OK;
403 
405  /* Go to privilege mode to write DMA config registers */
406  (void)FSYS_RaisePrivilege();
407 
408  /* DMA_REQ Disable */
409  pSpiInterface->pNode->INT0 &= ~DMAREQEN_BIT;
410  pSpiInterface->pNode->GCR1 &= ~SPIEN_BIT;
411 
412  /* Write FMT configuration in DAT1; as SPI is configured as slave, this does not provoke a transmission */
413  SPIDATAFMT_t DataFormat = pSpiInterface->pConfig->DFSEL;
414  pSpiInterface->pNode->DAT1 |= ((uint32)DataFormat << SPI_DATA_FORMAT_FIELD_POSITION);
415 
416  /* Set Tx buffer address */
417  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel].ISADDR =
418  (uint32_t)pTxBuff;
419  /* Set number of Tx bytes to send */
420  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel].ITCOUNT =
421  (frameLength << 16U) | 1U;
422 
423  /* Set Rx buffer address */
424  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel].IDADDR =
425  (uint32_t)pRxBuff;
426  /* Set number of Rx bytes to receive */
427  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel].ITCOUNT =
428  (frameLength << 16U) | 1U;
429 
430  /* Re-enable channels; because auto-init is disabled */
431  /* Disable otherwise transmission is constantly on going */
432  dmaSetChEnable(
433  (dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel, (dmaTriggerType_t)DMA_HW);
434  dmaSetChEnable(
435  (dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel, (dmaTriggerType_t)DMA_HW);
436 
437  /* DMA config registers written, leave privilege mode */
439 
441 
442  /* Activate chip selects according to bitmask register CSNR */
443  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
444  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
445  /* Bitmask = 0 --> HW CS active --> set pin as SPI functional pin */
446  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
447  }
448  }
449 
450  /* DMA_REQ Enable */
451  /* Starts DMA requests if SPIEN is also set to 1 */
452  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
453  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
454 
455  return retVal;
456 }
457 
458 extern void SPI_DmaSendLastByte(uint8_t spiIndex) {
460  dma_spiInterfaces[spiIndex]->DAT1 = spi_txLastWord[spiIndex];
461 }
462 
463 /* AXIVION Next Codeline Style Linker-Multiple_Definition: TI HAL only provides a weak implementation */
464 /* Doxygen comment needs to be here, as this is from a TI generated HAL header */
465 /**
466  * @brief SPI Interrupt callback
467  * @param[in] spi spi device
468  * @param flags flags to be passed
469  */
470 void UNIT_TEST_WEAK_IMPL spiNotification(spiBASE_t *spi, uint32 flags) {
471 }
472 
474  FAS_ASSERT(pNode != NULL_PTR);
475  const SpiDataStatus_t spiStatus = SpiTxStatus(pNode);
476  STD_RETURN_TYPE_e retval = STD_OK;
477  if (spiStatus == SPI_PENDING) {
478  retval = STD_NOT_OK;
479  }
480  return retval;
481 }
482 
483 extern uint8_t SPI_GetSpiIndex(spiBASE_t *pNode) {
484  FAS_ASSERT(pNode != NULL_PTR);
485  uint8_t spiIndex = 0u;
486 
487  if (pNode == spiREG1) {
488  spiIndex = SPI_SPI1_INDEX;
489  } else if (pNode == spiREG2) {
490  spiIndex = SPI_SPI2_INDEX;
491  } else if (pNode == spiREG3) {
492  spiIndex = SPI_SPI3_INDEX;
493  } else if (pNode == spiREG4) {
494  spiIndex = SPI_SPI4_INDEX;
495  } else if (pNode == spiREG5) {
496  spiIndex = SPI_SPI5_INDEX;
497  } else {
498  /** Invalid SPI node */
500  }
501 
502  return spiIndex;
503 }
504 
505 /*========== Externalized Static Function Implementations (Unit Test) =======*/
Headers for the driver for the DMA module.
spiBASE_t * dma_spiInterfaces[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:85
DMA_CHANNEL_CONFIG_s dma_spiDmaChannels[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:67
#define SPIEN_BIT
Definition: dma_cfg.h:111
#define DMA_NUMBER_SPI_INTERFACES
Definition: dma_cfg.h:107
#define DMAREQEN_BIT
Definition: dma_cfg.h:109
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:248
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:126
STD_RETURN_TYPE_e
Definition: fstd_types.h:81
@ STD_NOT_OK
Definition: fstd_types.h:83
@ STD_OK
Definition: fstd_types.h:82
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:76
Function to switch between user mode and privilege mode.
#define FSYS_SWITCH_TO_USER_MODE()
Switch back to user mode.
Definition: fsystem.h:132
long FSYS_RaisePrivilege(void)
Raise privilege.
Definition: test_htsensor.c:67
#define UNIT_TEST_WEAK_IMPL
Definition: general.h:95
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:87
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:94
Header for the driver for the IO module.
void MCU_Delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:86
#define MCU_LARGEST_PIN_NUMBER
largest pin number that exists in TMS570LC4357
Definition: mcu.h:70
Declaration of the OS wrapper interface.
void OS_ExitTaskCritical(void)
Exit Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os_freertos.c:135
void OS_EnterTaskCritical(void)
Enter Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os_freertos.c:131
STD_RETURN_TYPE_e SPI_TransmitReceiveDataDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:219
void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled)
Sets the functional of a SPI pin.
Definition: spi.c:356
STD_RETURN_TYPE_e SPI_CheckInterfaceAvailable(spiBASE_t *pNode)
Returns STD_OK if the SPI interface can be used again.
Definition: spi.c:473
void SPI_DmaSendLastByte(uint8_t spiIndex)
Used to send last byte per SPI.
Definition: spi.c:458
STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay)
Sends a dummy byte to wake up the SPI interface.
Definition: spi.c:86
void SPI_FramTransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA, wrappe for FRAM.
Definition: spi.c:206
STD_RETURN_TYPE_e SPI_Lock(uint8_t spi)
Locks SPI interfaces.
Definition: spi.c:329
bool spi_rxFinished
Definition: spi.c:78
STD_RETURN_TYPE_e SPI_SlaveSetReceiveDataDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:390
void SPI_Unlock(uint8_t spi)
Unlocks SPI interfaces.
Definition: spi.c:346
STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint32 frameLength)
Transmits data on SPI without DMA.
Definition: spi.c:96
void UNIT_TEST_WEAK_IMPL spiNotification(spiBASE_t *spi, uint32 flags)
SPI Interrupt callback.
Definition: spi.c:470
STD_RETURN_TYPE_e SPI_TransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:148
uint8_t SPI_GetSpiIndex(spiBASE_t *pNode)
Returns index of SPI node.
Definition: spi.c:483
#define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS
Definition: spi.c:71
static uint32_t spi_txLastWord[DMA_NUMBER_SPI_INTERFACES]
Definition: spi.c:67
bool spi_txFinished
Definition: spi.c:77
Headers for the driver for the SPI module.
SPI_BUSY_STATE_e spi_busyFlags[]
Definition: spi_cfg.c:260
const uint8_t spi_nrBusyFlags
Definition: spi_cfg.c:269
#define SPI_SPI5_INDEX
Definition: spi_cfg.h:74
#define SPI_HARDWARE_CHIP_SELECT_FIELD_POSITION
Definition: spi_cfg.h:84
#define SPI_SPI2_INDEX
Definition: spi_cfg.h:71
@ SPI_IDLE
Definition: spi_cfg.h:109
@ SPI_BUSY
Definition: spi_cfg.h:110
#define SPI_DATA_FORMAT_FIELD_POSITION
Definition: spi_cfg.h:87
#define SPI_WDEL_BIT
Definition: spi_cfg.h:81
#define SPI_TX_EMPTY_TIMEOUT_ITERATIONS
Definition: spi_cfg.h:96
#define SPI_CSHOLD_BIT
Definition: spi_cfg.h:78
#define SPI_MAX_NUMBER_HW_CS
Definition: spi_cfg.h:99
#define SPI_SPI4_INDEX
Definition: spi_cfg.h:73
#define SPI_TX_BUFFER_EMPTY_FLAG_POSITION
Definition: spi_cfg.h:90
#define SPI_SPI1_INDEX
Definition: spi_cfg.h:70
#define SPI_PC0_CLEAR_HW_CS_MASK
Definition: spi_cfg.h:93
@ SPI_CHIP_SELECT_SOFTWARE
Definition: spi_cfg.h:117
@ SPI_CHIP_SELECT_HARDWARE
Definition: spi_cfg.h:116
#define SPI_SPI3_INDEX
Definition: spi_cfg.h:72
dmaChannel_t rxChannel
Definition: dma_cfg.h:128
dmaChannel_t txChannel
Definition: dma_cfg.h:127
SPI_CHIP_SELECT_TYPE_e csType
Definition: spi_cfg.h:128
volatile uint32_t * pGioPort
Definition: spi_cfg.h:126
spiDAT1_t * pConfig
Definition: spi_cfg.h:124
spiBASE_t * pNode
Definition: spi_cfg.h:125