The foxBMS secondary mcu API documentation
io_mcu_cfg.h File Reference

Configuration for the I/O ports for MCU1 (secondary). More...

#include "io_package_cfg.h"
Include dependency graph for io_mcu_cfg.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define IO_PIN_TRACECLK   IO_PE_2
 
#define IO_PIN_TRACED0   IO_PE_3
 
#define IO_PIN_TRACED1   IO_PE_4
 
#define IO_PIN_TRACED2   IO_PE_5
 
#define IO_PIN_TRACED3   IO_PE_6
 
#define IO_PIN_DEBUG_LED_1   IO_PC_2
 
#define IO_PIN_DEBUG_LED_0   IO_PC_3
 
#define IO_PIN_BMS_INTERFACE_SPI_NSS   IO_PA_4
 
#define IO_PIN_BMS_INTERFACE_SPI_SCK   IO_PA_5
 
#define IO_PIN_BMS_INTERFACE_SPI_MISO   IO_PA_6
 
#define IO_PIN_BMS_INTERFACE_SPI_MOSI   IO_PA_7
 
#define IO_PIN_FTDI_TX   IO_PB_10
 
#define IO_PIN_FTDI_RX   IO_PB_11
 
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS   IO_PB_12
 
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK   IO_PD_3
 
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI   IO_PB_14
 
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO   IO_PB_15
 
#define IO_PIN_INTERLOCK_CONTROL   IO_PD_4
 
#define IO_PIN_INTERLOCK_FEEDBACK   IO_PD_5
 
#define IO_PIN_CAN_0_TRANS_STANDBY_CONTROL   IO_PC_12
 
#define IO_PIN_CAN_0_TX   IO_PB_13
 
#define IO_PIN_CAN_0_RX   IO_PB_5
 
#define IO_PIN_BMS_INTERFACE_0_GPIO_0   IO_PA_10
 
#define IO_PIN_BMS_INTERFACE_0_GPIO_1   IO_PA_11
 
#define IO_PIN_BMS_INTERFACE_0_GPIO_2   IO_PA_12
 
#define IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION   IO_PB_4
 
#define IO_PIN_GPIO_0   IO_PD_2
 
#define IO_PIN_GPIO_1   IO_PD_1
 
#define IO_PIN_GPIO_2   IO_PD_0
 
#define IO_PIN_GPIO_3   IO_PC_12
 
#define IO_PIN_GPIO_4   IO_PC_11
 
#define IO_PIN_GPIO_5   IO_PC_10
 

Detailed Description

Configuration for the I/O ports for MCU1 (secondary).

BSD 3-Clause License Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

We kindly request you to use one or more of the following phrases to refer to foxBMS in your hardware, software, documentation or advertising materials:

″This product uses parts of foxBMS®″

″This product includes parts of foxBMS®″

″This product is derived from foxBMS®″

Author
foxBMS Team
Date
18.01.2016 (date of creation)
Module-prefix IO_PIN_MCU_1

This file describes the names of the signals connected to the given hardware pin at the cpu.

Macro Definition Documentation

◆ IO_PIN_BMS_INTERFACE_0_GPIO_0

#define IO_PIN_BMS_INTERFACE_0_GPIO_0   IO_PA_10

◆ IO_PIN_BMS_INTERFACE_0_GPIO_1

#define IO_PIN_BMS_INTERFACE_0_GPIO_1   IO_PA_11

◆ IO_PIN_BMS_INTERFACE_0_GPIO_2

#define IO_PIN_BMS_INTERFACE_0_GPIO_2   IO_PA_12

◆ IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION

#define IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION   IO_PB_4

◆ IO_PIN_BMS_INTERFACE_SPI_MISO

#define IO_PIN_BMS_INTERFACE_SPI_MISO   IO_PA_6

◆ IO_PIN_BMS_INTERFACE_SPI_MOSI

#define IO_PIN_BMS_INTERFACE_SPI_MOSI   IO_PA_7

◆ IO_PIN_BMS_INTERFACE_SPI_NSS

#define IO_PIN_BMS_INTERFACE_SPI_NSS   IO_PA_4

◆ IO_PIN_BMS_INTERFACE_SPI_SCK

#define IO_PIN_BMS_INTERFACE_SPI_SCK   IO_PA_5

◆ IO_PIN_CAN_0_RX

#define IO_PIN_CAN_0_RX   IO_PB_5

◆ IO_PIN_CAN_0_TRANS_STANDBY_CONTROL

#define IO_PIN_CAN_0_TRANS_STANDBY_CONTROL   IO_PC_12

◆ IO_PIN_CAN_0_TX

#define IO_PIN_CAN_0_TX   IO_PB_13

◆ IO_PIN_DEBUG_LED_0

#define IO_PIN_DEBUG_LED_0   IO_PC_3

◆ IO_PIN_DEBUG_LED_1

#define IO_PIN_DEBUG_LED_1   IO_PC_2

◆ IO_PIN_FTDI_RX

#define IO_PIN_FTDI_RX   IO_PB_11

◆ IO_PIN_FTDI_TX

#define IO_PIN_FTDI_TX   IO_PB_10

◆ IO_PIN_GPIO_0

#define IO_PIN_GPIO_0   IO_PD_2

◆ IO_PIN_GPIO_1

#define IO_PIN_GPIO_1   IO_PD_1

◆ IO_PIN_GPIO_2

#define IO_PIN_GPIO_2   IO_PD_0

◆ IO_PIN_GPIO_3

#define IO_PIN_GPIO_3   IO_PC_12

◆ IO_PIN_GPIO_4

#define IO_PIN_GPIO_4   IO_PC_11

◆ IO_PIN_GPIO_5

#define IO_PIN_GPIO_5   IO_PC_10

◆ IO_PIN_INTERLOCK_CONTROL

#define IO_PIN_INTERLOCK_CONTROL   IO_PD_4

◆ IO_PIN_INTERLOCK_FEEDBACK

#define IO_PIN_INTERLOCK_FEEDBACK   IO_PD_5

◆ IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO

#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO   IO_PB_15

◆ IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI

#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI   IO_PB_14

◆ IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS

#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS   IO_PB_12

◆ IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK

#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK   IO_PD_3

◆ IO_PIN_TRACECLK

#define IO_PIN_TRACECLK   IO_PE_2

◆ IO_PIN_TRACED0

#define IO_PIN_TRACED0   IO_PE_3

◆ IO_PIN_TRACED1

#define IO_PIN_TRACED1   IO_PE_4

◆ IO_PIN_TRACED2

#define IO_PIN_TRACED2   IO_PE_5

◆ IO_PIN_TRACED3

#define IO_PIN_TRACED3   IO_PE_6