IO Module Sources¶
io.c¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io.c
* @author foxBMS Team
* @date 26.08.2015 (date of creation)
* @ingroup DRIVERS
* @prefix IO
*
* @brief Driver for the I/O ports (pins).
*
*/
/*================== Includes =============================================*/
#include "io.h"
#include "driver_assert.h"
/*================== Macros and Definitions ===============================*/
#define IO_GET_GPIOx(_N) ((GPIO_TypeDef *)(GPIOA_BASE + (GPIOB_BASE-GPIOA_BASE)*(_N)))
#define GPIO_MODE ((uint32_t)0x00000003U)
#define EXTI_MODE ((uint32_t)0x10000000U)
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define RISING_EDGE ((uint32_t)0x00100000U)
#define FALLING_EDGE ((uint32_t)0x00200000U)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define GPIO_NUMBER ((uint32_t)16U)
/*================== Constant and Variable Definitions ====================*/
/*================== Function Prototypes ==================================*/
static STD_RETURN_TYPE_e IO_ClkInit(void);
#ifdef IO_PIN_LOCKING
static IO_HAL_STATUS_e IO_LockPin(IO_PORTS_e pin);
#endif
static STD_RETURN_TYPE_e GPIO_Check(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
/*================== Function Implementations =============================*/
/*================== Public functions =====================================*/
STD_RETURN_TYPE_e IO_Init(const IO_PIN_CFG_s *io_config) {
if (NULL_PTR == io_config) {
return E_NOT_OK; /* configuration error */
}
STD_RETURN_TYPE_e retVal = E_NOT_OK;
STD_RETURN_TYPE_e clk_ok = E_NOT_OK;
STD_RETURN_TYPE_e config_ok = E_OK;
GPIO_InitTypeDef GPIO_InitStructure;
clk_ok = IO_ClkInit();
if (E_OK == clk_ok) {
for (uint8_t i = 0; i < io_cfg_length; i++) {
GPIO_InitStructure.Pin = (uint16_t) (1<< ((io_config[i].pin) % IO_NR_OF_PINS_PER_PORT));
GPIO_InitStructure.Mode = io_config[i].mode;
GPIO_InitStructure.Pull = io_config[i].pinpull;
GPIO_InitStructure.Speed = io_config[i].speed;
if (IO_ALTERNATE_NO_ALTERNATE != io_config[i].alternate) {
GPIO_InitStructure.Alternate = io_config[i].alternate;
}
HAL_GPIO_Init(IO_GET_GPIOx(io_config[i].pin/IO_NR_OF_PINS_PER_PORT), &GPIO_InitStructure);
if (io_config[i].initvalue == IO_PIN_SET) {
/* IO pin shall be high, check if the pin supports this */
if ((IO_MODE_OUTPUT_PP == io_config[i].mode) || (IO_MODE_OUTPUT_OD == io_config[i].mode) ||
(IO_MODE_AF_PP == io_config[i].mode) || (IO_MODE_AF_OD == io_config[i].mode)) {
IO_WritePin(io_config[i].pin, IO_PIN_SET);
}
} else if ((io_config[i].initvalue == IO_PIN_RESET) ||
(io_config[i].initvalue == IO_PIN_DC)) {
/* IO pin shall be low or state does not matter */
IO_WritePin(io_config[i].pin, IO_PIN_RESET);
} else {
/* configuration error, an unknown init value has been used */
DAS_trap();
}
config_ok = (GPIO_Check(IO_GET_GPIOx(io_config[i].pin/IO_NR_OF_PINS_PER_PORT), &GPIO_InitStructure) == E_OK ? config_ok : E_NOT_OK);
}
}
#ifdef IO_PIN_LOCKING
STD_RETURN_TYPE_e pinLocking_ok = E_NOT_OK;
if (E_OK == config_ok) {
IO_HAL_STATUS_e pinLockingState = IO_HAL_STATUS_ERROR;
uint8_t requestedLocks = 0;
uint8_t successfulLocks = 0;
for (uint8_t i = 0; i < io_cfg_length; i++) {
if (IO_PIN_LOCK_ENABLE == io_config[i].pinlock) {
requestedLocks++;
pinLockingState = IO_LockPin(io_config[i].pin);
}
if (IO_HAL_STATUS_OK == pinLockingState) {
successfulLocks++;
} else {
break;
}
pinLockingState = IO_HAL_STATUS_ERROR;
}
if (requestedLocks == successfulLocks) {
pinLocking_ok = E_OK;
}
}
#endif
if ((E_OK == clk_ok) &&
(E_OK == config_ok)
#ifdef IO_PIN_LOCKING
&& (E_OK == pinLocking_ok)
#endif
) {
retVal = E_OK;
}
return retVal;
}
IO_PIN_STATE_e IO_ReadPin(IO_PORTS_e pin) {
IO_PIN_STATE_e currentPinState;
uint16_t getPin = (uint16_t) (1 << (pin%IO_NR_OF_PINS_PER_PORT));
currentPinState = HAL_GPIO_ReadPin(IO_GET_GPIOx(pin/IO_NR_OF_PINS_PER_PORT), getPin);
return currentPinState;
}
void IO_WritePin(IO_PORTS_e pin, IO_PIN_STATE_e requestedPinState) {
uint16_t setPin = (uint16_t) (1 << (pin%IO_NR_OF_PINS_PER_PORT));
HAL_GPIO_WritePin(IO_GET_GPIOx(pin/IO_NR_OF_PINS_PER_PORT), setPin, requestedPinState);
}
void IO_TogglePin(IO_PORTS_e pin) {
uint16_t setPin = (uint16_t) (1 << (pin%IO_NR_OF_PINS_PER_PORT));
HAL_GPIO_TogglePin(IO_GET_GPIOx(pin/IO_NR_OF_PINS_PER_PORT), setPin);
}
void IO_EXTI_IRQHandler(IO_PORTS_e pin) {
HAL_GPIO_EXTI_IRQHandler((uint16_t) (1 << (pin%IO_NR_OF_PINS_PER_PORT)));
}
void IO_EXTI_Callback(IO_PORTS_e pin) {
HAL_GPIO_EXTI_Callback((uint16_t) (1 << (pin%IO_NR_OF_PINS_PER_PORT)));
}
/*================== Static functions =====================================*/
/**
* @brief IO_ClkInit() activates the port clocks of the used
* package.
*
* IO_ClkInit is automatically called in IO_Init(). The clocks of each port
* available at the used package is enabled.
*
* @return retVal (type: STD_RETURN_TYPE_e) returns E_OK when finished
*/
static STD_RETURN_TYPE_e IO_ClkInit(void) {
STD_RETURN_TYPE_e retVal = E_NOT_OK;
#if defined(IO_PACKAGE_LQFP100) || defined(IO_PACKAGE_LQFP144) || defined(IO_PACKAGE_LQFP176)
__GPIOA_CLK_ENABLE();
__GPIOB_CLK_ENABLE();
__GPIOC_CLK_ENABLE();
__GPIOD_CLK_ENABLE();
__GPIOE_CLK_ENABLE();
#endif /* IO_PACKAGE_LQFP100 */
#if defined(IO_PACKAGE_LQFP144) || defined(IO_PACKAGE_LQFP176)
__GPIOF_CLK_ENABLE();
__GPIOG_CLK_ENABLE();
__GPIOH_CLK_ENABLE();
#endif /* IO_PACKAGE_LQFP144 */
#if defined(IO_PACKAGE_LQFP176)
__GPIOI_CLK_ENABLE();
#endif /* IO_PACKAGE_LQFP176 */
retVal = E_OK;
return retVal;
}
#ifdef IO_PIN_LOCKING
/**
* @brief Locks the configuration of a pin.
*
* IO_LockPin(IO_PORTS_e) gets called in IO_Init(IO_PIN_CFG_s)
* when the IO_PIN_LOCKING macro is defined. If IO_PIN_LOCK_ENABLE is set
* in IO_PIN_CFG_s io_cfg[] the following registers are locked:
* - GPIOx_MODER,
* - GPIOx_OTYPER,
* - GPIOx_OSPEEDR,
* - GPIOx_PUPDR,
* - GPIOx_AFRL and
* - GPIOx_AFRH
*
* @param pin (type: IO_PORTS_e)
*
* @return currentPinStatus (type: IO_HAL_STATUS_e) returns
* IO_HAL_STATUS_OK when pin locking of the requested pin
* was successful.
*/
static IO_HAL_STATUS_e IO_LockPin(IO_PORTS_e pin) {
IO_HAL_STATUS_e currentPinStatus;
uint16_t setPin = (uint16_t) (1 << (pin%IO_NR_OF_PINS_PER_PORT));
currentPinStatus = HAL_GPIO_LockPin(IO_GET_GPIOx(pin/IO_NR_OF_PINS_PER_PORT), setPin);
return currentPinStatus;
}
#endif
/**
* @brief Checks the GPIOx peripheral according to the specified parameters in the GPIO_Init.
*
* <hr>
* @attention This function is based on the function 'HAL_GPIO_Init' from stm32f4xx_hal_gpio.c.
* The license of stm32f4xx_hal_gpio.c is as follows:
*
******************************************************************************
*
* @attention <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*
* <hr>
*
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval E_OK on success, E_NOT_OK on failure
*/
STD_RETURN_TYPE_e GPIO_Check(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
uint32_t position;
uint32_t ioposition = 0x00U;
uint32_t iocurrent = 0x00U;
uint32_t temp = 0x00U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Check the port pins */
for (position = 0U; position < GPIO_NUMBER; position++) {
/* Get the IO position */
ioposition = ((uint32_t)0x01U) << position;
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
if (iocurrent == ioposition) {
/*--------------------- GPIO Mode Checking ------------------------*/
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) {
/* Check Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U));
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
if (GPIOx->AFR[position >> 3U] != temp) return E_NOT_OK;
}
/* Check IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
if (GPIOx->MODER != temp) return E_NOT_OK;
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) {
/* Check the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
temp |= (GPIO_Init->Speed << (position * 2U));
if (GPIOx->OSPEEDR != temp) return E_NOT_OK;
/* Check the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position);
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
if (GPIOx->OTYPER != temp) return E_NOT_OK;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
if (GPIOx->PUPDR != temp) return E_NOT_OK;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Check the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) {
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
if (SYSCFG->EXTICR[position >> 2U] != temp) return E_NOT_OK;
/* Check EXTI line configuration */
temp = EXTI->IMR;
temp &= ~((uint32_t)iocurrent);
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) {
temp |= iocurrent;
}
if (EXTI->IMR != temp) return E_NOT_OK;
temp = EXTI->EMR;
temp &= ~((uint32_t)iocurrent);
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) {
temp |= iocurrent;
}
if (EXTI->EMR != temp) return E_NOT_OK;
/* Check Rising Falling edge configuration */
temp = EXTI->RTSR;
temp &= ~((uint32_t)iocurrent);
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) {
temp |= iocurrent;
}
if (EXTI->RTSR != temp) return E_NOT_OK;
temp = EXTI->FTSR;
temp &= ~((uint32_t)iocurrent);
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) {
temp |= iocurrent;
}
if (EXTI->FTSR != temp) return E_NOT_OK;
}
}
}
return E_OK;
}
io.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io.h
* @author foxBMS Team
* @date 26.08.2015 (date of creation)
* @ingroup DRIVERS
* @prefix IO
*
* @brief Header for the driver for the I/O ports (pins)..
*
* The io-module allows a neat configuration and initialization of the microcontroller
* pins of the foxbms hardware. The io-module enables an easy read and write access
* to the microcontroller pins.
*
* The configuration of the GPIOs is performed through the following parts of the io-module:
* - config\io_package_cfg.h:
* - If the foxBMS board is used, no changes have to be made my the user.
* - Configuration file config\io_foxbms_mcu0_cfg.h respectively config.h.h:
* - Defines the names of the signals connected to the pins of the STM32F429. The macro used
* for identification of the pin-port assignment are taken from io_package_cfg.h
* - config\io_cfg.h:
* - Defines the package type of the STM32F29 used on the board. The list of supported packages
* of the STM32F429 can be found in io_package_cfg.h.
* - Defines if the pin configuration locking of the is enabled.
* - Includes the pin configuration file io_foxbms_mcu0_cfg.h.
* - config\io_cfg.c
* - Determines the configuration of each used pin. The configuration is in the io_cfg[] array.
* The possible configurations of each GPIO are given in the official STM32F29
* <a href"http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00071990.pdf">datasheet</a>.
* The io-driver DOES NOT check whether your GPIO configuration is valid.
*/
#ifndef IO_H_
#define IO_H_
/*================== Includes =============================================*/
#include "io_cfg.h"
/*================== Macros and Definitions ===============================*/
/*================== Constant and Variable Definitions ====================*/
/*================== Function Prototypes ==================================*/
/**
* @brief Initializes all ports and pins of the microcontroller
*
* The pins of the microcontroller package are initialized
* by calling IO_Init(). The pins are identified by a signal
* name given in io_cfg_foxbms_mcu0_generated.h. The
* function gets the configuration of the pins by the array
* *io_cfg, which is defined is done in io_cfg.c.
* The io_cfg array allows you to set the functionality of
* the pin in the following order of the IO_PIN_CFG_s struct:
* - pin
* - signal name
* - mode
* -input
* - output
* - push-pull
* - open drain
* - analog
* - interrupt
* - rising edge
* - falling edge
* - rising falling edge
* - event
* - rising edge
* - falling edge
* - rising falling edge
* - logic level
* - no pull
* - pull up
* - pull down
* - speed
* - low
* - medium
* - fast
* - high
* - alternate functions
* - RTC_50Hz
* - MCO
* - TAMPER
* - SWJ (SWD and JTAG)
* - TRACE
* - TIM
* - I2C
* - SPI
* - I2S
* - SAI
* - USART
* - UART
* - CAN
* - LCD-TFT
* - OTG
* - pin configuration locking
* - disable
* - enable
* - default value of the pin
* - reset/low
* - set/high
*
* If the define IO_PIN_LOCKING is set in file io_cfg.h the pin configuration locking is
* performed as defined in file io_cfg.c at the array IO_PIN_CFG_s io_cfg.
*
* The default value of the pin/signal is optional. If the not given the signal is set low.
*
* @param *io_cfg (type: IO_PIN_CFG_s)
*
* @return retVal (type: STD_RETURN_TYPE_e)
*/
extern STD_RETURN_TYPE_e IO_Init(const IO_PIN_CFG_s *io_cfg);
/**
* @brief Returns the state of a pin
*
* Reads the state/output of the given pin, which is given by its
* symbolic name.
*
* @param pin (type: IO_PORTS_e)
*
* @return currentPinState (type: IO_PIN_STATE_e) returns
* currentPinState | physical pin out
* ---------------- | -----------------
* GPIO_PIN_SET | high
* GPIO_PIN_RESET | low
*/
extern IO_PIN_STATE_e IO_ReadPin(IO_PORTS_e pin);
/**
* @brief Sets the state of a pin
*
* Sets the state/output of the given pin, which is given by its
* symbolic name.
*
* @param pin (type: IO_PORTS_e) requested pin to be set
*
* @param requestedPinState (type: IO_PIN_STATE_e) requests
* requestedPinState | physical pin out
* ------------------- | -----------------
* GPIO_PIN_SET | high
* GPIO_PIN_RESET | low
*/
extern void IO_WritePin(IO_PORTS_e pin, IO_PIN_STATE_e requestedPinState);
/**
* @brief Toggles the state of a pin
*
* @param pin (type: IO_PORTS_e)
*/
extern void IO_TogglePin(IO_PORTS_e pin);
/**
* @brief Calls the EXTI_IRQHandler of the given pin
*
* @param pin (type: IO_PORTS_e)
*/
extern void IO_EXTI_IRQHandler(IO_PORTS_e pin);
/**
* @brief Calls the EXTI_Callback of the given pin
*
* @param pin (type: IO_PORTS_e)
*/
extern void IO_EXTI_Callback(IO_PORTS_e pin);
/*================== Function Implementations =============================*/
#endif /* IO_H_ */
io_cfg.c¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_cfg.c
* @author foxBMS Team
* @date 26.08.2015 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO
*
* @brief Configuration for the driver for the I/O ports
*
* ==============================================================================
* Detailed Configuration of the GPIOs
* ==============================================================================
*
* The functionality of the signal defined in io_foxbms_mcu0_cfg.h is set in the array
* io_cfg[], e.g. digital I/O or alternate functions like SPI, CAN, ...
*
* An incorrect definition of an signal may disturb one or more other
* signal functional definitions of pins
*
* Every entry of the io_cfg[] array consists of
* - name of the signal/pin (defined in io_foxbms_mcu0_cfg.h)
* - mode of signal/pin (input, output, ...)
* - push/pull
* - pin speed
* - alternate function (SPI, CAN, ...)
* - locking of the pin configuration (has to enabled in io_cfg.h)
* All available possibilities for each pin are found in the official<a href"http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00071990.pdf">datasheet</a>.
*
*/
/*================== Includes =============================================*/
#include "io_cfg.h"
/*================== Macros and Definitions ===============================*/
/*================== Constant and Variable Definitions ====================*/
const IO_PIN_CFG_s io_cfg[] = {
/*
* Trace
*/
{IO_PIN_TRACECLK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED0, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED2, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED3, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
/*
* Data Storage SPI and Supply
*/
{IO_PIN_DATA_STORAGE_EEPROM_SPI_NSS, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_DATA_STORAGE_MEMORY_CARD_SPI_NSS, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_DATA_STORAGE_SPI_MISO, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI6, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_DATA_STORAGE_SPI_SCK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI6, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_DATA_STORAGE_SPI_MOSI, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI6, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_MEMORY_CARD_SUPPLY_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
/*
* Flexible Memory Controller
*/
{IO_PIN_FMC_RAM_A0, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A2, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A3, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A4, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A5, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A6, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A7, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A8, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A9, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A10, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_A11, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D0, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D2, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D3, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D4, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D5, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D6, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D7, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D8, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D9, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D10, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D11, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D12, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D13, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D14, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_D15, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_SDNWE, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_SDNRAS, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_SDNE1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_SDCKE1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_BA0, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_BA1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_SDCLK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_NBL0, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_SDNCAS, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_FMC_RAM_NBL1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF12_FMC, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
/*
* Debug LEDs
*/
{IO_PIN_DEBUG_LED_1, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_DEBUG_LED_0, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
/*
* ADCs
*/
{IO_PIN_ADC_CH_0, IO_MODE_ANALOG, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_DISABLE, IO_PIN_DC},
{IO_PIN_ADC_CH_1, IO_MODE_ANALOG, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_DISABLE, IO_PIN_DC},
{IO_PIN_ADC_CH_2, IO_MODE_ANALOG, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_DISABLE, IO_PIN_DC},
{IO_PIN_ADC_CH_3, IO_MODE_ANALOG, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_DISABLE, IO_PIN_DC},
{IO_PIN_ADC_CH_4, IO_MODE_ANALOG, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_DISABLE, IO_PIN_DC},
/*
* Bender
*/
{IO_PIN_BENDER_SUPPLY_ENABLE, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BENDER_OK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_BENDER_PWM, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF3_TIM9, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
/*
* Contactors' Control and Feedback Pins
*/
{IO_PIN_INTERLOCK_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_INTERLOCK_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_0_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_0_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_1_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_1_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_2_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_2_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_3_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_3_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_4_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_4_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_5_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_5_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_6_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_6_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_7_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_7_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CONTACTOR_8_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CONTACTOR_8_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
/*
* Interfaces
*/
{IO_PIN_BMS_INTERFACE_SPI_NSS, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_BMS_INTERFACE_SPI_SCK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BMS_INTERFACE_SPI_MISO, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BMS_INTERFACE_SPI_MOSI, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_FPGA_INTERFACE_SPI_NSS, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI5, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_FPGA_INTERFACE_SPI_SCK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI5, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_FPGA_INTERFACE_SPI_MISO, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI5, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_FPGA_INTERFACE_SPI_MOSI, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI5, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BMS_INTERFACE_0_GPIO_0, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_BMS_INTERFACE_0_GPIO_1, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_BMS_INTERFACE_0_GPIO_2, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
/* Pin high -> forward mode, Pin low -> reverse mode */
{IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_CAN_0_TRANS_STANDBY_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_0_TX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF9_CAN0, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_0_RX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF9_CAN0, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_1_TRANS_STANDBY_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_1_TX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF9_CAN1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_1_RX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF9_CAN1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_FTDI_TX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF7_USART3, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_FTDI_RX, IO_MODE_AF_PP, IO_PIN_PULLUP, IO_SPEED_HIGH, IO_ALTERNATE_AF7_USART3, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_RS485_TX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF7_USART2, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_RS485_RX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF7_USART2, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_RS485_NRE, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_RS485_DE, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
/*
* Isolated In- and Outputs
*/
{IO_PIN_ISO_GPIO_IN_0, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_ISO_GPIO_OUT_0, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISO_GPIO_IN_1, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_ISO_GPIO_OUT_1, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISO_GPIO_IN_2, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_ISO_GPIO_OUT_2, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISO_GPIO_IN_3, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_ISO_GPIO_OUT_3, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISONOC_0_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISONOC_1_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISONOC_2_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISONOC_3_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISONOC_4_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_ISONOC_5_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
};
const uint8_t io_cfg_length = sizeof(io_cfg)/sizeof(io_cfg[0]);
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
io_mcu_cfg.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_mcu_cfg.h
* @author foxBMS Team
* @date 18.01.2016 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO_PIN_MCU_0
*
* @brief Configuration for the I/O ports for MCU0 (primary)
*
* This file describes the names of the signals connected
* to the given hardware pin at the cpu.
*
*/
#ifndef IO_MCU_CFG_H_
#define IO_MCU_CFG_H_
/*================== Includes =============================================*/
#include "io_package_cfg.h"
/*================== Macros and Definitions ===============================*/
/*
*Trace
*/
#define IO_PIN_TRACECLK IO_PE_2 /* package pin:1 */
#define IO_PIN_TRACED0 IO_PE_3 /* package pin:2 */
#define IO_PIN_TRACED1 IO_PE_4 /* package pin:3 */
#define IO_PIN_TRACED2 IO_PE_5 /* package pin:4 */
#define IO_PIN_TRACED3 IO_PE_6 /* package pin:5 */
/*
*Data Storage SPI and Supply
*/
#define IO_PIN_DATA_STORAGE_EEPROM_SPI_NSS IO_PI_8 /* package pin:7 */
#define IO_PIN_DATA_STORAGE_MEMORY_CARD_SPI_NSS IO_PI_9 /* package pin:11 */
#define IO_PIN_DATA_STORAGE_SPI_SCK IO_PG_13 /* package pin:156 */
#define IO_PIN_DATA_STORAGE_SPI_MISO IO_PG_12 /* package pin:155 */
#define IO_PIN_DATA_STORAGE_SPI_MOSI IO_PG_14 /* package pin:157 */
#define IO_PIN_MEMORY_CARD_SUPPLY_CONTROL IO_PC_1 /* package pin:33 */
/*
*Flexible Memory Controller
*/
#define IO_PIN_FMC_RAM_A0 IO_PF_0 /* package pin:16 */
#define IO_PIN_FMC_RAM_A1 IO_PF_1 /* package pin:17 */
#define IO_PIN_FMC_RAM_A2 IO_PF_2 /* package pin:18 */
#define IO_PIN_FMC_RAM_A3 IO_PF_3 /* package pin:19 */
#define IO_PIN_FMC_RAM_A4 IO_PF_4 /* package pin:20 */
#define IO_PIN_FMC_RAM_A5 IO_PF_5 /* package pin:21 */
#define IO_PIN_FMC_RAM_A6 IO_PF_12 /* package pin:60 */
#define IO_PIN_FMC_RAM_A7 IO_PF_13 /* package pin:63 */
#define IO_PIN_FMC_RAM_A8 IO_PF_14 /* package pin:64 */
#define IO_PIN_FMC_RAM_A9 IO_PF_15 /* package pin:65 */
#define IO_PIN_FMC_RAM_A10 IO_PG_0 /* package pin:66 */
#define IO_PIN_FMC_RAM_A11 IO_PG_1 /* package pin:67 */
#define IO_PIN_FMC_RAM_D0 IO_PD_14 /* package pin:104 */
#define IO_PIN_FMC_RAM_D1 IO_PD_15 /* package pin:105 */
#define IO_PIN_FMC_RAM_D2 IO_PD_0 /* package pin:142 */
#define IO_PIN_FMC_RAM_D3 IO_PD_1 /* package pin:143 */
#define IO_PIN_FMC_RAM_D4 IO_PE_7 /* package pin:68 */
#define IO_PIN_FMC_RAM_D5 IO_PE_8 /* package pin:69 */
#define IO_PIN_FMC_RAM_D6 IO_PE_9 /* package pin:70 */
#define IO_PIN_FMC_RAM_D7 IO_PE_10 /* package pin:73 */
#define IO_PIN_FMC_RAM_D8 IO_PE_11 /* package pin:74 */
#define IO_PIN_FMC_RAM_D9 IO_PE_12 /* package pin:75 */
#define IO_PIN_FMC_RAM_D10 IO_PE_13 /* package pin:76 */
#define IO_PIN_FMC_RAM_D11 IO_PE_14 /* package pin:77 */
#define IO_PIN_FMC_RAM_D12 IO_PE_15 /* package pin:78 */
#define IO_PIN_FMC_RAM_D13 IO_PD_8 /* package pin:96 */
#define IO_PIN_FMC_RAM_D14 IO_PD_9 /* package pin:97 */
#define IO_PIN_FMC_RAM_D15 IO_PD_10 /* package pin:98 */
#define IO_PIN_FMC_RAM_SDNWE IO_PC_0 /* package pin:32 */
#define IO_PIN_FMC_RAM_SDNRAS IO_PF_11 /* package pin:59 */
#define IO_PIN_FMC_RAM_SDNE1 IO_PH_6 /* package pin:83 */
#define IO_PIN_FMC_RAM_SDCKE1 IO_PH_7 /* package pin:84 */
#define IO_PIN_FMC_RAM_BA0 IO_PG_4 /* package pin:108 */
#define IO_PIN_FMC_RAM_BA1 IO_PG_5 /* package pin:109 */
#define IO_PIN_FMC_RAM_SDCLK IO_PG_8 /* package pin:112 */
#define IO_PIN_FMC_RAM_SDNCAS IO_PG_15 /* package pin:160 */
#define IO_PIN_FMC_RAM_NBL0 IO_PE_0 /* package pin:169 */
#define IO_PIN_FMC_RAM_NBL1 IO_PE_1 /* package pin:170 */
/*
*Debug LEDs
*/
#define IO_PIN_DEBUG_LED_1 IO_PC_2 /* package pin:34 */
#define IO_PIN_DEBUG_LED_0 IO_PC_3 /* package pin:35 */
/*
*ADCs
*/
#define IO_PIN_ADC_CH_0 IO_PC_4 /* package pin:54 */
#define IO_PIN_ADC_CH_1 IO_PC_5 /* package pin:55 */
#define IO_PIN_ADC_CH_2 IO_PB_0 /* package pin:56 */
#define IO_PIN_ADC_CH_3 IO_PB_1 /* package pin:57 */
#define IO_PIN_ADC_CH_4 IO_PA_1 /* package pin:41 */
/*
*Bender
*/
#define IO_PIN_BENDER_SUPPLY_ENABLE IO_PH_2 /* package pin:43 */
#define IO_PIN_BENDER_OK IO_PH_5 /* package pin:46 */
#define IO_PIN_BENDER_PWM IO_PA_3 /* package pin:47 */
/*
*Contactors' Controll and Feedback Pins
*/
#define IO_PIN_INTERLOCK_CONTROL IO_PD_4 /* package pin:146 */
#define IO_PIN_INTERLOCK_FEEDBACK IO_PD_5 /* package pin:147 */
#define IO_PIN_CONTACTOR_0_CONTROL IO_PI_2 /* package pin:133 */
#define IO_PIN_CONTACTOR_0_FEEDBACK IO_PH_13 /* package pin:128 */
#define IO_PIN_CONTACTOR_1_CONTROL IO_PI_1 /* package pin:132 */
#define IO_PIN_CONTACTOR_1_FEEDBACK IO_PH_14 /* package pin:129 */
#define IO_PIN_CONTACTOR_2_CONTROL IO_PI_0 /* package pin:131 */
#define IO_PIN_CONTACTOR_2_FEEDBACK IO_PH_15 /* package pin:130 */
#define IO_PIN_CONTACTOR_3_CONTROL IO_PA_9 /* package pin:120 */
#define IO_PIN_CONTACTOR_3_FEEDBACK IO_PC_6 /* package pin:115 */
#define IO_PIN_CONTACTOR_4_CONTROL IO_PA_8 /* package pin:119 */
#define IO_PIN_CONTACTOR_4_FEEDBACK IO_PC_7 /* package pin:116 */
#define IO_PIN_CONTACTOR_5_CONTROL IO_PC_9 /* package pin:118 */
#define IO_PIN_CONTACTOR_5_FEEDBACK IO_PC_8 /* package pin:117 */
#define IO_PIN_CONTACTOR_6_CONTROL IO_PC_10 /* package pin:139 */
#define IO_PIN_CONTACTOR_6_FEEDBACK IO_PC_11 /* package pin:140 */
#define IO_PIN_CONTACTOR_7_CONTROL IO_PD_2 /* package pin:144 */
#define IO_PIN_CONTACTOR_7_FEEDBACK IO_PB_6 /* package pin:164 */
#define IO_PIN_CONTACTOR_8_CONTROL IO_PH_3 /* package pin:44 */
#define IO_PIN_CONTACTOR_8_FEEDBACK IO_PH_4 /* package pin:45 */
/*
*Interfaces
*/
#define IO_PIN_BMS_INTERFACE_SPI_NSS IO_PA_4 /* package pin:50 */
#define IO_PIN_BMS_INTERFACE_SPI_SCK IO_PA_5 /* package pin:51 */
#define IO_PIN_BMS_INTERFACE_SPI_MISO IO_PA_6 /* package pin:52 */
#define IO_PIN_BMS_INTERFACE_SPI_MOSI IO_PA_7 /* package pin:53 */
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS IO_PB_12 /* package pin:92 */
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK IO_PD_3 /* package pin:145 */
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO IO_PB_14 /* package pin:94 */
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI IO_PB_15 /* package pin:95 */
#define IO_PIN_TO_FPGA_INTERFACE_SPI_NSS IO_PF_6 /* package pin:24 */
#define IO_PIN_TO_FPGA_INTERFACE_SPI_SCK IO_PF_7 /* package pin:25 */
#define IO_PIN_TO_FPGA_INTERFACE_SPI_MISO IO_PF_8 /* package pin:26 */
#define IO_PIN_TO_FPGA_INTERFACE_SPI_MOSI IO_PF_9 /* package pin:27 */
#define IO_PIN_CAN_0_TRANS_STANDBY_CONTROL IO_PC_12 /* package pin:141 */
#define IO_PIN_CAN_0_TX IO_PB_13 /* package pin:93 */
#define IO_PIN_CAN_0_RX IO_PB_5 /* package pin:163 */
#define IO_PIN_CAN_1_TRANS_STANDBY_CONTROL IO_PB_7 /* package pin:165 */
#define IO_PIN_CAN_1_RX IO_PB_8 /* package pin:167 */
#define IO_PIN_CAN_1_TX IO_PB_9 /* package pin:168 */
#define IO_PIN_FTDI_TX IO_PB_10 /* package pin:79 */
#define IO_PIN_FTDI_RX IO_PB_11 /* package pin:80 */
#define IO_PIN_RS485_NRE IO_PG_2 /* package pin:106 */
#define IO_PIN_RS485_DE IO_PG_3 /* package pin:107 */
#define IO_PIN_RS485_TX IO_PA_2 /* package pin:42 */
#define IO_PIN_RS485_RX IO_PD_6
#define IO_PIN_BMS_INTERFACE_0_GPIO_0 IO_PA_10 /* package pin:121 */
#define IO_PIN_BMS_INTERFACE_0_GPIO_1 IO_PA_11 /* package pin:122 */
#define IO_PIN_BMS_INTERFACE_0_GPIO_2 IO_PA_12 /* package pin:123 */
#define IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION IO_PB_4 /* package pin:162 */
/*
*Isolated In- and Outputs
*/
#define IO_PIN_ISO_GPIO_IN_0 IO_PD_12 /* package pin:152 */
#define IO_PIN_ISO_GPIO_OUT_0 IO_PG_9 /* package pin:100 */
#define IO_PIN_ISO_GPIO_IN_1 IO_PD_13 /* package pin:153 */
#define IO_PIN_ISO_GPIO_OUT_1 IO_PG_10 /* package pin:101 */
#define IO_PIN_ISO_GPIO_IN_2 IO_PG_11 /* package pin:174 */
#define IO_PIN_ISO_GPIO_OUT_2 IO_PI_5 /* package pin:154 */
#define IO_PIN_ISO_GPIO_IN_3 IO_PI_4 /* package pin:175 */
#define IO_PIN_ISO_GPIO_OUT_3 IO_PI_6 /* package pin:173 */
#define IO_PIN_ISONOC_0_CONTROL IO_PH_8 /* package pin:85 */
#define IO_PIN_ISONOC_1_CONTROL IO_PH_9 /* package pin:86 */
#define IO_PIN_ISONOC_2_CONTROL IO_PH_10 /* package pin:87 */
#define IO_PIN_ISONOC_3_CONTROL IO_PH_11 /* package pin:88 */
#define IO_PIN_ISONOC_4_CONTROL IO_PH_12 /* package pin:89 */
#define IO_PIN_ISONOC_5_CONTROL IO_PD_11 /* package pin:99 */
/*
*Special Pins
*/
/* VBATT package pin:6 */
/* RTC_XTAL IO_PC_14 package pin:9 */
/* RTC_XTAL IO_PC_15 package pin:10 */
/* XTAL IO_PH_0 package pin:29 */
/* XTAL IO_PH_1 package pin:30 */
/* NRST package pin:31 */
/* GNDA package pin:37 */
/* VREF+ package pin:38 */
/* VCCA package pin:39 */
/* Wakeup IO_PA_0 package pin:40 */
/* BOOT1 IO_PB_2 package pin:58 */
/* BYPASS_REG package pin:48 */
/* VCAP_1 package pin:81 */
/* SWDIO IO_PA_13 package pin:124 */
/* VCAP_2 package pin:125 */
/* SWCLK IO_PA_14 package pin:137 */
/* TDI IO_PA_15 package pin:138 */
/* SWO IO_PB_3 package pin:161 */
/* BOOT0 package pin:166 */
/* PDR_ON package pin:171 */
/*
*Ground Pins
*/
/* GND package pin:14 */
/* GND package pin:22 */
/* GND package pin:61 */
/* GND package pin:71 */
/* GND package pin:90 */
/* GND package pin:102 */
/* GND package pin:113 */
/* GND package pin:126 */
/* GND package pin:135 */
/* GND package pin:148 */
/* GND package pin:158 */
/*
*Supply Pins
*/
/* VCC package pin:15 */
/* VCC package pin:23 */
/* VCC package pin:36 */
/* VCC package pin:49 */
/* VCC package pin:62 */
/* VCC package pin:72 */
/* VCC package pin:82 */
/* VCC package pin:91 */
/* VCC package pin:103 */
/* VCC package pin:114 */
/* VCC package pin:127 */
/* VCC package pin:136 */
/* VCC package pin:149 */
/* VCC package pin:159 */
/* VCC package pin:172 */
/*
*Pins free to be used
*/
/* FREE FOR USAGE IO_PC_13 package pin:8 */
/* FREE FOR USAGE IO_PI_10 package pin:12 */
/* FREE FOR USAGE IO_PI_11 package pin:13 */
/* FREE FOR USAGE IO_PF_10 package pin:28 */
/* FREE FOR USAGE IO_PG_6 package pin:110 */
/* FREE FOR USAGE IO_PG_7 package pin:111 */
/* FREE FOR USAGE IO_PI_3 package pin:134 */
/* FREE FOR USAGE IO_PD_7 package pin:151 */
/* FREE FOR USAGE IO_PI_7 package pin:176 */
/*================== Constant and Variable Definitions ====================*/
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
#endif /* IO_MCU_CFG_H_ */
io_package_cfg.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_package_cfg.h
* @author foxBMS Team
* @date 07.10.2015 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO
*
* @brief configuration header of the io-module
*
* ==============================================================================
* Configuration of the GPIOs
* ==============================================================================
*
* The io_package_cfg.h assigns a name of each GPIO available on the specific
* package to a unique, ascending number starting 0, e.g. the first pin at the
* port A gets the name IO_PA_0 = 0, the second IO_PA_1 = 1, ... With this unique
* number for each pin it is possible to calculate from every pin name the
* corresponding port (by integer division) and corresponding pin (by modulo
* division).
*/
#ifndef IO_PACKAGE_CFG_H_
#define IO_PACKAGE_CFG_H_
/*================== Includes =============================================*/
/*================== Macros and Definitions ===============================*/
/**
* @ingroup CONFIG_IO
* Nr. of pins per port must always be set to 16
* \par Type:
* int
* \par Default:
* 16
*/
/**
* Number of pins per port at the microcontroller. This number is fixed.
*
*/
#define IO_NR_OF_PINS_PER_PORT 16
/**
* @ingroup CONFIG_IO
* specify the type of microcontroller used
*
* \par Type:
* switch (3)
* \par Default:
* 2
*/
/**
* Defines the used microcontroller package. The user can choose between
* - IO_PACKAGE_LQFP100
* - IO_PACKAGE_LQFP144
* - IO_PACKAGE_LQFP176
*
*/
/* #define IO_PACKAGE_LQFP100 */
/* #define IO_PACKAGE_LQFP144 */
#define IO_PACKAGE_LQFP176
/*================== Constant and Variable Definitions ====================*/
#if defined(IO_PACKAGE_LQFP100) || defined(IO_PACKAGE_LQFP144) || defined(IO_PACKAGE_LQFP176)
/**
* symbolic names of the pins at the microcontroller
*/
typedef enum {
IO_PA_0 = 0, /*!< Port A, Pin 0 */
IO_PA_1 = 1, /*!< Port A, Pin 1 */
IO_PA_2 = 2, /*!< Port A, Pin 2 */
IO_PA_3 = 3, /*!< Port A, Pin 3 */
IO_PA_4 = 4, /*!< Port A, Pin 4 */
IO_PA_5 = 5, /*!< Port A, Pin 5 */
IO_PA_6 = 6, /*!< Port A, Pin 6 */
IO_PA_7 = 7, /*!< Port A, Pin 7 */
IO_PA_8 = 8, /*!< Port A, Pin 8 */
IO_PA_9 = 9, /*!< Port A, Pin 9 */
IO_PA_10 = 10, /*!< Port A, Pin 10 */
IO_PA_11 = 11, /*!< Port A, Pin 11 */
IO_PA_12 = 12, /*!< Port A, Pin 12 */
IO_PA_13 = 13, /*!< Port A, Pin 13 */
IO_PA_14 = 14, /*!< Port A, Pin 14 */
IO_PA_15 = 15, /*!< Port A, Pin 15 */
IO_PB_0 = 16, /*!< Port B, Pin 0 */
IO_PB_1 = 17, /*!< Port B, Pin 1 */
IO_PB_2 = 18, /*!< Port B, Pin 2 */
IO_PB_3 = 19, /*!< Port B, Pin 3 */
IO_PB_4 = 20, /*!< Port B, Pin 4 */
IO_PB_5 = 21, /*!< Port B, Pin 5 */
IO_PB_6 = 22, /*!< Port B, Pin 6 */
IO_PB_7 = 23, /*!< Port B, Pin 7 */
IO_PB_8 = 24, /*!< Port B, Pin 8 */
IO_PB_9 = 25, /*!< Port B, Pin 9 */
IO_PB_10 = 26, /*!< Port B, Pin 10 */
IO_PB_11 = 27, /*!< Port B, Pin 11 */
IO_PB_12 = 28, /*!< Port B, Pin 12 */
IO_PB_13 = 29, /*!< Port B, Pin 13 */
IO_PB_14 = 30, /*!< Port B, Pin 14 */
IO_PB_15 = 31, /*!< Port B, Pin 15 */
IO_PC_0 = 32, /*!< Port C, Pin 0 */
IO_PC_1 = 33, /*!< Port C, Pin 1 */
IO_PC_2 = 34, /*!< Port C, Pin 2 */
IO_PC_3 = 35, /*!< Port C, Pin 3 */
IO_PC_4 = 36, /*!< Port C, Pin 4 */
IO_PC_5 = 37, /*!< Port C, Pin 5 */
IO_PC_6 = 38, /*!< Port C, Pin 6 */
IO_PC_7 = 39, /*!< Port C, Pin 7 */
IO_PC_8 = 40, /*!< Port C, Pin 8 */
IO_PC_9 = 41, /*!< Port C, Pin 9 */
IO_PC_10 = 42, /*!< Port C, Pin 10 */
IO_PC_11 = 43, /*!< Port C, Pin 11 */
IO_PC_12 = 44, /*!< Port C, Pin 12 */
IO_PC_13 = 45, /*!< Port C, Pin 13 */
IO_PC_14 = 46, /*!< Port C, Pin 14 */
IO_PC_15 = 47, /*!< Port C, Pin 15 */
IO_PD_0 = 48, /*!< Port D, Pin 0 */
IO_PD_1 = 49, /*!< Port D, Pin 1 */
IO_PD_2 = 50, /*!< Port D, Pin 2 */
IO_PD_3 = 51, /*!< Port D, Pin 3 */
IO_PD_4 = 52, /*!< Port D, Pin 4 */
IO_PD_5 = 53, /*!< Port D, Pin 5 */
IO_PD_6 = 54, /*!< Port D, Pin 6 */
IO_PD_7 = 55, /*!< Port D, Pin 7 */
IO_PD_8 = 56, /*!< Port D, Pin 8 */
IO_PD_9 = 57, /*!< Port D, Pin 9 */
IO_PD_10 = 58, /*!< Port D, Pin 10 */
IO_PD_11 = 59, /*!< Port D, Pin 11 */
IO_PD_12 = 60, /*!< Port D, Pin 12 */
IO_PD_13 = 61, /*!< Port D, Pin 13 */
IO_PD_14 = 62, /*!< Port D, Pin 14 */
IO_PD_15 = 63, /*!< Port D, Pin 15 */
IO_PE_0 = 64, /*!< Port E, Pin 0 */
IO_PE_1 = 65, /*!< Port E, Pin 1 */
IO_PE_2 = 66, /*!< Port E, Pin 2 */
IO_PE_3 = 67, /*!< Port E, Pin 3 */
IO_PE_4 = 68, /*!< Port E, Pin 4 */
IO_PE_5 = 69, /*!< Port E, Pin 5 */
IO_PE_6 = 70, /*!< Port E, Pin 6 */
IO_PE_7 = 71, /*!< Port E, Pin 7 */
IO_PE_8 = 72, /*!< Port E, Pin 8 */
IO_PE_9 = 73, /*!< Port E, Pin 9 */
IO_PE_10 = 74, /*!< Port E, Pin 10 */
IO_PE_11 = 75, /*!< Port E, Pin 11 */
IO_PE_12 = 76, /*!< Port E, Pin 12 */
IO_PE_13 = 77, /*!< Port E, Pin 13 */
IO_PE_14 = 78, /*!< Port E, Pin 14 */
IO_PE_15 = 79 /*!< Port E, Pin 15 */
#endif /* IO_PACKAGE_LQFP100 */
#if defined(IO_PACKAGE_LQFP144) || defined(IO_PACKAGE_LQFP176)
,
IO_PF_0 = 80, /*!< Port F, Pin 0 */
IO_PF_1 = 81, /*!< Port F, Pin 1 */
IO_PF_2 = 82, /*!< Port F, Pin 2 */
IO_PF_3 = 83, /*!< Port F, Pin 3 */
IO_PF_4 = 84, /*!< Port F, Pin 4 */
IO_PF_5 = 85, /*!< Port F, Pin 5 */
IO_PF_6 = 86, /*!< Port F, Pin 6 */
IO_PF_7 = 87, /*!< Port F, Pin 7 */
IO_PF_8 = 88, /*!< Port F, Pin 8 */
IO_PF_9 = 89, /*!< Port F, Pin 9 */
IO_PF_10 = 90, /*!< Port F, Pin 10 */
IO_PF_11 = 91, /*!< Port F, Pin 11 */
IO_PF_12 = 92, /*!< Port F, Pin 12 */
IO_PF_13 = 93, /*!< Port F, Pin 13 */
IO_PF_14 = 94, /*!< Port F, Pin 14 */
IO_PF_15 = 95, /*!< Port F, Pin 15 */
IO_PG_0 = 96, /*!< Port G, Pin 0 */
IO_PG_1 = 97, /*!< Port G, Pin 1 */
IO_PG_2 = 98, /*!< Port G, Pin 2 */
IO_PG_3 = 99, /*!< Port G, Pin 3 */
IO_PG_4 = 100, /*!< Port G, Pin 4 */
IO_PG_5 = 101, /*!< Port G, Pin 5 */
IO_PG_6 = 102, /*!< Port G, Pin 6 */
IO_PG_7 = 103, /*!< Port G, Pin 7 */
IO_PG_8 = 104, /*!< Port G, Pin 8 */
IO_PG_9 = 105, /*!< Port G, Pin 9 */
IO_PG_10 = 106, /*!< Port G, Pin 10 */
IO_PG_11 = 107, /*!< Port G, Pin 11 */
IO_PG_12 = 108, /*!< Port G, Pin 12 */
IO_PG_13 = 109, /*!< Port G, Pin 13 */
IO_PG_14 = 110, /*!< Port G, Pin 14 */
IO_PG_15 = 111, /*!< Port G, Pin 15 */
IO_PH_0 = 112, /*!< Port H, Pin 0 */
IO_PH_1 = 113 /*!< Port H, Pin 1 */
#endif /* IO_PACKAGE_LQFP144 */
#if defined(IO_PACKAGE_LQFP176)
,
IO_PH_2 = 114, /*!< Port H, Pin 2 */
IO_PH_3 = 115, /*!< Port H, Pin 3 */
IO_PH_4 = 116, /*!< Port H, Pin 4 */
IO_PH_5 = 117, /*!< Port H, Pin 5 */
IO_PH_6 = 118, /*!< Port H, Pin 6 */
IO_PH_7 = 119, /*!< Port H, Pin 7 */
IO_PH_8 = 120, /*!< Port H, Pin 8 */
IO_PH_9 = 121, /*!< Port H, Pin 9 */
IO_PH_10 = 122, /*!< Port H, Pin 10 */
IO_PH_11 = 123, /*!< Port H, Pin 11 */
IO_PH_12 = 124, /*!< Port H, Pin 12 */
IO_PH_13 = 125, /*!< Port H, Pin 13 */
IO_PH_14 = 126, /*!< Port H, Pin 14 */
IO_PH_15 = 127, /*!< Port H, Pin 15 */
IO_PI_0 = 128, /*!< Port I, Pin 0 */
IO_PI_1 = 129, /*!< Port I, Pin 1 */
IO_PI_2 = 130, /*!< Port I, Pin 2 */
IO_PI_3 = 131, /*!< Port I, Pin 3 */
IO_PI_4 = 132, /*!< Port I, Pin 4 */
IO_PI_5 = 133, /*!< Port I, Pin 5 */
IO_PI_6 = 134, /*!< Port I, Pin 6 */
IO_PI_7 = 135, /*!< Port I, Pin 7 */
IO_PI_8 = 136, /*!< Port I, Pin 8 */
IO_PI_9 = 137, /*!< Port I, Pin 9 */
IO_PI_10 = 138, /*!< Port I, Pin 10 */
IO_PI_11 = 139 /*!< Port I, Pin 11 */
#endif /* IO_PACKAGE_LQFP176 */
} IO_PORTS_e;
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
#endif /* IO_PACKAGE_CFG_H_ */
io_cfg.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_cfg.h
* @author foxBMS Team
* @date 26.08.2015 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO
*
* @brief Headers for the configuration for the driver for the I/O ports (pins).
*
* ==============================================================================
* Configuration of the GPIOs
* ==============================================================================
*
* Supported packages of the STM32F429
* ===================================
* In io_cfg.h the users defines the used package of the STM32F429 by a macro.
* The following table shows the package and its corresponding macro:
* Package | Macro
* --------| ------------------
* LQFP100 | IO_PACKAGE_LQFP100
* LQFP144 | IO_PACKAGE_LQFP144
* LQFP176 | IO_PACKAGE_LQFP176
*
* The global enable for locking of pin configuration is set (Macro IO_PIN_LOCKING).
* Enabling this macro allows to specify in a locking variable in io_cfg[] array in
* io_cfg.c.
*
*
*/
#ifndef IO_CFG_H_
#define IO_CFG_H_
/*================== Includes =============================================*/
#include "general.h"
#include "cpu_cfg.h"
#include "io_mcu_cfg.h"
/*================== Macros and Definitions ===============================*/
/**
* @ingroup CONFIG_IO
* description if port locking is enabled, one can specify in the
* io_cfg[] array each pin configuration as locked/unlocked.
* \par Type:
* toggle
* \par Default:
* True
*/
/**
* Enables pin locking globally. If this macro is not defined, pin locking
* can not be activated.
*/
/* #define IO_PIN_LOCKING */
/*================== Constant and Variable Definitions ====================*/
/**
* symbolic names for possible modes of the pins
*/
typedef enum {
IO_MODE_INPUT = GPIO_MODE_INPUT, /*!< The pin is used as input */
IO_MODE_OUTPUT_PP = GPIO_MODE_OUTPUT_PP, /*!< The pin is used as output with push-pull */
IO_MODE_OUTPUT_OD = GPIO_MODE_OUTPUT_OD, /*!< The pin is used as output with open-drain */
IO_MODE_AF_PP = GPIO_MODE_AF_PP, /*!< The pin is used as alternate function with push-pull */
IO_MODE_AF_OD = GPIO_MODE_AF_OD, /*!< The pin is used as alternate function with open-drain */
IO_MODE_ANALOG = GPIO_MODE_ANALOG, /*!< The pin is used as analog pin */
IO_MODE_IT_RISING = GPIO_MODE_IT_RISING, /*!< The pin is used as interrupt at rising edge */
IO_MODE_IT_FALLING = GPIO_MODE_IT_FALLING, /*!< The pin is used as interrupt at falling edge */
IO_MODE_IT_RISING_FALLING = GPIO_MODE_IT_RISING_FALLING, /*!< The pin is used as interrupt at rising/falling edge */
IO_MODE_EVT_RISING = GPIO_MODE_EVT_RISING, /*!< The pin is used as event mode at rising edge */
IO_MODE_EVT_FALLLING = GPIO_MODE_EVT_FALLING, /*!< The pin is used as event mode at falling edge */
IO_MODE_EVT_RISING_FALLING = GPIO_MODE_EVT_RISING_FALLING /*!< The pin is used as event mode at rising/falling edge */
} IO_PIN_MODES_e;
/**
* symbolic names for possible speeds of the pins
*/
typedef enum {
IO_SPEED_LOW = GPIO_SPEED_LOW, /*!< The pin speed is low */
IO_SPEED_MEDIUM = GPIO_SPEED_MEDIUM, /*!< The pin speed is medium */
IO_SPEED_FAST = GPIO_SPEED_FAST, /*!< The pin speed is fast */
IO_SPEED_HIGH = GPIO_SPEED_HIGH /*!< The pin speed is high */
} IO_PIN_SPEEDS_e;
/**
* symbolic names for possible pull-up or pull-downs of the pins
*/
typedef enum {
IO_PIN_NOPULL = GPIO_NOPULL, /*!< Whether pull-up nor pull-down is activated */
IO_PIN_PULLUP = GPIO_PULLUP, /*!< Pull-up is activated */
IO_PIN_PULLDOWN = GPIO_PULLDOWN /*!< Pull-down is activated */
} IO_PIN_PULL_e;
/**
* symbolic names for possible alternate functions of the pins
*/
typedef enum {
IO_ALTERNATE_AF0_RTC_50Hz = GPIO_AF0_RTC_50Hz, /*!< Real-time Clock 50Hz */
IO_ALTERNATE_AF0_MCO = GPIO_AF0_MCO, /*!< Microcontroller clock output, (MCO1 and MCO2) */
IO_ALTERNATE_AF0_SWJ = GPIO_AF0_SWJ, /*!< Serial Wire Debug or JTAG */
IO_ALTERNATE_AF0_TRACE = GPIO_AF0_TRACE, /*!< Trace */
IO_ALTERNATE_AF1_TIM1 = GPIO_AF1_TIM1, /*!< TIM1 */
IO_ALTERNATE_AF1_TIM2 = GPIO_AF1_TIM2, /*!< TIM2 */
IO_ALTERNATE_AF2_TIM3 = GPIO_AF2_TIM3, /*!< TIM3 */
IO_ALTERNATE_AF2_TIM4 = GPIO_AF2_TIM4, /*!< TIM4 */
IO_ALTERNATE_AF2_TIM5 = GPIO_AF2_TIM5, /*!< TIM5 */
IO_ALTERNATE_AF3_TIM8 = GPIO_AF3_TIM8, /*!< TIM8 */
IO_ALTERNATE_AF3_TIM9 = GPIO_AF3_TIM9, /*!< TIM9 */
IO_ALTERNATE_AF3_TIM10 = GPIO_AF3_TIM10, /*!< TIM10 */
IO_ALTERNATE_AF3_TIM11 = GPIO_AF3_TIM11, /*!< TIM11 */
IO_ALTERNATE_AF4_I2C1 = GPIO_AF4_I2C1, /*!< Inter-Integrated Circuit Bus 1 */
IO_ALTERNATE_AF4_I2C2 = GPIO_AF4_I2C2, /*!< Inter-Integrated Circuit Bus 2 */
IO_ALTERNATE_AF4_I2C3 = GPIO_AF4_I2C3, /*!< Inter-Integrated Circuit Bus 3 */
IO_ALTERNATE_AF5_SPI1 = GPIO_AF5_SPI1, /*!< Serial Peripheral Interface Bus 1 */
IO_ALTERNATE_AF5_SPI2 = GPIO_AF5_SPI2, /*!< Serial Peripheral Interface Bus 2 */
IO_ALTERNATE_AF5_SPI3 = GPIO_AF5_SPI3, /*!< Serial Peripheral Interface Bus 3 */
IO_ALTERNATE_AF5_SPI4 = GPIO_AF5_SPI4, /*!< Serial Peripheral Interface Bus 4 */
IO_ALTERNATE_AF5_SPI5 = GPIO_AF5_SPI5, /*!< Serial Peripheral Interface Bus 5 */
IO_ALTERNATE_AF5_SPI6 = GPIO_AF5_SPI6, /*!< Serial Peripheral Interface Bus 6 */
IO_ALTERNATE_AF6_SPI3 = GPIO_AF6_SPI3, /*!< Serial Peripheral Interface Bus 3 */
IO_ALTERNATE_AF6_SAI1 = GPIO_AF6_SAI1, /*!< Serial Audio Interface 1 */
IO_ALTERNATE_AF7_USART1 = GPIO_AF7_USART1, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 1 */
IO_ALTERNATE_AF7_USART2 = GPIO_AF7_USART2, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 2 */
IO_ALTERNATE_AF7_USART3 = GPIO_AF7_USART3, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 3 */
IO_ALTERNATE_AF8_UART4 = GPIO_AF8_UART4, /*!< Universal Asynchronous Receiver Transmitter 4 */
IO_ALTERNATE_AF8_UART5 = GPIO_AF8_UART5, /*!< Universal Asynchronous Receiver Transmitter 5 */
IO_ALTERNATE_AF8_USART6 = GPIO_AF8_USART6, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 6 */
IO_ALTERNATE_AF8_UART7 = GPIO_AF8_UART7, /*!< Universal Asynchronous Receiver Transmitter 3 */
IO_ALTERNATE_AF8_UART8 = GPIO_AF8_UART8, /*!< Universal Asynchronous Receiver Transmitter 3 */
IO_ALTERNATE_AF9_CAN1 = GPIO_AF9_CAN1, /*!< Controller Area Network Bus 1 */
IO_ALTERNATE_AF9_CAN0 = GPIO_AF9_CAN2, /*!< Controller Area Network Bus 2 */
IO_ALTERNATE_AF9_TIM12 = GPIO_AF9_TIM12, /*!< TIM12 */
IO_ALTERNATE_AF9_TIM13 = GPIO_AF9_TIM13, /*!< TIM13 */
IO_ALTERNATE_AF9_TIM14 = GPIO_AF9_TIM14, /*!< TIM14 */
IO_ALTERNATE_AF10_OTG_FS = GPIO_AF10_OTG_FS, /*!< USB On-the-go FS */
IO_ALTERNATE_AF10_OTG_HS = GPIO_AF10_OTG_HS, /*!< USB On-the-go HS */
IO_ALTERNATE_AF11_ETH = GPIO_AF11_ETH, /*!< Ethernet */
IO_ALTERNATE_AF12_FMC = GPIO_AF12_FMC, /*!< Flexible Memory Controller */
IO_ALTERNATE_AF12_OTG_HS_FS = GPIO_AF12_OTG_HS_FS, /*!< USB On-the-go HS/FS */
IO_ALTERNATE_AF12_SDIO = GPIO_AF12_SDIO, /*!< Secure Digital Memory Card */
IO_ALTERNATE_AF13_DCMI = GPIO_AF13_DCMI, /*!< Digital Camera Memory Interface */
IO_ALTERNATE_AF15_EVENTOUT = GPIO_AF15_EVENTOUT, /*!< Eventout */
IO_ALTERNATE_NO_ALTERNATE = 0xFF /*!< No alternate function */
} IO_PIN_ALTERNATE_e;
/**
* symbolic names for enabling/disabling pin locking at certain pin
*/
typedef enum {
IO_PIN_LOCK_DISABLE = 0, /*!< Disable configuration locking */
IO_PIN_LOCK_ENABLE = 1, /*!< Enable configuration locking */
} IO_PIN_LOCK_e;
/**
* symbolic names for pin state, where reset means low, and set means high
*/
typedef enum {
IO_PIN_RESET = GPIO_PIN_RESET, /*!< Pin is set to low/0 */
IO_PIN_SET = GPIO_PIN_SET, /*!< Pin is set to high/1 */
IO_PIN_DC = GPIO_PIN_RESET, /*!< default value for Pin (don't care) */
} IO_PIN_STATE_e;
/**
* symbolic names for status returned by the HAL
*/
typedef enum {
IO_HAL_STATUS_OK = HAL_OK, /*!< HAL ok */
IO_HAL_STATUS_ERROR = HAL_ERROR, /*!< HAL error */
IO_HAL_STATUS_BUSY = HAL_BUSY, /*!< HAL busy */
IO_HAL_STATUS_TIMEOUT = HAL_TIMEOUT /*!< HAL timeout */
} IO_HAL_STATUS_e;
/**
* struct for the initialization configuration of a pin
*/
typedef struct {
IO_PORTS_e pin; /*!< The pin to be configured defined by its symbolic name */
IO_PIN_MODES_e mode; /*!< The mode in which the pin will be used defined by its symbolic name */
IO_PIN_PULL_e pinpull; /*!< The speed at which the pin will be driven defined by its symbolic name */
IO_PIN_SPEEDS_e speed; /*!< The speed at which the pin will be driven defined by its symbolic name */
IO_PIN_ALTERNATE_e alternate; /*!< The alternate function the pin uses defined by its symbolic name */
IO_PIN_LOCK_e pinlock; /*!< Enable or disable pin locking. The macro IO_PIN_LOCKING has to be set */
IO_PIN_STATE_e initvalue; /*!< Set the pin high or low at the pin initialization. Default is low. */
} IO_PIN_CFG_s;
/**
* array for the initialization of the pins of the microcontroller
*/
extern const IO_PIN_CFG_s io_cfg[];
/**
* length of the array for the initialization of the pins of the
* microcontroller
*/
extern const uint8_t io_cfg_length;
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
#endif /* IO_CFG_H_ */
io_cfg.c¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_cfg.c
* @author foxBMS Team
* @date 26.08.2015 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO
*
* @brief Configuration for the driver for the I/O ports
*
* ==============================================================================
* Detailed Configuration of the GPIOs
* ==============================================================================
*
* The functionality of the signal defined in io_foxbms_mcu0_cfg.h is set in the array
* io_cfg[], e.g. digital I/O or alternate functions like SPI, CAN, ...
*
* An incorrect definition of an signal may disturb one or more other
* signal functional definitions of pins
*
* Every entry of the io_cfg[] array consists of
* - name of the signal/pin (defined in io_foxbms_mcu0_cfg.h)
* - mode of signal/pin (input, output, ...)
* - push/pull
* - pin speed
* - alternate function (SPI, CAN, ...)
* - locking of the pin configuration (has to enabled in io_cfg.h)
* All available possibilities for each pin are found in the official<a href"http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00071990.pdf">datasheet</a>.
*
*/
/*================== Includes =============================================*/
#include "io_cfg.h"
/*================== Macros and Definitions ===============================*/
/*================== Constant and Variable Definitions ====================*/
const IO_PIN_CFG_s io_cfg[] = {
/*
* Trace
*/
{IO_PIN_TRACECLK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED0, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED1, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED2, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TRACED3, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_AF0_TRACE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
/*
* Debug LEDs
*/
{IO_PIN_DEBUG_LED_1, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_DEBUG_LED_0, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
/*
* Contactors' Controll and Feedback Pins
*/
{IO_PIN_INTERLOCK_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_INTERLOCK_FEEDBACK, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
/*
* Interfaces
*/
{IO_PIN_BMS_INTERFACE_SPI_NSS, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_BMS_INTERFACE_SPI_SCK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BMS_INTERFACE_SPI_MISO, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BMS_INTERFACE_SPI_MOSI, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF5_SPI1, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_BMS_INTERFACE_0_GPIO_0, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_BMS_INTERFACE_0_GPIO_1, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_BMS_INTERFACE_0_GPIO_2, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
/* Pin high -> forward mode, Pin low -> reverse mode */
{IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_SET},
{IO_PIN_GPIO_0, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_GPIO_1, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_GPIO_2, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_GPIO_3, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_GPIO_4, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_GPIO_5, IO_MODE_INPUT, IO_PIN_PULLDOWN, IO_SPEED_FAST, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_DC},
{IO_PIN_CAN_0_TRANS_STANDBY_CONTROL, IO_MODE_OUTPUT_PP, IO_PIN_NOPULL, IO_SPEED_LOW, IO_ALTERNATE_NO_ALTERNATE, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_0_TX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF9_CAN0, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_CAN_0_RX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF9_CAN0, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_FTDI_TX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF7_USART3, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
{IO_PIN_FTDI_RX, IO_MODE_AF_PP, IO_PIN_NOPULL, IO_SPEED_HIGH, IO_ALTERNATE_AF7_USART3, IO_PIN_LOCK_ENABLE, IO_PIN_RESET},
};
const uint8_t io_cfg_length = sizeof(io_cfg)/sizeof(io_cfg[0]);
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
io_cfg.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_cfg.h
* @author foxBMS Team
* @date 26.08.2015 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO
*
* @brief Headers for the configuration for the driver for the I/O ports (pins).
*
* ==============================================================================
* Configuration of the GPIOs
* ==============================================================================
*
* Supported packages of the STM32F429
* ===================================
* In io_cfg.h the users defines the used package of the STM32F429 by a macro.
* The following table shows the package and its corresponding macro:
* Package | Macro
* --------| ------------------
* LQFP100 | IO_PACKAGE_LQFP100
* LQFP144 | IO_PACKAGE_LQFP144
* LQFP176 | IO_PACKAGE_LQFP176
*
* The global enable for locking of pin configuration is set (Macro IO_PIN_LOCKING).
* Enabling this macro allows to specify in a locking variable in io_cfg[] array in
* io_cfg.c.
*
*
*/
#ifndef IO_CFG_H_
#define IO_CFG_H_
/*================== Includes =============================================*/
#include "general.h"
#include "cpu_cfg.h"
#include "io_mcu_cfg.h"
/*================== Macros and Definitions ===============================*/
/**
* @ingroup CONFIG_IO
* description if port locking is enabled, one can specify in the
* io_cfg[] array each pin configuration as locked/unlocked.
* \par Type:
* toggle
* \par Default:
* True
*/
/**
* Enables pin locking globally. If this macro is not defined, pin locking
* can not be activated.
*/
/* #define IO_PIN_LOCKING */
/*================== Constant and Variable Definitions ====================*/
/**
* symbolic names for possible modes of the pins
*/
typedef enum {
IO_MODE_INPUT = GPIO_MODE_INPUT, /*!< The pin is used as input */
IO_MODE_OUTPUT_PP = GPIO_MODE_OUTPUT_PP, /*!< The pin is used as output with push-pull */
IO_MODE_OUTPUT_OD = GPIO_MODE_OUTPUT_OD, /*!< The pin is used as output with open-drain */
IO_MODE_AF_PP = GPIO_MODE_AF_PP, /*!< The pin is used as alternate function with push-pull */
IO_MODE_AF_OD = GPIO_MODE_AF_OD, /*!< The pin is used as alternate function with open-drain */
IO_MODE_ANALOG = GPIO_MODE_ANALOG, /*!< The pin is used as analog pin */
IO_MODE_IT_RISING = GPIO_MODE_IT_RISING, /*!< The pin is used as interrupt at rising edge */
IO_MODE_IT_FALLING = GPIO_MODE_IT_FALLING, /*!< The pin is used as interrupt at falling edge */
IO_MODE_IT_RISING_FALLING = GPIO_MODE_IT_RISING_FALLING, /*!< The pin is used as interrupt at rising/falling edge */
IO_MODE_EVT_RISING = GPIO_MODE_EVT_RISING, /*!< The pin is used as event mode at rising edge */
IO_MODE_EVT_FALLLING = GPIO_MODE_EVT_FALLING, /*!< The pin is used as event mode at falling edge */
IO_MODE_EVT_RISING_FALLING = GPIO_MODE_EVT_RISING_FALLING /*!< The pin is used as event mode at rising/falling edge */
} IO_PIN_MODES_e;
/**
* symbolic names for possible speeds of the pins
*/
typedef enum {
IO_SPEED_LOW = GPIO_SPEED_LOW, /*!< The pin speed is low */
IO_SPEED_MEDIUM = GPIO_SPEED_MEDIUM, /*!< The pin speed is medium */
IO_SPEED_FAST = GPIO_SPEED_FAST, /*!< The pin speed is fast */
IO_SPEED_HIGH = GPIO_SPEED_HIGH /*!< The pin speed is high */
} IO_PIN_SPEEDS_e;
/**
* symbolic names for possible pull-up or pull-downs of the pins
*/
typedef enum {
IO_PIN_NOPULL = GPIO_NOPULL, /*!< Whether pull-up nor pull-down is activated */
IO_PIN_PULLUP = GPIO_PULLUP, /*!< Pull-up is activated */
IO_PIN_PULLDOWN = GPIO_PULLDOWN /*!< Pull-down is activated */
} IO_PIN_PULL_e;
/**
* symbolic names for possible alternate functions of the pins
*/
typedef enum {
IO_ALTERNATE_AF0_RTC_50Hz = GPIO_AF0_RTC_50Hz, /*!< Real-time Clock 50Hz */
IO_ALTERNATE_AF0_MCO = GPIO_AF0_MCO, /*!< Microcontroller clock output, (MCO1 and MCO2) */
IO_ALTERNATE_AF0_SWJ = GPIO_AF0_SWJ, /*!< Serial Wire Debug or JTAG */
IO_ALTERNATE_AF0_TRACE = GPIO_AF0_TRACE, /*!< Trace */
IO_ALTERNATE_AF1_TIM1 = GPIO_AF1_TIM1, /*!< TIM1 */
IO_ALTERNATE_AF1_TIM2 = GPIO_AF1_TIM2, /*!< TIM2 */
IO_ALTERNATE_AF2_TIM3 = GPIO_AF2_TIM3, /*!< TIM3 */
IO_ALTERNATE_AF2_TIM4 = GPIO_AF2_TIM4, /*!< TIM4 */
IO_ALTERNATE_AF2_TIM5 = GPIO_AF2_TIM5, /*!< TIM5 */
IO_ALTERNATE_AF3_TIM8 = GPIO_AF3_TIM8, /*!< TIM8 */
IO_ALTERNATE_AF3_TIM9 = GPIO_AF3_TIM9, /*!< TIM9 */
IO_ALTERNATE_AF3_TIM10 = GPIO_AF3_TIM10, /*!< TIM10 */
IO_ALTERNATE_AF3_TIM11 = GPIO_AF3_TIM11, /*!< TIM11 */
IO_ALTERNATE_AF4_I2C1 = GPIO_AF4_I2C1, /*!< Inter-Integrated Circuit Bus 1 */
IO_ALTERNATE_AF4_I2C2 = GPIO_AF4_I2C2, /*!< Inter-Integrated Circuit Bus 2 */
IO_ALTERNATE_AF4_I2C3 = GPIO_AF4_I2C3, /*!< Inter-Integrated Circuit Bus 3 */
IO_ALTERNATE_AF5_SPI1 = GPIO_AF5_SPI1, /*!< Serial Peripheral Interface Bus 1 */
IO_ALTERNATE_AF5_SPI2 = GPIO_AF5_SPI2, /*!< Serial Peripheral Interface Bus 2 */
IO_ALTERNATE_AF5_SPI3 = GPIO_AF5_SPI3, /*!< Serial Peripheral Interface Bus 3 */
IO_ALTERNATE_AF5_SPI4 = GPIO_AF5_SPI4, /*!< Serial Peripheral Interface Bus 4 */
IO_ALTERNATE_AF5_SPI5 = GPIO_AF5_SPI5, /*!< Serial Peripheral Interface Bus 5 */
IO_ALTERNATE_AF5_SPI6 = GPIO_AF5_SPI6, /*!< Serial Peripheral Interface Bus 6 */
IO_ALTERNATE_AF6_SPI3 = GPIO_AF6_SPI3, /*!< Serial Peripheral Interface Bus 3 */
IO_ALTERNATE_AF6_SAI1 = GPIO_AF6_SAI1, /*!< Serial Audio Interface 1 */
IO_ALTERNATE_AF7_USART1 = GPIO_AF7_USART1, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 1 */
IO_ALTERNATE_AF7_USART2 = GPIO_AF7_USART2, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 2 */
IO_ALTERNATE_AF7_USART3 = GPIO_AF7_USART3, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 3 */
IO_ALTERNATE_AF8_UART4 = GPIO_AF8_UART4, /*!< Universal Asynchronous Receiver Transmitter 4 */
IO_ALTERNATE_AF8_UART5 = GPIO_AF8_UART5, /*!< Universal Asynchronous Receiver Transmitter 5 */
IO_ALTERNATE_AF8_USART6 = GPIO_AF8_USART6, /*!< Universal Synchronous/Asynchronous Receiver Transmitter 6 */
IO_ALTERNATE_AF8_UART7 = GPIO_AF8_UART7, /*!< Universal Asynchronous Receiver Transmitter 3 */
IO_ALTERNATE_AF8_UART8 = GPIO_AF8_UART8, /*!< Universal Asynchronous Receiver Transmitter 3 */
IO_ALTERNATE_AF9_CAN1 = GPIO_AF9_CAN1, /*!< Controller Area Network Bus 1 */
IO_ALTERNATE_AF9_CAN0 = GPIO_AF9_CAN2, /*!< Controller Area Network Bus 2 */
IO_ALTERNATE_AF9_TIM12 = GPIO_AF9_TIM12, /*!< TIM12 */
IO_ALTERNATE_AF9_TIM13 = GPIO_AF9_TIM13, /*!< TIM13 */
IO_ALTERNATE_AF9_TIM14 = GPIO_AF9_TIM14, /*!< TIM14 */
IO_ALTERNATE_AF10_OTG_FS = GPIO_AF10_OTG_FS, /*!< USB On-the-go FS */
IO_ALTERNATE_AF10_OTG_HS = GPIO_AF10_OTG_HS, /*!< USB On-the-go HS */
IO_ALTERNATE_AF11_ETH = GPIO_AF11_ETH, /*!< Ethernet */
IO_ALTERNATE_AF12_FMC = GPIO_AF12_FMC, /*!< Flexible Memory Controller */
IO_ALTERNATE_AF12_OTG_HS_FS = GPIO_AF12_OTG_HS_FS, /*!< USB On-the-go HS/FS */
IO_ALTERNATE_AF12_SDIO = GPIO_AF12_SDIO, /*!< Secure Digital Memory Card */
IO_ALTERNATE_AF13_DCMI = GPIO_AF13_DCMI, /*!< Digital Camera Memory Interface */
IO_ALTERNATE_AF15_EVENTOUT = GPIO_AF15_EVENTOUT, /*!< Eventout */
IO_ALTERNATE_NO_ALTERNATE = 0xFF /*!< No alternate function */
} IO_PIN_ALTERNATE_e;
/**
* symbolic names for enabling/disabling pin locking at certain pin
*/
typedef enum {
IO_PIN_LOCK_DISABLE = 0, /*!< Disable configuration locking */
IO_PIN_LOCK_ENABLE = 1, /*!< Enable configuration locking */
} IO_PIN_LOCK_e;
/**
* symbolic names for pin state, where reset means low, and set means high
*/
typedef enum {
IO_PIN_RESET = GPIO_PIN_RESET, /*!< Pin is set to low/0 */
IO_PIN_SET = GPIO_PIN_SET, /*!< Pin is set to high/1 */
IO_PIN_DC = GPIO_PIN_RESET, /*!< default value for Pin (don't care) */
} IO_PIN_STATE_e;
/**
* symbolic names for status returned by the HAL
*/
typedef enum {
IO_HAL_STATUS_OK = HAL_OK, /*!< HAL ok */
IO_HAL_STATUS_ERROR = HAL_ERROR, /*!< HAL error */
IO_HAL_STATUS_BUSY = HAL_BUSY, /*!< HAL busy */
IO_HAL_STATUS_TIMEOUT = HAL_TIMEOUT /*!< HAL timeout */
} IO_HAL_STATUS_e;
/**
* struct for the initialization configuration of a pin
*/
typedef struct {
IO_PORTS_e pin; /*!< The pin to be configured defined by its symbolic name */
IO_PIN_MODES_e mode; /*!< The mode in which the pin will be used defined by its symbolic name */
IO_PIN_PULL_e pinpull; /*!< The speed at which the pin will be driven defined by its symbolic name */
IO_PIN_SPEEDS_e speed; /*!< The speed at which the pin will be driven defined by its symbolic name */
IO_PIN_ALTERNATE_e alternate; /*!< The alternate function the pin uses defined by its symbolic name */
IO_PIN_LOCK_e pinlock; /*!< Enable or disable pin locking. The macro IO_PIN_LOCKING has to be set */
IO_PIN_STATE_e initvalue; /*!< Set the pin high or low at the pin initialization. Default is low. */
} IO_PIN_CFG_s;
/**
* array for the initialization of the pins of the microcontroller
*/
extern const IO_PIN_CFG_s io_cfg[];
/**
* length of the array for the initialization of the pins of the
* microcontroller
*/
extern const uint8_t io_cfg_length;
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
#endif /* IO_CFG_H_ */
io_mcu_cfg.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_mcu_cfg.h
* @author foxBMS Team
* @date 18.01.2016 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO_PIN_MCU_1
*
* @brief Configuration for the I/O ports for MCU1 (secondary).
*
* This file describes the names of the signals connected
* to the given hardware pin at the cpu.
*
*/
#ifndef IO_MCU_CFG_H_
#define IO_MCU_CFG_H_
/*================== Includes =============================================*/
#include "io_package_cfg.h"
/*================== Macros and Definitions ===============================*/
/*
*Trace
*/
#define IO_PIN_TRACECLK IO_PE_2
#define IO_PIN_TRACED0 IO_PE_3
#define IO_PIN_TRACED1 IO_PE_4
#define IO_PIN_TRACED2 IO_PE_5
#define IO_PIN_TRACED3 IO_PE_6
/*
*Debug LEDs
*/
#define IO_PIN_DEBUG_LED_1 IO_PC_2
#define IO_PIN_DEBUG_LED_0 IO_PC_3
/*
*Interfaces
*/
#define IO_PIN_BMS_INTERFACE_SPI_NSS IO_PA_4
#define IO_PIN_BMS_INTERFACE_SPI_SCK IO_PA_5
#define IO_PIN_BMS_INTERFACE_SPI_MISO IO_PA_6
#define IO_PIN_BMS_INTERFACE_SPI_MOSI IO_PA_7
#define IO_PIN_FTDI_TX IO_PB_10
#define IO_PIN_FTDI_RX IO_PB_11
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_NSS IO_PB_12
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_SCK IO_PD_3
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MOSI IO_PB_14
#define IO_PIN_TO_OTHER_MCU_INTERFACE_SPI_MISO IO_PB_15
/*
*Interlock and Feedback Pins
*/
#define IO_PIN_INTERLOCK_CONTROL IO_PD_4
#define IO_PIN_INTERLOCK_FEEDBACK IO_PD_5
/*
*Interfaces
*/
#define IO_PIN_CAN_0_TRANS_STANDBY_CONTROL IO_PC_12
#define IO_PIN_CAN_0_TX IO_PB_13
#define IO_PIN_CAN_0_RX IO_PB_5
#define IO_PIN_BMS_INTERFACE_0_GPIO_0 IO_PA_10
#define IO_PIN_BMS_INTERFACE_0_GPIO_1 IO_PA_11
#define IO_PIN_BMS_INTERFACE_0_GPIO_2 IO_PA_12
#define IO_PIN_BMS_INTERFACE_ISOSPI_DIRECTION IO_PB_4
#define IO_PIN_GPIO_0 IO_PD_2
#define IO_PIN_GPIO_1 IO_PD_1
#define IO_PIN_GPIO_2 IO_PD_0
#define IO_PIN_GPIO_3 IO_PC_12
#define IO_PIN_GPIO_4 IO_PC_11
#define IO_PIN_GPIO_5 IO_PC_10
/*================== Constant and Variable Definitions ====================*/
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
#endif /* IO_MCU_CFG_H_ */
io_package_cfg.h¶
/**
*
* @copyright © 2010 - 2020, Fraunhofer-Gesellschaft zur Foerderung der
* angewandten Forschung e.V. All rights reserved.
*
* BSD 3-Clause License
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* We kindly request you to use one or more of the following phrases to refer
* to foxBMS in your hardware, software, documentation or advertising
* materials:
*
* ″This product uses parts of foxBMS®″
*
* ″This product includes parts of foxBMS®″
*
* ″This product is derived from foxBMS®″
*
*/
/**
* @file io_package_cfg.h
* @author foxBMS Team
* @date 07.10.2015 (date of creation)
* @ingroup DRIVERS_CONF
* @prefix IO
*
* @brief configuration header of the io-module
*
* ==============================================================================
* Configuration of the GPIOs
* ==============================================================================
*
* The io_package_cfg.h assigns a name of each GPIO available on the specific
* package to a unique, ascending number starting 0, e.g. the first pin at the
* port A gets the name IO_PA_0 = 0, the second IO_PA_1 = 1, ... With this unique
* number for each pin it is possible to calculate from every pin name the
* corresponding port (by integer division) and corresponding pin (by modulo
* division).
*/
#ifndef IO_PACKAGE_CFG_H_
#define IO_PACKAGE_CFG_H_
/*================== Includes =============================================*/
/*================== Macros and Definitions ===============================*/
/**
* @ingroup CONFIG_IO
* Nr. of pins per port must always be set to 16
* \par Type:
* int
* \par Default:
* 16
*/
/**
* Number of pins per port at the microcontroller. This number is fixed.
*
*/
#define IO_NR_OF_PINS_PER_PORT 16
/**
* @ingroup CONFIG_IO
* specify the type of microcontroller used
*
* \par Type:
* switch (3)
* \par Default:
* 2
*/
/**
* Defines the used microcontroller package. The user can choose between
* - IO_PACKAGE_LQFP100
* - IO_PACKAGE_LQFP144
* - IO_PACKAGE_LQFP176
*
*/
#define IO_PACKAGE_LQFP100
/* #define IO_PACKAGE_LQFP144 */
/* #define IO_PACKAGE_LQFP176 */
/*================== Constant and Variable Definitions ====================*/
#if defined(IO_PACKAGE_LQFP100) || defined(IO_PACKAGE_LQFP144) || defined(IO_PACKAGE_LQFP176)
/**
* symbolic names of the pins at the microcontroller
*/
typedef enum {
IO_PA_0 = 0, /*!< Port A, Pin 0 */
IO_PA_1 = 1, /*!< Port A, Pin 1 */
IO_PA_2 = 2, /*!< Port A, Pin 2 */
IO_PA_3 = 3, /*!< Port A, Pin 3 */
IO_PA_4 = 4, /*!< Port A, Pin 4 */
IO_PA_5 = 5, /*!< Port A, Pin 5 */
IO_PA_6 = 6, /*!< Port A, Pin 6 */
IO_PA_7 = 7, /*!< Port A, Pin 7 */
IO_PA_8 = 8, /*!< Port A, Pin 8 */
IO_PA_9 = 9, /*!< Port A, Pin 9 */
IO_PA_10 = 10, /*!< Port A, Pin 10 */
IO_PA_11 = 11, /*!< Port A, Pin 11 */
IO_PA_12 = 12, /*!< Port A, Pin 12 */
IO_PA_13 = 13, /*!< Port A, Pin 13 */
IO_PA_14 = 14, /*!< Port A, Pin 14 */
IO_PA_15 = 15, /*!< Port A, Pin 15 */
IO_PB_0 = 16, /*!< Port B, Pin 0 */
IO_PB_1 = 17, /*!< Port B, Pin 1 */
IO_PB_2 = 18, /*!< Port B, Pin 2 */
IO_PB_3 = 19, /*!< Port B, Pin 3 */
IO_PB_4 = 20, /*!< Port B, Pin 4 */
IO_PB_5 = 21, /*!< Port B, Pin 5 */
IO_PB_6 = 22, /*!< Port B, Pin 6 */
IO_PB_7 = 23, /*!< Port B, Pin 7 */
IO_PB_8 = 24, /*!< Port B, Pin 8 */
IO_PB_9 = 25, /*!< Port B, Pin 9 */
IO_PB_10 = 26, /*!< Port B, Pin 10 */
IO_PB_11 = 27, /*!< Port B, Pin 11 */
IO_PB_12 = 28, /*!< Port B, Pin 12 */
IO_PB_13 = 29, /*!< Port B, Pin 13 */
IO_PB_14 = 30, /*!< Port B, Pin 14 */
IO_PB_15 = 31, /*!< Port B, Pin 15 */
IO_PC_0 = 32, /*!< Port C, Pin 0 */
IO_PC_1 = 33, /*!< Port C, Pin 1 */
IO_PC_2 = 34, /*!< Port C, Pin 2 */
IO_PC_3 = 35, /*!< Port C, Pin 3 */
IO_PC_4 = 36, /*!< Port C, Pin 4 */
IO_PC_5 = 37, /*!< Port C, Pin 5 */
IO_PC_6 = 38, /*!< Port C, Pin 6 */
IO_PC_7 = 39, /*!< Port C, Pin 7 */
IO_PC_8 = 40, /*!< Port C, Pin 8 */
IO_PC_9 = 41, /*!< Port C, Pin 9 */
IO_PC_10 = 42, /*!< Port C, Pin 10 */
IO_PC_11 = 43, /*!< Port C, Pin 11 */
IO_PC_12 = 44, /*!< Port C, Pin 12 */
IO_PC_13 = 45, /*!< Port C, Pin 13 */
IO_PC_14 = 46, /*!< Port C, Pin 14 */
IO_PC_15 = 47, /*!< Port C, Pin 15 */
IO_PD_0 = 48, /*!< Port D, Pin 0 */
IO_PD_1 = 49, /*!< Port D, Pin 1 */
IO_PD_2 = 50, /*!< Port D, Pin 2 */
IO_PD_3 = 51, /*!< Port D, Pin 3 */
IO_PD_4 = 52, /*!< Port D, Pin 4 */
IO_PD_5 = 53, /*!< Port D, Pin 5 */
IO_PD_6 = 54, /*!< Port D, Pin 6 */
IO_PD_7 = 55, /*!< Port D, Pin 7 */
IO_PD_8 = 56, /*!< Port D, Pin 8 */
IO_PD_9 = 57, /*!< Port D, Pin 9 */
IO_PD_10 = 58, /*!< Port D, Pin 10 */
IO_PD_11 = 59, /*!< Port D, Pin 11 */
IO_PD_12 = 60, /*!< Port D, Pin 12 */
IO_PD_13 = 61, /*!< Port D, Pin 13 */
IO_PD_14 = 62, /*!< Port D, Pin 14 */
IO_PD_15 = 63, /*!< Port D, Pin 15 */
IO_PE_0 = 64, /*!< Port E, Pin 0 */
IO_PE_1 = 65, /*!< Port E, Pin 1 */
IO_PE_2 = 66, /*!< Port E, Pin 2 */
IO_PE_3 = 67, /*!< Port E, Pin 3 */
IO_PE_4 = 68, /*!< Port E, Pin 4 */
IO_PE_5 = 69, /*!< Port E, Pin 5 */
IO_PE_6 = 70, /*!< Port E, Pin 6 */
IO_PE_7 = 71, /*!< Port E, Pin 7 */
IO_PE_8 = 72, /*!< Port E, Pin 8 */
IO_PE_9 = 73, /*!< Port E, Pin 9 */
IO_PE_10 = 74, /*!< Port E, Pin 10 */
IO_PE_11 = 75, /*!< Port E, Pin 11 */
IO_PE_12 = 76, /*!< Port E, Pin 12 */
IO_PE_13 = 77, /*!< Port E, Pin 13 */
IO_PE_14 = 78, /*!< Port E, Pin 14 */
IO_PE_15 = 79 /*!< Port E, Pin 15 */
#endif /* IO_PACKAGE_LQFP100 */
#if defined(IO_PACKAGE_LQFP144) || defined(IO_PACKAGE_LQFP176)
,
IO_PF_0 = 80, /*!< Port F, Pin 0 */
IO_PF_1 = 81, /*!< Port F, Pin 1 */
IO_PF_2 = 82, /*!< Port F, Pin 2 */
IO_PF_3 = 83, /*!< Port F, Pin 3 */
IO_PF_4 = 84, /*!< Port F, Pin 4 */
IO_PF_5 = 85, /*!< Port F, Pin 5 */
IO_PF_6 = 86, /*!< Port F, Pin 6 */
IO_PF_7 = 87, /*!< Port F, Pin 7 */
IO_PF_8 = 88, /*!< Port F, Pin 8 */
IO_PF_9 = 89, /*!< Port F, Pin 9 */
IO_PF_10 = 90, /*!< Port F, Pin 10 */
IO_PF_11 = 91, /*!< Port F, Pin 11 */
IO_PF_12 = 92, /*!< Port F, Pin 12 */
IO_PF_13 = 93, /*!< Port F, Pin 13 */
IO_PF_14 = 94, /*!< Port F, Pin 14 */
IO_PF_15 = 95, /*!< Port F, Pin 15 */
IO_PG_0 = 96, /*!< Port G, Pin 0 */
IO_PG_1 = 97, /*!< Port G, Pin 1 */
IO_PG_2 = 98, /*!< Port G, Pin 2 */
IO_PG_3 = 99, /*!< Port G, Pin 3 */
IO_PG_4 = 100, /*!< Port G, Pin 4 */
IO_PG_5 = 101, /*!< Port G, Pin 5 */
IO_PG_6 = 102, /*!< Port G, Pin 6 */
IO_PG_7 = 103, /*!< Port G, Pin 7 */
IO_PG_8 = 104, /*!< Port G, Pin 8 */
IO_PG_9 = 105, /*!< Port G, Pin 9 */
IO_PG_10 = 106, /*!< Port G, Pin 10 */
IO_PG_11 = 107, /*!< Port G, Pin 11 */
IO_PG_12 = 108, /*!< Port G, Pin 12 */
IO_PG_13 = 109, /*!< Port G, Pin 13 */
IO_PG_14 = 110, /*!< Port G, Pin 14 */
IO_PG_15 = 111, /*!< Port G, Pin 15 */
IO_PH_0 = 112, /*!< Port H, Pin 0 */
IO_PH_1 = 113 /*!< Port H, Pin 1 */
#endif /* IO_PACKAGE_LQFP144 */
#if defined(IO_PACKAGE_LQFP176)
,
IO_PH_2 = 114, /*!< Port H, Pin 2 */
IO_PH_3 = 115, /*!< Port H, Pin 3 */
IO_PH_4 = 116, /*!< Port H, Pin 4 */
IO_PH_5 = 117, /*!< Port H, Pin 5 */
IO_PH_6 = 118, /*!< Port H, Pin 6 */
IO_PH_7 = 119, /*!< Port H, Pin 7 */
IO_PH_8 = 120, /*!< Port H, Pin 8 */
IO_PH_9 = 121, /*!< Port H, Pin 9 */
IO_PH_10 = 122, /*!< Port H, Pin 10 */
IO_PH_11 = 123, /*!< Port H, Pin 11 */
IO_PH_12 = 124, /*!< Port H, Pin 12 */
IO_PH_13 = 125, /*!< Port H, Pin 13 */
IO_PH_14 = 126, /*!< Port H, Pin 14 */
IO_PH_15 = 127, /*!< Port H, Pin 15 */
IO_PI_0 = 128, /*!< Port I, Pin 0 */
IO_PI_1 = 129, /*!< Port I, Pin 1 */
IO_PI_2 = 130, /*!< Port I, Pin 2 */
IO_PI_3 = 131, /*!< Port I, Pin 3 */
IO_PI_4 = 132, /*!< Port I, Pin 4 */
IO_PI_5 = 133, /*!< Port I, Pin 5 */
IO_PI_6 = 134, /*!< Port I, Pin 6 */
IO_PI_7 = 135, /*!< Port I, Pin 7 */
IO_PI_8 = 136, /*!< Port I, Pin 8 */
IO_PI_9 = 137, /*!< Port I, Pin 9 */
IO_PI_10 = 138, /*!< Port I, Pin 10 */
IO_PI_11 = 139 /*!< Port I, Pin 11 */
#endif /* IO_PACKAGE_LQFP176 */
} IO_PORTS_e;
/*================== Function Prototypes ==================================*/
/*================== Function Implementations =============================*/
#endif /* IO_PACKAGE_CFG_H_ */