foxBMS  1.2.1
The foxBMS Battery Management System API Documentation
mxm_17841b.c
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41 
42 /**
43  * @file mxm_17841b.c
44  * @author foxBMS Team
45  * @date 2018-12-14 (date of creation)
46  * @updated 2021-12-06 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix MXM
49  *
50  * @brief Driver for the MAX17841B ASCI and MAX1785x monitoring chip
51  *
52  * @details def
53  *
54  */
55 
56 /*========== Includes =======================================================*/
57 #include "mxm_17841b.h"
58 
59 #include "mxm_41b_register_map.h"
60 #include "mxm_bitextract.h"
61 #include "os.h"
62 
63 /*========== Macros and Definitions =========================================*/
64 /** bit shift half byte length */
65 #define MXM_41B_BIT_SHIFT_HALF_BYTE (4u)
66 
67 /** low nibble (of uint8_t) bit mask */
68 #define MXM_41B_BIT_MASK_LOW_NIBBLE (0xFu)
69 
70 /** high nibble (of uint8_t) bit mask */
71 #define MXM_41B_BIT_MASK_HIGH_NIBBLE (0xF0u)
72 
73 /** (uint8_t) one byte bit mask */
74 #define MXM_41B_BIT_MASK_ONE_BYTE (0xFFu)
75 
76 /** threshold above which a reset in this driver occurs in case of hangup */
77 #define MXM_41B_WAIT_COUNTER_THRESHOLD (75u)
78 #if MXM_41B_WAIT_COUNTER_THRESHOLD > (UINT8_MAX - 1)
79 #error "invalid wait counter threshold (counter is implemented in uint8_t)"
80 #endif
81 
82 /**
83  * time interval that shall ensure that the bridge IC is completely reset in ms
84  */
85 #define MXM_41B_BRIDGE_RESET_TIME_MS (100u)
86 
87 /** default config register bank length
88  *
89  * Length of the array that writes the registers referenced in
90  * mxm_41B_reg_default_values in #MXM_41BStateHandlerInit().
91  */
92 #define MXM_41B_CONFIG_REGISTER_LENGTH (7u)
93 
94 /*========== Static Constant and Variable Definitions =======================*/
95 
96 /*========== Extern Constant and Variable Definitions =======================*/
97 
98 /*========== Static Function Prototypes =====================================*/
99 /* static MXM_SPI_STATE_s mxm_proto_enable_keep_alive(void); */
100 /**
101  * @brief Write one or multiple registers of MAX17841B.
102  *
103  * This function puts together a SPI message consisting of command
104  * and payload and writes it to the assigned SPI interface.
105  *
106  * The command should be one of the #MXM_41B_REG_ADD_t commands.
107  * The function checks whether the chosen command is a write command.
108  *
109  * The payload-length has to be consistent with the payload.
110  * Payload-lengths of one will write to one register only. Longer payloads
111  * will write to adjacent registers. Please see the MAX17841B data sheet
112  * for reference.
113  *
114  * @param[in,out] pInstance pointer to the state of the MAX17841B-state-machine
115  * @param[in] command register command of #MXM_41B_REG_ADD_t
116  * @param[in] kpkPayload pointer to an array of data to be written
117  * @param[in] lengthPayload length of the payload array
118  * @return #STD_NOT_OK for inconsistent input or a blocked SPI interface,
119  * otherwise #STD_OK
120  */
122  MXM_41B_INSTANCE_s *pInstance,
123  MXM_41B_REG_ADD_t command,
124  const uint8_t *const kpkPayload,
125  uint8_t lengthPayload);
126 
127 /**
128  * @brief Read one or multiple registers of MAX17841B.
129  *
130  * This function puts together a SPI message consisting of command
131  * and bit-stuffing and writes it to the assigned SPI-interface.
132  *
133  * The command should be one of the #MXM_41B_REG_ADD_t commands.
134  * The function checks whether the chosen command is a read command.
135  *
136  * The RX buffer length has to be consistent with the RX buffer.
137  * RX buffer lengths of one will read one register only. Longer RX buffers
138  * will read also from adjacent registers. Please see the MAX17841B data sheet
139  * for reference.
140  *
141  * @param[in,out] pInstance pointer to the state of the MAX17841B-state-machine
142  * @param[in] command register command of #MXM_41B_REG_ADD_t
143  * @param[out] pRxBuffer pointer to an array into which read data will be written
144  * @param[in] length length of the RX buffer array
145  * @return #STD_NOT_OK for inconsistent input or a blocked SPI interface,
146  * otherwise #STD_OK
147  */
149  MXM_41B_INSTANCE_s *pInstance,
150  MXM_41B_REG_ADD_t command,
151  uint16_t *pRxBuffer,
152  uint8_t length);
153 
154 /**
155  * @brief Write the config register of MAX17841B.
156  *
157  * This functions writes the config registers with the values
158  * from the local register copies. It puts together a
159  * buffer from these register values and calls MXM_41BRegisterWrite()
160  * with this data.
161  *
162  * @param[in,out] pInstance state pointer
163  * @return returnvalue of MXM_41BRegisterWrite()
164  */
166 
167 /**
168  * @brief Write a buffer transaction to MAX17841B.
169  *
170  * Writes into the load-queue-buffer.
171  * The supplied-message-length marks the length of the Battery Management
172  * Protocol message without any stuffing-bytes for read-commands.
173  * The extendMessage parameter describes with how much bytes the
174  * command shall be stretched. This number will be added to the
175  * length of the command and written into the length field of the
176  * buffer.
177  * After this action the user has to select the next load queue with
178  * the appropriate command in order to mark the load queue as sendable.
179  *
180  * @param[in,out] pInstance pointer to the state of the MAX17841B-state-machine
181  * @param[in] kpkMessage pointer to an array containing the message
182  * @param[in] messageLength length of the supplied array
183  * @param[in] extendMessage stretch the message by number of bytes
184  * @return #STD_NOT_OK for inconsistent input or a blocked SPI interface,
185  * otherwise #STD_OK
186  */
188  MXM_41B_INSTANCE_s *pInstance,
189  const uint16_t *const kpkMessage,
190  uint8_t messageLength,
191  uint8_t extendMessage);
192 
193 /**
194  * @brief Transition into idle, mark as successfull
195  * @param[out] pInstance pointer to the state-struct
196  */
197 static void MXM_41BTransitionToIdleSuccess(MXM_41B_INSTANCE_s *pInstance);
198 
199 /**
200  * @brief Transition into idle, mark as an error occurred
201  * @param[out] pInstance pointer to the state-struct
202  */
203 static void MXM_41BTransitionToIdleError(MXM_41B_INSTANCE_s *pInstance);
204 
205 /**
206  * @brief Reset register copies to default
207  * @param[out] pInstance pointer to the state-struct
208  */
210 
211 /**
212  * \defgroup mxm-41b-state-handlers State handler functions for #MXM_41BStateMachine()
213  * @{
214  */
215 
216 /**
217  * @brief init state handler
218  * @details This function contains all states for #MXM_STATEMACH_41B_INIT.
219  * @param[in,out] pInstance pointer to the state-struct
220  */
221 static void MXM_41BStateHandlerInit(MXM_41B_INSTANCE_s *pInstance);
222 
223 /**
224  * @brief state handler for "get version"
225  * @details This function contains all states for #MXM_STATEMACH_41B_GET_VERSION.
226  * @param[in,out] pInstance pointer to the state-struct
227  */
228 static void MXM_41BStateHandlerGetVersion(MXM_41B_INSTANCE_s *pInstance);
229 
230 /**
231  * @brief state handler for "idle"
232  * @details This function contains all states for #MXM_STATEMACH_41B_IDLE.
233  * @param[in,out] pInstance pointer to the state-struct
234  */
235 static void MXM_41BStateHandlerIdle(MXM_41B_INSTANCE_s *pInstance);
236 
237 /**
238  * @brief state handler for "write conf and int register"
239  * @details This functions contains all states for #MXM_STATEMACH_41B_WRITE_CONF_AND_INT_REGISTER.
240  * @param[in,out] pInstance pointer to the state-struct
241  */
243 
244 /**
245  * @brief state handler for "read status register"
246  * @details This functions contains all states for #MXM_STATEMACH_41B_READ_STATUS_REGISTER.
247  * @param[in,out] pInstance pointer to the state-struct
248  */
250 
251 /**
252  * @brief state handler for "uart transaction"
253  * @details This functions contains all states for #MXM_STATEMACH_41B_UART_TRANSACTION.
254  * @param[in,out] pInstance pointer to the state-struct
255  */
257 
258 /**
259  * @brief state handler for "check fmea"
260  * @details This functions contains all states for #MXM_STATEMACH_41B_CHECK_FMEA.
261  * @param[in,out] pInstance pointer to the state-struct
262  */
263 static void MXM_41BStateHandlerCheckFmea(MXM_41B_INSTANCE_s *pInstance);
264 
265 /**
266  * @brief state handler for "clear receive buffer"
267  * @details This functions contains all states for #MXM_STATEMACH_41B_CLEAR_RECEIVE_BUFFER.
268  * @param[in,out] pInstance pointer to the state-struct
269  */
271 
272 /**
273  * @brief state handler for "clear transmit buffer"
274  * @details This functions contains all states for #MXM_STATEMACH_41B_CLEAR_TRANSMIT_BUFFER.
275  * @param[in,out] pInstance pointer to the state-struct
276  */
278 
279 /** @} */
280 
281 /*========== Static Function Implementations ================================*/
283  MXM_41B_INSTANCE_s *pInstance,
284  MXM_41B_REG_ADD_t command,
285  const uint8_t *const kpkPayload,
286  uint8_t lengthPayload) {
287  /* sanity check: state-pointer may not be null */
288  FAS_ASSERT(pInstance != NULL_PTR);
289  FAS_ASSERT(lengthPayload < (MXM_SPI_TX_BUFFER_LENGTH - 1u));
290  STD_RETURN_TYPE_e retval = STD_NOT_OK;
291  /* check if command is a write command (write addresses in MAX17841B are even) */
292  if ((command % 2u) == 0u) {
293  /* construct tx buffer */
294  pInstance->spiTXBuffer[0] = command;
295  /* message has payload --> copy into buffer */
296  if ((kpkPayload != NULL_PTR) && (lengthPayload != 0u)) {
297  for (uint8_t i = 0u; i < lengthPayload; i++) {
298  pInstance->spiTXBuffer[i + 1u] = kpkPayload[i];
299  }
300  /* null rest of tx buffer */
301  for (uint8_t i = lengthPayload + 1u; i < MXM_SPI_TX_BUFFER_LENGTH; i++) {
302  pInstance->spiTXBuffer[i] = 0u;
303  }
304  /* send command with payload */
305  retval = MXM_SendData(pInstance->spiTXBuffer, (uint16_t)lengthPayload + 1u);
306  } else if ((kpkPayload == NULL_PTR) && (lengthPayload == 0u)) {
307  /* send command without payload */
308  retval = MXM_SendData(pInstance->spiTXBuffer, 1);
309  } else {
310  /* invalid configuration */
311  }
312  }
313  return retval;
314 }
315 
317  MXM_41B_INSTANCE_s *pInstance,
318  MXM_41B_REG_ADD_t command,
319  uint16_t *pRxBuffer,
320  uint8_t length) {
321  /* sanity check: state-pointer may not be null */
322  FAS_ASSERT(pInstance != NULL_PTR);
323  /* RX Buffer may not be NULL pointer for this function */
324  FAS_ASSERT(pRxBuffer != NULL_PTR);
326 
327  STD_RETURN_TYPE_e retval = STD_NOT_OK;
328  /* check if command is a read command (read addresses in MAX17841B are odd) */
329  if ((command % 2u) != 0u) {
330  /* construct tx buffer */
331  pInstance->spiTXBuffer[0] = command;
332  /* null rest of tx buffer */
333  for (uint16_t i = 1u; i < MXM_SPI_TX_BUFFER_LENGTH; i++) {
334  pInstance->spiTXBuffer[i] = 0u;
335  }
336  /* send command with payload */
337  retval = MXM_ReceiveData(pInstance->spiTXBuffer, pRxBuffer, ((uint16_t)length + 1u));
338  }
339  return retval;
340 }
341 
343  /* sanity check: state-pointer may not be null */
344  FAS_ASSERT(pInstance != NULL_PTR);
345  uint8_t mxm_spi_temp_buffer[MXM_41B_CONFIG_REGISTER_LENGTH] = {0};
346  /* TODO refactor so that int flags are not cleared by this function (because otherwise we would have to read them before every write) */
347  /* AXIVION Disable Style Generic-NoMagicNumbers: Magic numbers for index value of array is clear in usage */
348  mxm_spi_temp_buffer[0u] = pInstance->regRXIntEnable;
349  mxm_spi_temp_buffer[1u] = pInstance->regTXIntEnable;
350  mxm_spi_temp_buffer[2u] = MXM_41B_RX_INT_FLAG_DEFAULT_VALUE; /* TODO add reg_*x_int_flag */
351  mxm_spi_temp_buffer[3u] = MXM_41B_TX_INT_FLAG_DEFAULT_VALUE;
352  mxm_spi_temp_buffer[4u] = pInstance->regConfig1;
353  mxm_spi_temp_buffer[5u] = pInstance->regConfig2;
354  mxm_spi_temp_buffer[6u] = pInstance->regConfig3;
355  /* AXIVION Enable Style Generic-NoMagicNumbers: */
356  static_assert((6u < MXM_41B_CONFIG_REGISTER_LENGTH), "Revise this function and config register length!");
357 
358  return MXM_41BRegisterWrite(
359  pInstance, MXM_REG_RX_INTERRUPT_ENABLE_W, mxm_spi_temp_buffer, MXM_41B_CONFIG_REGISTER_LENGTH);
360 }
361 
363  MXM_41B_INSTANCE_s *pInstance,
364  const uint16_t *const kpkMessage,
365  uint8_t messageLength,
366  uint8_t extendMessage) {
367  /* sanity check: state-pointer may not be null */
368  FAS_ASSERT(pInstance != NULL_PTR);
369  /* check if message-pointer is valid */
370  FAS_ASSERT(kpkMessage != NULL_PTR);
371  FAS_ASSERT(messageLength >= 1u);
372  FAS_ASSERT(messageLength <= 6u);
373 
374  /* write address and length to buffer */
375  pInstance->spiTXBuffer[0] = (uint16_t)MXM_BUF_WR_LD_Q_0;
376  pInstance->spiTXBuffer[1] = (uint16_t)messageLength + extendMessage;
377  /* iterate of complete TX buffer and
378  * write into proper fields, null rest
379  */
380  for (uint8_t i = 0; i < (MXM_SPI_TX_BUFFER_LENGTH - 2u); i++) {
381  if (i < messageLength) {
382  pInstance->spiTXBuffer[i + 2u] = kpkMessage[i];
383  } else {
384  pInstance->spiTXBuffer[i + 2u] = 0x00u;
385  }
386  }
387 
388  /* send data */
389  return MXM_SendData(pInstance->spiTXBuffer, ((uint16_t)messageLength + 2u));
390 }
391 
393  FAS_ASSERT(pInstance != NULL_PTR);
394  FAS_ASSERT(pInstance->processed != NULL_PTR);
395  pInstance->state = MXM_STATEMACH_41B_IDLE;
396  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
397  *pInstance->processed = MXM_41B_STATE_PROCESSED;
398  return;
399 }
400 
402  FAS_ASSERT(pInstance != NULL_PTR);
403  FAS_ASSERT(pInstance->processed != NULL_PTR);
404  pInstance->state = MXM_STATEMACH_41B_IDLE;
405  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
406  *pInstance->processed = MXM_41B_STATE_ERROR;
407  return;
408 }
409 
411  FAS_ASSERT(pInstance != NULL_PTR);
412  pInstance->regRXStatus = 0u;
413  pInstance->regTXStatus = 0u;
419  return;
420 }
421 
423  FAS_ASSERT(pInstance != NULL_PTR);
424 
425  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
426  /* entry of state --> set to first substate */
428  }
429 
430  if (pInstance->substate == MXM_41B_INIT_RESET_BRIDGE_IC) {
432  pInstance->shutdownTimeStamp = OS_GetTickCount();
434  } else if (pInstance->substate == MXM_41B_INIT_START_BRIDGE_IC) {
435  const bool resetTimeHasPassed =
437  if (resetTimeHasPassed) {
440  }
441  } else if (pInstance->substate == MXM_41B_INIT_WRITE_DEFAULT_VALUES) {
442  /* set default register values according to data sheet */
444  const STD_RETURN_TYPE_e retval = MXM_41BConfigRegisterWrite(pInstance);
445  if (retval == STD_OK) {
447  }
448  } else if (pInstance->substate == MXM_41B_INIT_READ_CONFIG_REGISTERS) {
449  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(
451 
452  if (retval == STD_OK) {
454  }
455  } else if (pInstance->substate == MXM_41B_INIT_CHECK_INITIALIZATION) {
456  STD_RETURN_TYPE_e retval = STD_OK;
457 
458  if (MXM_GetSPIStateReady() == STD_OK) {
459  /**
460  * @brief Default values for the configuration and interrupt registers
461  * @details This constant array contains the default values to which the
462  * configuration is compared when resetting it.
463  * The array is 7 entries long in order to fit onto the following
464  * registers which are placed in succession in the memory of
465  * MAX17841B:
466  * - RX_Interrupt_Enable
467  * - TX_Interrupt_Enable
468  * - RX_Interrupt_Flags
469  * - TX_Interrupt_Flags
470  * - Configuration_1
471  * - Configuration_2
472  * - Configuration_3
473  */
474  const uint8_t mxm_41B_reg_default_values[MXM_41B_CONFIG_REGISTER_LENGTH] = {
482 
483  for (uint8_t i = 0; i < MXM_41B_CONFIG_REGISTER_LENGTH; i++) {
484  if (pInstance->spiRXBuffer[i + 1u] != mxm_41B_reg_default_values[i]) {
485  retval = STD_NOT_OK;
486  }
487  }
488  } else {
489  retval = STD_NOT_OK;
490  }
491 
492  if (retval == STD_NOT_OK) {
493  MXM_41BTransitionToIdleError(pInstance);
494  } else {
496  }
497  } else {
498  MXM_41BTransitionToIdleError(pInstance);
499  }
500 }
501 
503  FAS_ASSERT(pInstance != NULL_PTR);
504  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
506  }
507 
508  if (pInstance->substate == MXM_41B_VERSION_REQUEST_REGISTER) {
509  /* read two byte in order to read also the adjacent version register */
510  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_MODEL_R, pInstance->spiRXBuffer, 2);
511 
512  if (retval == STD_OK) {
513  pInstance->substate = MXM_41B_VERSION_VERIFY;
514  }
515  } else if (pInstance->substate == MXM_41B_VERSION_VERIFY) {
516  if (MXM_GetSPIStateReady() == STD_OK) {
517  /* get model from model register and high nibble of mask revision (should be 0x8410) */
518  pInstance->hwModel =
519  (uint16_t)((pInstance->spiRXBuffer[1] & MXM_41B_BIT_MASK_ONE_BYTE) << MXM_41B_BIT_SHIFT_HALF_BYTE);
520  pInstance->hwModel |=
522  /* extract mask revision from low nibble */
523  pInstance->hwMaskRevision = (uint8_t)(pInstance->spiRXBuffer[2] & MXM_41B_BIT_MASK_LOW_NIBBLE);
524 
526  }
527 
528  } else {
529  /* something is very broken */
530  MXM_41BTransitionToIdleError(pInstance);
531  }
532 }
533 
535  FAS_ASSERT(pInstance != NULL_PTR);
536  /* do nothing in idle state
537  just clean up substate */
538  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
539 }
540 
542  FAS_ASSERT(pInstance != NULL_PTR);
543  const STD_RETURN_TYPE_e retval = MXM_41BConfigRegisterWrite(pInstance);
544 
545  if (retval == STD_NOT_OK) {
546  MXM_41BTransitionToIdleError(pInstance);
547  } else {
549  }
550 }
551 
553  FAS_ASSERT(pInstance != NULL_PTR);
554  /* TODO read status register and parse into static variables */
555  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
556  /* entry of state --> set to first substate */
558  }
559 
560  if (pInstance->substate == MXM_41B_READ_STATUS_REGISTER_SEND) {
561  /* read rx and tx status register */
562  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_RX_STATUS_R, pInstance->spiRXBuffer, 2);
563  if (retval == STD_NOT_OK) {
564  MXM_41BTransitionToIdleError(pInstance);
565  } else {
567  }
568  } else if (pInstance->substate == MXM_41B_READ_STATUS_REGISTER_PROCESS) {
569  pInstance->regRXStatus = (uint8_t)(pInstance->spiRXBuffer[1] & 0xFFu);
570  pInstance->regTXStatus = (uint8_t)(pInstance->spiRXBuffer[2] & 0xFFu);
572  } else {
573  /* something is very broken */
574  MXM_41BTransitionToIdleError(pInstance);
575  }
576 }
577 
579  FAS_ASSERT(pInstance != NULL_PTR);
580  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
581  /* entry of state --> set to first substate */
583  }
584 
585  if (pInstance->substate == MXM_41B_UART_READ_RX_SPACE) {
586  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_RX_SPACE_R, pInstance->spiRXBuffer, 1u);
587  if (retval == STD_NOT_OK) {
588  MXM_41BTransitionToIdleError(pInstance);
589  } else {
591  }
592  } else if (pInstance->substate == MXM_41B_UART_READ_RX_SPACE_PARSE) {
593  pInstance->regRxSpace = (uint8_t)(pInstance->spiRXBuffer[1] & MXM_41B_BIT_MASK_ONE_BYTE);
595 
596  } else if (pInstance->substate == MXM_41B_UART_WRITE_LOAD_QUEUE) {
597  /* load queue with message */
598  const STD_RETURN_TYPE_e retval =
599  MXM_41BBufferWrite(pInstance, pInstance->pPayload, pInstance->payloadLength, pInstance->extendMessageBytes);
600 
601  if (retval == STD_NOT_OK) {
602  MXM_41BTransitionToIdleError(pInstance);
603  } else {
605  }
606  } else if (pInstance->substate == MXM_41B_UART_READ_LOAD_QUEUE) {
607  /* check assumption that incremented payloadlength fits into uint8_t */
608  FAS_ASSERT(pInstance->payloadLength < (uint8_t)UINT8_MAX);
609  const uint8_t payloadLength = pInstance->payloadLength + 1u;
610  /* send read load queue */
611  const STD_RETURN_TYPE_e retval =
612  MXM_41BRegisterRead(pInstance, MXM_BUF_RD_LD_Q_0, pInstance->spiRXBuffer, payloadLength);
613 
614  if (retval == STD_NOT_OK) {
615  MXM_41BTransitionToIdleError(pInstance);
616  } else {
618  }
619  } else if (pInstance->substate == MXM_41B_UART_VERIFY_LOAD_QUEUE_AND_TRANSMIT) {
620  /* verify load queue */
621  STD_RETURN_TYPE_e retval = STD_OK;
622  /* check message length */
623  if (pInstance->spiRXBuffer[1] != (pInstance->payloadLength + (uint16_t)pInstance->extendMessageBytes)) {
624  retval = STD_NOT_OK;
625  }
626  for (uint8_t i = 0; i < pInstance->payloadLength; i++) {
627  FAS_ASSERT(pInstance->pPayload != NULL_PTR);
628  if (pInstance->spiRXBuffer[i + 2u] != pInstance->pPayload[i]) {
629  /* message corrupted during SPI transfer */
630  retval = STD_NOT_OK;
631  }
632  }
633  if (retval == STD_NOT_OK) {
634  MXM_41BTransitionToIdleError(pInstance);
635  } else {
636  /* transmit queue */
637  retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_WR_NXT_LD_Q_0, NULL_PTR, 0);
638 
639  if (retval == STD_NOT_OK) {
640  MXM_41BTransitionToIdleError(pInstance);
641  } else {
643  }
644  }
645  } else if (pInstance->substate == MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_WRITE) {
646  /* poll RX status change */
647  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_RX_STATUS_R, pInstance->spiRXBuffer, 1);
648 
649  if (retval == STD_NOT_OK) {
650  MXM_41BTransitionToIdleError(pInstance);
651  } else {
653  }
655  /* update RX status register copy with received buffer */
656  pInstance->regRXStatus = (uint8_t)(pInstance->spiRXBuffer[1] & MXM_41B_BIT_MASK_ONE_BYTE);
657  /* check if RX_OVERFLOW_Status is 1 */
658  MXM_41B_REG_BIT_VALUE rx_overflow_status_value = MXM_41B_REG_FALSE;
659  const STD_RETURN_TYPE_e resultWrongRegisterOverflow =
660  MXM_41BReadRegisterFunction(pInstance, MXM_41B_REG_FUNCTION_RX_OVERFLOW_STATUS, &rx_overflow_status_value);
661  FAS_ASSERT(resultWrongRegisterOverflow == STD_OK);
662  /* check if RX_STOP_Status is 1 */
663  MXM_41B_REG_BIT_VALUE rx_stop_status_value = MXM_41B_REG_FALSE;
664  const STD_RETURN_TYPE_e resultWrongRegisterStop =
665  MXM_41BReadRegisterFunction(pInstance, MXM_41B_REG_FUNCTION_RX_STOP_STATUS, &rx_stop_status_value);
666  FAS_ASSERT(resultWrongRegisterStop == STD_OK);
667  if (rx_overflow_status_value == MXM_41B_REG_TRUE) {
668  /* overflow, we have to discard the rx buffer */
669  const STD_RETURN_TYPE_e retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_CLR_RX_BUF, NULL_PTR, 0);
670  if (retval == STD_NOT_OK) {
671  MXM_41BTransitionToIdleError(pInstance);
672  } else {
673  MXM_41BTransitionToIdleError(pInstance);
674  }
675  } else if (rx_stop_status_value == MXM_41B_REG_TRUE) {
676  /* received full UART frame --> continue */
677  /* check assumption that payload length fits into uint8_t */
678  FAS_ASSERT((pInstance->payloadLength + (uint16_t)1u + pInstance->extendMessageBytes) <= (uint8_t)UINT8_MAX);
679  const uint8_t payloadLength = pInstance->payloadLength + 1u + pInstance->extendMessageBytes;
680  /* read back receive buffer */
681  const STD_RETURN_TYPE_e retval =
682  MXM_41BRegisterRead(pInstance, MXM_BUF_RD_NXT_MSG, pInstance->spiRXBuffer, payloadLength);
683 
684  if (retval == STD_NOT_OK) {
685  MXM_41BTransitionToIdleError(pInstance);
686  } else {
688  pInstance->waitCounter = 0u;
689  }
690  } else {
691  /* no UART frame received yet --> check again */
693  /* increment wait counter (only to 1 above MXM_41B_WAIT_COUNTER_THRESHOLD,
694  then other parts of the code will reset). */
695  if (pInstance->waitCounter <= MXM_41B_WAIT_COUNTER_THRESHOLD) {
696  pInstance->waitCounter++;
697  }
698  }
699  } else if (pInstance->substate == MXM_41B_UART_READ_BACK_RECEIVE_BUFFER_SAVE) {
700  if ((pInstance->spiRXBuffer != NULL_PTR) && (pInstance->pRxBuffer != NULL_PTR)) {
701  for (uint16_t i = 0; i < ((uint16_t)pInstance->payloadLength + pInstance->extendMessageBytes); i++) {
702  if (i < pInstance->rxBufferLength) {
703  pInstance->pRxBuffer[i] = pInstance->spiRXBuffer[i + 1u];
704  }
705  }
706  }
708  } else {
709  /* we should not be here */
711  }
712 }
713 
715  FAS_ASSERT(pInstance != NULL_PTR);
716  if (pInstance->substate == MXM_41B_ENTRY_SUBSTATE) {
718  }
719 
720  if (pInstance->substate == MXM_41B_FMEA_REQUEST_REGISTER) {
721  const STD_RETURN_TYPE_e retval = MXM_41BRegisterRead(pInstance, MXM_REG_FMEA_R, pInstance->spiRXBuffer, 1);
722 
723  if (retval == STD_OK) {
724  pInstance->substate = MXM_41B_FMEA_VERIFY;
725  }
726  } else if (pInstance->substate == MXM_41B_FMEA_VERIFY) {
727  STD_RETURN_TYPE_e retval = STD_NOT_OK;
728  if (MXM_GetSPIStateReady() == STD_OK) {
729  if (pInstance->spiRXBuffer[1] == 0u) {
730  retval = STD_OK;
731  }
732  }
733 
734  if (retval == STD_NOT_OK) {
735  /* FMEA check went bad */
736  MXM_41BTransitionToIdleError(pInstance);
737  } else {
739  }
740  } else {
741  /* something is very broken */
742  MXM_41BTransitionToIdleError(pInstance);
743  }
744 }
745 
747  FAS_ASSERT(pInstance != NULL_PTR);
748  /* clear receive buffer --> reset UART RX into defined state */
749  const STD_RETURN_TYPE_e retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_CLR_RX_BUF, NULL_PTR, 0);
750 
751  if (retval == STD_OK) {
752  /* writing successful, return to idle */
754  } else {
755  /* an error has occurred, retry and set error */
756  MXM_41BTransitionToIdleError(pInstance);
757  }
758 }
759 
761  FAS_ASSERT(pInstance != NULL_PTR);
762  /* clear receive buffer --> reset UART RX into defined state */
763  const STD_RETURN_TYPE_e retval = MXM_41BRegisterWrite(pInstance, MXM_BUF_CLR_TX_BUF, NULL_PTR, 0);
764 
765  if (retval == STD_OK) {
766  /* writing successful, return to idle */
768  } else {
769  /* an error has occurred, retry and set error */
770  MXM_41BTransitionToIdleError(pInstance);
771  }
772 }
773 
774 /*========== Extern Function Implementations ================================*/
776  MXM_41B_INSTANCE_s *pInstance,
777  MXM_STATEMACH_41B_e state,
778  uint16_t *pPayload,
779  uint8_t payloadLength,
780  uint8_t extendMessageBytes,
781  uint16_t *pRxBuffer,
782  uint16_t rxBufferLength,
783  MXM_41B_STATE_REQUEST_STATUS_e *processed) {
784  /* sanity check: state-pointer may not be null */
785  FAS_ASSERT(pInstance != NULL_PTR);
786 
787  STD_RETURN_TYPE_e retval = STD_OK;
788  /* start by checking for input inconsistency */
789  if (state >= MXM_STATEMACH_41B_MAXSTATE) {
790  retval = STD_NOT_OK;
791  } else if ((pPayload == NULL_PTR) && (payloadLength != 0u)) {
792  retval = STD_NOT_OK;
793  } else if ((payloadLength == 0u) && (pPayload != NULL_PTR)) {
794  retval = STD_NOT_OK;
795  } else if ((pRxBuffer == NULL_PTR) && (rxBufferLength != 0u)) {
796  retval = STD_NOT_OK;
797  } else if ((rxBufferLength == 0u) && (pRxBuffer != NULL_PTR)) {
798  retval = STD_NOT_OK;
799  } else if (processed == NULL_PTR) {
800  retval = STD_NOT_OK;
801  } else if (pInstance->state == MXM_STATEMACH_41B_UNINITIALIZED) {
802  if (state == MXM_STATEMACH_41B_INIT) {
803  pInstance->state = state;
804  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
805  pInstance->pPayload = pPayload;
806  pInstance->payloadLength = payloadLength;
807  pInstance->extendMessageBytes = extendMessageBytes;
808  pInstance->pRxBuffer = pRxBuffer;
809  pInstance->rxBufferLength = rxBufferLength;
810  pInstance->processed = processed;
811  *pInstance->processed = MXM_41B_STATE_UNPROCESSED;
812  } else {
813  retval = STD_NOT_OK;
814  }
815  } else if (pInstance->state == MXM_STATEMACH_41B_IDLE) {
816  pInstance->state = state;
817  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
818  pInstance->pPayload = pPayload;
819  pInstance->payloadLength = payloadLength;
820  pInstance->extendMessageBytes = extendMessageBytes;
821  pInstance->pRxBuffer = pRxBuffer;
822  pInstance->rxBufferLength = rxBufferLength;
823  pInstance->processed = processed;
824  *pInstance->processed = MXM_41B_STATE_UNPROCESSED;
825  } else {
826  retval = STD_NOT_OK;
827  }
828  return retval;
829 }
830 
832  MXM_41B_INSTANCE_s *pInstance,
833  MXM_41B_REG_FUNCTION_e registerFunction,
834  MXM_41B_REG_BIT_VALUE value) {
835  /* sanity check: state-pointer may not be null */
836  FAS_ASSERT(pInstance != NULL_PTR);
837 
838  STD_RETURN_TYPE_e retval = STD_OK;
839  /* TODO sanitize value */
840 
841  switch (registerFunction) {
843  pInstance->regConfig2 = mxm_41bWriteValue(
844  value,
845  1,
847  pInstance->regConfig2); /* MXM_41B_TX_PREAMBLES is 5th bit of regConfig2 */
848  break;
850  pInstance->regConfig3 = mxm_41bWriteValue(
851  value, 4, MXM_41B_KEEP_ALIVE, pInstance->regConfig3); /* MXM_41B_KEEP_ALIVE is 0st bit of regConfig3 */
852  break;
854  pInstance->regRXIntEnable = mxm_41bWriteValue(
855  value,
856  1,
858  pInstance->regRXIntEnable); /* MXM_41B_RX_ERROR is 7th bit of regRXIntEnable */
859  break;
861  pInstance->regRXIntEnable = mxm_41bWriteValue(
862  value,
863  1,
865  pInstance->regRXIntEnable); /* MXM_41B_RX_OVERFLOW is 2nd bit of regRXIntEnable */
866  break;
867  default:
868  retval = STD_NOT_OK;
869  break;
870  }
871 
872  return retval;
873 }
874 
876  const MXM_41B_INSTANCE_s *const kpkInstance,
877  MXM_41B_REG_FUNCTION_e registerFunction,
878  MXM_41B_REG_BIT_VALUE *pValue) {
879  /* sanity check: state-pointer may not be null */
880  FAS_ASSERT(kpkInstance != NULL_PTR);
881  /* sanity check: pValue may not be null */
882  FAS_ASSERT(pValue != NULL_PTR);
883  STD_RETURN_TYPE_e retval = STD_OK;
884 
885  switch (registerFunction) {
887  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_BUSY_STATUS); /* 5th bit */
888  break;
890  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_STOP_STATUS); /* 1st bit */
891  break;
893  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_OVERFLOW_STATUS); /* 3rd bit */
894  break;
896  *pValue = mxm_41bReadValue(kpkInstance->regRXStatus, 1, MXM_41B_RX_EMPTY_STATUS); /* 0th bit */
897  break;
899  *pValue = mxm_41bReadValue(kpkInstance->regConfig2, 1, MXM_41B_TX_PREAMBLES); /* 5th bit */
900  break;
901  default:
902  *pValue = MXM_41B_REG_FALSE;
903  retval = STD_NOT_OK;
904  break;
905  }
906 
907  return retval;
908 }
909 
911  /* sanity check: state-pointer may not be null */
912  FAS_ASSERT(pInstance != NULL_PTR);
913 
914  if (pInstance->waitCounter > MXM_41B_WAIT_COUNTER_THRESHOLD) {
915  /* error, reset to idle state */
916  MXM_41BTransitionToIdleError(pInstance);
917  pInstance->waitCounter = 0u;
918  }
919  switch (pInstance->state) {
921  break;
923  MXM_41BStateHandlerInit(pInstance);
924  break;
927  break;
929  MXM_41BStateHandlerIdle(pInstance);
930  break;
933  break;
936  break;
939  break;
941  MXM_41BStateHandlerCheckFmea(pInstance);
942  break;
945  break;
948  break;
949  default:
950  /* this default case should never be reached */
952  break;
953  }
954 }
955 
957  FAS_ASSERT(pInstance != NULL_PTR);
958 
960 
962  pInstance->substate = MXM_41B_ENTRY_SUBSTATE;
963  pInstance->pPayload = NULL_PTR;
964  pInstance->payloadLength = 0u;
965  pInstance->pRxBuffer = NULL_PTR;
966  pInstance->rxBufferLength = 0u;
967  pInstance->processed = NULL_PTR;
968  pInstance->extendMessageBytes = 0u;
969  pInstance->waitCounter = 0u;
970  pInstance->regRxSpace = 0u;
971  pInstance->hwModel = 0u;
972  pInstance->hwMaskRevision = 0u;
973  pInstance->shutdownTimeStamp = 0u;
974 
975  for (uint32_t i = 0u; i < MXM_SPI_RX_BUFFER_LENGTH; i++) {
976  pInstance->spiRXBuffer[i] = 0u;
977  }
978 
979  for (uint32_t i = 0u; i < MXM_SPI_TX_BUFFER_LENGTH; i++) {
980  pInstance->spiTXBuffer[i] = 0u;
981  }
982 }
983 
984 /*========== Externalized Static Function Implementations (Unit Test) =======*/
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:239
#define static_assert(cond, msg)
static assertion macro
Definition: fassert.h:254
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:110
@ STD_NOT_OK
Definition: fstd_types.h:82
@ STD_OK
Definition: fstd_types.h:81
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:75
enum STD_RETURN_TYPE STD_RETURN_TYPE_e
static void MXM_41BStateHandlerClearTransmitBuffer(MXM_41B_INSTANCE_s *pInstance)
state handler for "clear transmit buffer"
Definition: mxm_17841b.c:760
static void MXM_41BStateHandlerIdle(MXM_41B_INSTANCE_s *pInstance)
state handler for "idle"
Definition: mxm_17841b.c:534
static void MXM_41BStateHandlerClearReceiveBuffer(MXM_41B_INSTANCE_s *pInstance)
state handler for "clear receive buffer"
Definition: mxm_17841b.c:746
static void MXM_41BStateHandlerUartTransaction(MXM_41B_INSTANCE_s *pInstance)
state handler for "uart transaction"
Definition: mxm_17841b.c:578
static void MXM_41BStateHandlerWriteConfAndIntRegister(MXM_41B_INSTANCE_s *pInstance)
state handler for "write conf and int register"
Definition: mxm_17841b.c:541
static void MXM_41BStateHandlerReadStatusRegister(MXM_41B_INSTANCE_s *pInstance)
state handler for "read status register"
Definition: mxm_17841b.c:552
static void MXM_41BStateHandlerGetVersion(MXM_41B_INSTANCE_s *pInstance)
state handler for "get version"
Definition: mxm_17841b.c:502
static void MXM_41BStateHandlerCheckFmea(MXM_41B_INSTANCE_s *pInstance)
state handler for "check fmea"
Definition: mxm_17841b.c:714
static void MXM_41BStateHandlerInit(MXM_41B_INSTANCE_s *pInstance)
init state handler
Definition: mxm_17841b.c:422
STD_RETURN_TYPE_e MXM_41BSetStateRequest(MXM_41B_INSTANCE_s *pInstance, MXM_STATEMACH_41B_e state, uint16_t *pPayload, uint8_t payloadLength, uint8_t extendMessageBytes, uint16_t *pRxBuffer, uint16_t rxBufferLength, MXM_41B_STATE_REQUEST_STATUS_e *processed)
Set state transition for MAX17841B-state-machine.
Definition: mxm_17841b.c:775
void MXM_41BStateMachine(MXM_41B_INSTANCE_s *pInstance)
Execute state-machine for the MAX17841B.
Definition: mxm_17841b.c:910
static STD_RETURN_TYPE_e MXM_41BRegisterWrite(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_ADD_t command, const uint8_t *const kpkPayload, uint8_t lengthPayload)
Write one or multiple registers of MAX17841B.
Definition: mxm_17841b.c:282
STD_RETURN_TYPE_e MXM_41BWriteRegisterFunction(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_FUNCTION_e registerFunction, MXM_41B_REG_BIT_VALUE value)
Write a register function.
Definition: mxm_17841b.c:831
static STD_RETURN_TYPE_e MXM_41BConfigRegisterWrite(MXM_41B_INSTANCE_s *pInstance)
Write the config register of MAX17841B.
Definition: mxm_17841b.c:342
static void MXM_41BTransitionToIdleError(MXM_41B_INSTANCE_s *pInstance)
Transition into idle, mark as an error occurred.
Definition: mxm_17841b.c:401
static void MXM_41BInitializeRegisterCopies(MXM_41B_INSTANCE_s *pInstance)
Reset register copies to default.
Definition: mxm_17841b.c:410
static STD_RETURN_TYPE_e MXM_41BRegisterRead(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_ADD_t command, uint16_t *pRxBuffer, uint8_t length)
Read one or multiple registers of MAX17841B.
Definition: mxm_17841b.c:316
#define MXM_41B_CONFIG_REGISTER_LENGTH
Definition: mxm_17841b.c:92
#define MXM_41B_BIT_MASK_HIGH_NIBBLE
Definition: mxm_17841b.c:71
#define MXM_41B_BIT_MASK_ONE_BYTE
Definition: mxm_17841b.c:74
void MXM_41BInitializeStateStruct(MXM_41B_INSTANCE_s *pInstance)
Initializes the state struct with default values.
Definition: mxm_17841b.c:956
static void MXM_41BTransitionToIdleSuccess(MXM_41B_INSTANCE_s *pInstance)
Transition into idle, mark as successfull.
Definition: mxm_17841b.c:392
STD_RETURN_TYPE_e MXM_41BReadRegisterFunction(const MXM_41B_INSTANCE_s *const kpkInstance, MXM_41B_REG_FUNCTION_e registerFunction, MXM_41B_REG_BIT_VALUE *pValue)
Read the value of a register function.
Definition: mxm_17841b.c:875
static STD_RETURN_TYPE_e MXM_41BBufferWrite(MXM_41B_INSTANCE_s *pInstance, const uint16_t *const kpkMessage, uint8_t messageLength, uint8_t extendMessage)
Write a buffer transaction to MAX17841B.
Definition: mxm_17841b.c:362
#define MXM_41B_BIT_SHIFT_HALF_BYTE
Definition: mxm_17841b.c:65
#define MXM_41B_BRIDGE_RESET_TIME_MS
Definition: mxm_17841b.c:85
#define MXM_41B_WAIT_COUNTER_THRESHOLD
Definition: mxm_17841b.c:77
#define MXM_41B_BIT_MASK_LOW_NIBBLE
Definition: mxm_17841b.c:68
Headers for the driver for the MAX17841B ASCI and MAX1785x monitoring chip.
#define MXM_SPI_TX_BUFFER_LENGTH
SPI TX buffer length.
Definition: mxm_17841b.h:75
MXM_STATEMACH_41B_e
States of the MAX17841B state-machine.
Definition: mxm_17841b.h:83
@ MXM_STATEMACH_41B_MAXSTATE
Definition: mxm_17841b.h:94
@ MXM_STATEMACH_41B_GET_VERSION
Definition: mxm_17841b.h:88
@ MXM_STATEMACH_41B_CLEAR_RECEIVE_BUFFER
Definition: mxm_17841b.h:92
@ MXM_STATEMACH_41B_CLEAR_TRANSMIT_BUFFER
Definition: mxm_17841b.h:93
@ MXM_STATEMACH_41B_UNINITIALIZED
Definition: mxm_17841b.h:84
@ MXM_STATEMACH_41B_INIT
Definition: mxm_17841b.h:85
@ MXM_STATEMACH_41B_WRITE_CONF_AND_INT_REGISTER
Definition: mxm_17841b.h:89
@ MXM_STATEMACH_41B_CHECK_FMEA
Definition: mxm_17841b.h:87
@ MXM_STATEMACH_41B_READ_STATUS_REGISTER
Definition: mxm_17841b.h:90
@ MXM_STATEMACH_41B_IDLE
Definition: mxm_17841b.h:86
@ MXM_STATEMACH_41B_UART_TRANSACTION
Definition: mxm_17841b.h:91
@ MXM_41B_FMEA_REQUEST_REGISTER
Definition: mxm_17841b.h:107
@ MXM_41B_INIT_RESET_BRIDGE_IC
Definition: mxm_17841b.h:102
@ MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_WRITE
Definition: mxm_17841b.h:117
@ MXM_41B_VERSION_VERIFY
Definition: mxm_17841b.h:110
@ MXM_41B_UART_READ_RX_SPACE
Definition: mxm_17841b.h:112
@ MXM_41B_INIT_CHECK_INITIALIZATION
Definition: mxm_17841b.h:106
@ MXM_41B_FMEA_VERIFY
Definition: mxm_17841b.h:108
@ MXM_41B_UART_READ_BACK_RECEIVE_BUFFER_SAVE
Definition: mxm_17841b.h:119
@ MXM_41B_VERSION_REQUEST_REGISTER
Definition: mxm_17841b.h:109
@ MXM_41B_ENTRY_SUBSTATE
Definition: mxm_17841b.h:101
@ MXM_41B_UART_WRITE_LOAD_QUEUE
Definition: mxm_17841b.h:114
@ MXM_41B_UART_READ_LOAD_QUEUE
Definition: mxm_17841b.h:115
@ MXM_41B_INIT_START_BRIDGE_IC
Definition: mxm_17841b.h:103
@ MXM_41B_UART_READ_RX_SPACE_PARSE
Definition: mxm_17841b.h:113
@ MXM_41B_INIT_READ_CONFIG_REGISTERS
Definition: mxm_17841b.h:105
@ MXM_41B_UART_VERIFY_LOAD_QUEUE_AND_TRANSMIT
Definition: mxm_17841b.h:116
@ MXM_41B_READ_STATUS_REGISTER_SEND
Definition: mxm_17841b.h:120
@ MXM_41B_READ_STATUS_REGISTER_PROCESS
Definition: mxm_17841b.h:121
@ MXM_41B_INIT_WRITE_DEFAULT_VALUES
Definition: mxm_17841b.h:104
@ MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_READ_AND_READ_BACK_RCV_BUF
Definition: mxm_17841b.h:118
#define MXM_SPI_RX_BUFFER_LENGTH
Definition: mxm_17841b.h:78
MXM_41B_REG_FUNCTION_e
Register functions.
Definition: mxm_17841b.h:140
@ MXM_41B_REG_FUNCTION_RX_BUSY_STATUS
Definition: mxm_17841b.h:141
@ MXM_41B_REG_FUNCTION_RX_EMPTY_STATUS
Definition: mxm_17841b.h:144
@ MXM_41B_REG_FUNCTION_RX_STOP_STATUS
Definition: mxm_17841b.h:143
@ MXM_41B_REG_FUNCTION_RX_OVERFLOW_STATUS
Definition: mxm_17841b.h:142
@ MXM_41B_REG_FUNCTION_TX_PREAMBLES
Definition: mxm_17841b.h:145
@ MXM_41B_REG_FUNCTION_RX_ERROR_INT
Definition: mxm_17841b.h:147
@ MXM_41B_REG_FUNCTION_KEEP_ALIVE
Definition: mxm_17841b.h:146
@ MXM_41B_REG_FUNCTION_RX_OVERFLOW_INT
Definition: mxm_17841b.h:148
MXM_41B_STATE_REQUEST_STATUS_e
Request status of MAX17841B states.
Definition: mxm_17841b.h:130
@ MXM_41B_STATE_ERROR
Definition: mxm_17841b.h:134
@ MXM_41B_STATE_UNPROCESSED
Definition: mxm_17841b.h:132
@ MXM_41B_STATE_PROCESSED
Definition: mxm_17841b.h:133
Register map of the MAX17841 bridge IC.
#define MXM_REG_RX_INTERRUPT_ENABLE_W
RX interrupt enable register write address.
#define MXM_BUF_RD_LD_Q_0
Read load queue starting from location 0.
#define MXM_REG_RX_SPACE_R
RX space register read address.
#define MXM_BUF_CLR_RX_BUF
Reset receive buffer and pointers to default state.
#define MXM_REG_FMEA_R
FMEA register read address.
#define MXM_REG_RX_INTERRUPT_ENABLE_R
RX interrupt enable register read address.
#define MXM_BUF_RD_NXT_MSG
Read receive buffer starting at the oldest unread message.
#define MXM_REG_RX_STATUS_R
RX status register read address.
#define MXM_REG_MODEL_R
Model register read address.
#define MXM_BUF_WR_LD_Q_0
Write load queue starting from location 0.
#define MXM_BUF_CLR_TX_BUF
Reset transmit buffer to default state and clear TX_Q and LD_Q.
#define MXM_BUF_WR_NXT_LD_Q_0
Select next load queue and write starting from location 0.
uint8_t MXM_41B_REG_ADD_t
MAX17841B register addresses.
MXM_41B_REG_BIT_VALUE mxm_41bWriteValue(MXM_41B_REG_BIT_VALUE value, uint8_t numberOfBits, MXM_41B_REG_BITS shift, uint8_t reg)
write a value to a register supplied as variable
MXM_41B_REG_BIT_VALUE mxm_41bReadValue(uint8_t reg, uint8_t numberOfBits, MXM_41B_REG_BITS position)
read a value from a register supplied as variable
Bit extraction function for MXM_17841b.
#define MXM_41B_KEEP_ALIVE
#define MXM_41B_RX_BUSY_STATUS
#define MXM_41B_REG_FALSE
#define MXM_41B_RX_EMPTY_STATUS
#define MXM_41B_RX_OVERFLOW_STATUS
uint8_t MXM_41B_REG_BIT_VALUE
Bit-values for registers.
#define MXM_41B_RX_STOP_STATUS
#define MXM_41B_RX_OVERFLOW_INT_ENABLE
#define MXM_41B_RX_ERROR
#define MXM_41B_TX_PREAMBLES
#define MXM_41B_REG_TRUE
STD_RETURN_TYPE_e MXM_ReceiveData(uint16_t *txBuffer, uint16_t *rxBuffer, uint16_t length)
Send and Receive data over SPI.
Definition: mxm_cfg.c:92
STD_RETURN_TYPE_e MXM_GetSPIStateReady(void)
Return whether SPI interface is ready.
Definition: mxm_cfg.c:82
void MXM_ShutDownBridgeIc(void)
Pulls the shutdown of the bridge IC low.
Definition: mxm_cfg.c:99
void MXM_EnableBridgeIc(void)
Pulls the shutdown of the bridge IC high.
Definition: mxm_cfg.c:103
STD_RETURN_TYPE_e MXM_SendData(uint16_t *txBuffer, uint16_t length)
Transmit data over SPI.
Definition: mxm_cfg.c:86
#define MXM_41B_CONFIG_3_DEFAULT_VALUE
Definition: mxm_cfg.h:103
#define MXM_41B_CONFIG_1_DEFAULT_VALUE
Definition: mxm_cfg.h:91
#define MXM_41B_CONFIG_2_DEFAULT_VALUE
Definition: mxm_cfg.h:97
#define MXM_41B_RX_INT_ENABLE_DEFAULT_VALUE
Definition: mxm_cfg.h:80
#define MXM_41B_RX_INT_FLAG_DEFAULT_VALUE
Definition: mxm_cfg.h:82
#define MXM_41B_TX_INT_ENABLE_DEFAULT_VALUE
Definition: mxm_cfg.h:81
#define MXM_41B_TX_INT_FLAG_DEFAULT_VALUE
Definition: mxm_cfg.h:83
bool OS_CheckTimeHasPassed(uint32_t oldTimeStamp_ms, uint32_t timeToPass_ms)
This function checks if timeToPass has passed since the last timestamp to now.
Definition: os.c:140
Declaration of the OS wrapper interface.
uint32_t OS_GetTickCount(void)
Returns OS based system tick value.
Definition: os_freertos.c:129
Struct for the state-variable of state-machine.
Definition: mxm_17841b.h:157
uint8_t regRXIntEnable
Definition: mxm_17841b.h:167
uint16_t * pRxBuffer
Definition: mxm_17841b.h:162
uint16_t * pPayload
Definition: mxm_17841b.h:160
uint8_t regTXIntEnable
Definition: mxm_17841b.h:168
uint8_t hwMaskRevision
Definition: mxm_17841b.h:176
uint16_t rxBufferLength
Definition: mxm_17841b.h:163
MXM_41B_STATE_REQUEST_STATUS_e * processed
Definition: mxm_17841b.h:164
uint16_t spiRXBuffer[MXM_SPI_RX_BUFFER_LENGTH]
Definition: mxm_17841b.h:178
uint16_t spiTXBuffer[MXM_SPI_TX_BUFFER_LENGTH]
Definition: mxm_17841b.h:179
uint32_t shutdownTimeStamp
Definition: mxm_17841b.h:177
MXM_41B_SUBSTATES_e substate
Definition: mxm_17841b.h:159
MXM_STATEMACH_41B_e state
Definition: mxm_17841b.h:158
uint8_t extendMessageBytes
Definition: mxm_17841b.h:165
uint8_t payloadLength
Definition: mxm_17841b.h:161