foxBMS  1.2.1
The foxBMS Battery Management System API Documentation
mxm_41b_register_map.h File Reference

Register map of the MAX17841 bridge IC. More...

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Macros

#define MXM_BUF_CLR_TX_BUF   ((MXM_41B_BUF_CMD_t)0x20u)
 Reset transmit buffer to default state and clear TX_Q and LD_Q. More...
 
#define MXM_BUF_RD_MSG   ((MXM_41B_BUF_CMD_t)0x91u)
 Read receive buffer starting at RX_RD_Pointer. More...
 
#define MXM_BUF_RD_NXT_MSG   ((MXM_41B_BUF_CMD_t)0x93u)
 Read receive buffer starting at the oldest unread message. More...
 
#define MXM_BUF_WR_NXT_LD_Q_0   ((MXM_41B_BUF_CMD_t)0xB0u)
 Select next load queue and write starting from location 0. More...
 
#define MXM_BUF_WR_NXT_LD_Q_1   ((MXM_41B_BUF_CMD_t)0xB2u)
 Select next load queue and write starting from location 1. More...
 
#define MXM_BUF_WR_NXT_LD_Q_2   ((MXM_41B_BUF_CMD_t)0xB4u)
 Select next load queue and write starting from location 2. More...
 
#define MXM_BUF_WR_NXT_LD_Q_3   ((MXM_41B_BUF_CMD_t)0xB6u)
 Select next load queue and write starting from location 3. More...
 
#define MXM_BUF_WR_NXT_LD_Q_4   ((MXM_41B_BUF_CMD_t)0xB8u)
 Select next load queue and write starting from location 4. More...
 
#define MXM_BUF_WR_NXT_LD_Q_5   ((MXM_41B_BUF_CMD_t)0xBAu)
 Select next load queue and write starting from location 5. More...
 
#define MXM_BUF_WR_NXT_LD_Q_6   ((MXM_41B_BUF_CMD_t)0xBCu)
 Select next load queue and write starting from location 6. More...
 
#define MXM_BUF_WR_LD_Q_0   ((MXM_41B_BUF_CMD_t)0xC0u)
 Write load queue starting from location 0. More...
 
#define MXM_BUF_WR_LD_Q_1   ((MXM_41B_BUF_CMD_t)0xC2u)
 Write load queue starting from location 1. More...
 
#define MXM_BUF_WR_LD_Q_2   ((MXM_41B_BUF_CMD_t)0xC4u)
 Write load queue starting from location 2. More...
 
#define MXM_BUF_WR_LD_Q_3   ((MXM_41B_BUF_CMD_t)0xC6u)
 Write load queue starting from location 3. More...
 
#define MXM_BUF_WR_LD_Q_4   ((MXM_41B_BUF_CMD_t)0xC8u)
 Write load queue starting from location 4. More...
 
#define MXM_BUF_WR_LD_Q_5   ((MXM_41B_BUF_CMD_t)0xCAu)
 Write load queue starting from location 5. More...
 
#define MXM_BUF_WR_LD_Q_6   ((MXM_41B_BUF_CMD_t)0xCCu)
 Write load queue starting from location 6. More...
 
#define MXM_BUF_RD_LD_Q_0   ((MXM_41B_BUF_CMD_t)0xC1u)
 Read load queue starting from location 0. More...
 
#define MXM_BUF_RD_LD_Q_1   ((MXM_41B_BUF_CMD_t)0xC3u)
 Read load queue starting from location 1. More...
 
#define MXM_BUF_RD_LD_Q_2   ((MXM_41B_BUF_CMD_t)0xC5u)
 Read load queue starting from location 2. More...
 
#define MXM_BUF_RD_LD_Q_3   ((MXM_41B_BUF_CMD_t)0xC7u)
 Read load queue starting from location 3. More...
 
#define MXM_BUF_RD_LD_Q_4   ((MXM_41B_BUF_CMD_t)0xC9u)
 Read load queue starting from location 4. More...
 
#define MXM_BUF_RD_LD_Q_5   ((MXM_41B_BUF_CMD_t)0xCBu)
 Read load queue starting from location 5. More...
 
#define MXM_BUF_RD_LD_Q_6   ((MXM_41B_BUF_CMD_t)0xCDu)
 Read load queue starting from location 6. More...
 
#define MXM_BUF_CLR_RX_BUF   ((MXM_41B_BUF_CMD_t)0xE0u)
 Reset receive buffer and pointers to default state. More...
 
#define MXM_REG_RX_STATUS_R   ((MXM_41B_REG_ADD_t)0x01u)
 RX status register read address. More...
 
#define MXM_REG_TX_STATUS_R   ((MXM_41B_REG_ADD_t)0x03u)
 TX status register read address. More...
 
#define MXM_REG_RX_INTERRUPT_ENABLE_R   ((MXM_41B_REG_ADD_t)0x05u)
 RX interrupt enable register read address. More...
 
#define MXM_REG_RX_INTERRUPT_ENABLE_W   ((MXM_41B_REG_ADD_t)0x04u)
 RX interrupt enable register write address. More...
 
#define MXM_REG_TX_INTERRUPT_ENABLE_R   ((MXM_41B_REG_ADD_t)0x07u)
 TX interrupt enable register read address. More...
 
#define MXM_REG_TX_INTERRUPT_ENABLE_W   ((MXM_41B_REG_ADD_t)0x06u)
 TX interrupt enable register write address. More...
 
#define MXM_REG_RX_INTERRUPT_FLAGS_R   ((MXM_41B_REG_ADD_t)0x09u)
 RX interrupt flags register read address. More...
 
#define MXM_REG_RX_INTERRUPT_FLAGS_W   ((MXM_41B_REG_ADD_t)0x08u)
 RX interrupt flags register write address. More...
 
#define MXM_REG_TX_INTERRUPT_FLAGS_R   ((MXM_41B_REG_ADD_t)0x0Bu)
 TX interrupt flags register read address. More...
 
#define MXM_REG_TX_INTERRUPT_FLAGS_W   ((MXM_41B_REG_ADD_t)0x0Au)
 TX interrupt flags register write address. More...
 
#define MXM_REG_CONFIGURATION_1_R   ((MXM_41B_REG_ADD_t)0x0Du)
 Configuration 1 register read address. More...
 
#define MXM_REG_CONFIGURATION_1_W   ((MXM_41B_REG_ADD_t)0x0Cu)
 Configuration 1 register write address. More...
 
#define MXM_REG_CONFIGURATION_2_R   ((MXM_41B_REG_ADD_t)0x0Fu)
 Configuration 2 register read address. More...
 
#define MXM_REG_CONFIGURATION_2_W   ((MXM_41B_REG_ADD_t)0x0Eu)
 Configuration 2 register write address. More...
 
#define MXM_REG_CONFIGURATION_3_R   ((MXM_41B_REG_ADD_t)0x11u)
 Configuration 3 register read address. More...
 
#define MXM_REG_CONFIGURATION_3_W   ((MXM_41B_REG_ADD_t)0x10u)
 Configuration 3 register write address. More...
 
#define MXM_REG_FMEA_R   ((MXM_41B_REG_ADD_t)0x13u)
 FMEA register read address. More...
 
#define MXM_REG_MODEL_R   ((MXM_41B_REG_ADD_t)0x15u)
 Model register read address. More...
 
#define MXM_REG_VERSION_R   ((MXM_41B_REG_ADD_t)0x17u)
 Version register read address. More...
 
#define MXM_REG_RX_BYTE_R   ((MXM_41B_REG_ADD_t)0x19u)
 RX byte register read address. More...
 
#define MXM_REG_RX_SPACE_R   ((MXM_41B_REG_ADD_t)0x1Bu)
 RX space register read address. More...
 
#define MXM_REG_TX_QUEUE_SELECTS_R   ((MXM_41B_REG_ADD_t)0x95u)
 TX queue selects register read address. More...
 
#define MXM_REG_RX_READ_POINTER_R   ((MXM_41B_REG_ADD_t)0x97u)
 RX read pointer register read address. More...
 
#define MXM_REG_RX_WRITE_POINTER_R   ((MXM_41B_REG_ADD_t)0x99u)
 RX write pointer register read address. More...
 
#define MXM_REG_RX_NEXT_MESSAGE_R   ((MXM_41B_REG_ADD_t)0x9Bu)
 RX next message register read address. More...
 

Typedefs

typedef uint8_t MXM_41B_BUF_CMD_t
 Type for MAX17841B buffer transaction commands. More...
 
typedef uint8_t MXM_41B_REG_ADD_t
 MAX17841B register addresses. More...
 

Detailed Description

Register map of the MAX17841 bridge IC.

SPDX-License-Identifier: BSD-3-Clause

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Author
foxBMS Team
Date
2020-06-25 (date of creation)
Updated
2021-06-16 (date of last update)
Prefix
MXM

Definition in file mxm_41b_register_map.h.

Macro Definition Documentation

◆ MXM_BUF_CLR_RX_BUF

#define MXM_BUF_CLR_RX_BUF   ((MXM_41B_BUF_CMD_t)0xE0u)

Reset receive buffer and pointers to default state.

Definition at line 202 of file mxm_41b_register_map.h.

◆ MXM_BUF_CLR_TX_BUF

#define MXM_BUF_CLR_TX_BUF   ((MXM_41B_BUF_CMD_t)0x20u)

Reset transmit buffer to default state and clear TX_Q and LD_Q.

Definition at line 82 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_0

#define MXM_BUF_RD_LD_Q_0   ((MXM_41B_BUF_CMD_t)0xC1u)

Read load queue starting from location 0.

Definition at line 167 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_1

#define MXM_BUF_RD_LD_Q_1   ((MXM_41B_BUF_CMD_t)0xC3u)

Read load queue starting from location 1.

Definition at line 172 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_2

#define MXM_BUF_RD_LD_Q_2   ((MXM_41B_BUF_CMD_t)0xC5u)

Read load queue starting from location 2.

Definition at line 177 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_3

#define MXM_BUF_RD_LD_Q_3   ((MXM_41B_BUF_CMD_t)0xC7u)

Read load queue starting from location 3.

Definition at line 182 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_4

#define MXM_BUF_RD_LD_Q_4   ((MXM_41B_BUF_CMD_t)0xC9u)

Read load queue starting from location 4.

Definition at line 187 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_5

#define MXM_BUF_RD_LD_Q_5   ((MXM_41B_BUF_CMD_t)0xCBu)

Read load queue starting from location 5.

Definition at line 192 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_LD_Q_6

#define MXM_BUF_RD_LD_Q_6   ((MXM_41B_BUF_CMD_t)0xCDu)

Read load queue starting from location 6.

Definition at line 197 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_MSG

#define MXM_BUF_RD_MSG   ((MXM_41B_BUF_CMD_t)0x91u)

Read receive buffer starting at RX_RD_Pointer.

Definition at line 87 of file mxm_41b_register_map.h.

◆ MXM_BUF_RD_NXT_MSG

#define MXM_BUF_RD_NXT_MSG   ((MXM_41B_BUF_CMD_t)0x93u)

Read receive buffer starting at the oldest unread message.

Definition at line 92 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_0

#define MXM_BUF_WR_LD_Q_0   ((MXM_41B_BUF_CMD_t)0xC0u)

Write load queue starting from location 0.

Definition at line 132 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_1

#define MXM_BUF_WR_LD_Q_1   ((MXM_41B_BUF_CMD_t)0xC2u)

Write load queue starting from location 1.

Definition at line 137 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_2

#define MXM_BUF_WR_LD_Q_2   ((MXM_41B_BUF_CMD_t)0xC4u)

Write load queue starting from location 2.

Definition at line 142 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_3

#define MXM_BUF_WR_LD_Q_3   ((MXM_41B_BUF_CMD_t)0xC6u)

Write load queue starting from location 3.

Definition at line 147 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_4

#define MXM_BUF_WR_LD_Q_4   ((MXM_41B_BUF_CMD_t)0xC8u)

Write load queue starting from location 4.

Definition at line 152 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_5

#define MXM_BUF_WR_LD_Q_5   ((MXM_41B_BUF_CMD_t)0xCAu)

Write load queue starting from location 5.

Definition at line 157 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_LD_Q_6

#define MXM_BUF_WR_LD_Q_6   ((MXM_41B_BUF_CMD_t)0xCCu)

Write load queue starting from location 6.

Definition at line 162 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_0

#define MXM_BUF_WR_NXT_LD_Q_0   ((MXM_41B_BUF_CMD_t)0xB0u)

Select next load queue and write starting from location 0.

Definition at line 97 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_1

#define MXM_BUF_WR_NXT_LD_Q_1   ((MXM_41B_BUF_CMD_t)0xB2u)

Select next load queue and write starting from location 1.

Definition at line 102 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_2

#define MXM_BUF_WR_NXT_LD_Q_2   ((MXM_41B_BUF_CMD_t)0xB4u)

Select next load queue and write starting from location 2.

Definition at line 107 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_3

#define MXM_BUF_WR_NXT_LD_Q_3   ((MXM_41B_BUF_CMD_t)0xB6u)

Select next load queue and write starting from location 3.

Definition at line 112 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_4

#define MXM_BUF_WR_NXT_LD_Q_4   ((MXM_41B_BUF_CMD_t)0xB8u)

Select next load queue and write starting from location 4.

Definition at line 117 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_5

#define MXM_BUF_WR_NXT_LD_Q_5   ((MXM_41B_BUF_CMD_t)0xBAu)

Select next load queue and write starting from location 5.

Definition at line 122 of file mxm_41b_register_map.h.

◆ MXM_BUF_WR_NXT_LD_Q_6

#define MXM_BUF_WR_NXT_LD_Q_6   ((MXM_41B_BUF_CMD_t)0xBCu)

Select next load queue and write starting from location 6.

Definition at line 127 of file mxm_41b_register_map.h.

◆ MXM_REG_CONFIGURATION_1_R

#define MXM_REG_CONFIGURATION_1_R   ((MXM_41B_REG_ADD_t)0x0Du)

Configuration 1 register read address.

Definition at line 257 of file mxm_41b_register_map.h.

◆ MXM_REG_CONFIGURATION_1_W

#define MXM_REG_CONFIGURATION_1_W   ((MXM_41B_REG_ADD_t)0x0Cu)

Configuration 1 register write address.

Definition at line 262 of file mxm_41b_register_map.h.

◆ MXM_REG_CONFIGURATION_2_R

#define MXM_REG_CONFIGURATION_2_R   ((MXM_41B_REG_ADD_t)0x0Fu)

Configuration 2 register read address.

Definition at line 267 of file mxm_41b_register_map.h.

◆ MXM_REG_CONFIGURATION_2_W

#define MXM_REG_CONFIGURATION_2_W   ((MXM_41B_REG_ADD_t)0x0Eu)

Configuration 2 register write address.

Definition at line 272 of file mxm_41b_register_map.h.

◆ MXM_REG_CONFIGURATION_3_R

#define MXM_REG_CONFIGURATION_3_R   ((MXM_41B_REG_ADD_t)0x11u)

Configuration 3 register read address.

Definition at line 277 of file mxm_41b_register_map.h.

◆ MXM_REG_CONFIGURATION_3_W

#define MXM_REG_CONFIGURATION_3_W   ((MXM_41B_REG_ADD_t)0x10u)

Configuration 3 register write address.

Definition at line 282 of file mxm_41b_register_map.h.

◆ MXM_REG_FMEA_R

#define MXM_REG_FMEA_R   ((MXM_41B_REG_ADD_t)0x13u)

FMEA register read address.

Definition at line 287 of file mxm_41b_register_map.h.

◆ MXM_REG_MODEL_R

#define MXM_REG_MODEL_R   ((MXM_41B_REG_ADD_t)0x15u)

Model register read address.

Definition at line 292 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_BYTE_R

#define MXM_REG_RX_BYTE_R   ((MXM_41B_REG_ADD_t)0x19u)

RX byte register read address.

Definition at line 302 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_INTERRUPT_ENABLE_R

#define MXM_REG_RX_INTERRUPT_ENABLE_R   ((MXM_41B_REG_ADD_t)0x05u)

RX interrupt enable register read address.

Definition at line 217 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_INTERRUPT_ENABLE_W

#define MXM_REG_RX_INTERRUPT_ENABLE_W   ((MXM_41B_REG_ADD_t)0x04u)

RX interrupt enable register write address.

Definition at line 222 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_INTERRUPT_FLAGS_R

#define MXM_REG_RX_INTERRUPT_FLAGS_R   ((MXM_41B_REG_ADD_t)0x09u)

RX interrupt flags register read address.

Definition at line 237 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_INTERRUPT_FLAGS_W

#define MXM_REG_RX_INTERRUPT_FLAGS_W   ((MXM_41B_REG_ADD_t)0x08u)

RX interrupt flags register write address.

Definition at line 242 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_NEXT_MESSAGE_R

#define MXM_REG_RX_NEXT_MESSAGE_R   ((MXM_41B_REG_ADD_t)0x9Bu)

RX next message register read address.

Definition at line 327 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_READ_POINTER_R

#define MXM_REG_RX_READ_POINTER_R   ((MXM_41B_REG_ADD_t)0x97u)

RX read pointer register read address.

Definition at line 317 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_SPACE_R

#define MXM_REG_RX_SPACE_R   ((MXM_41B_REG_ADD_t)0x1Bu)

RX space register read address.

Definition at line 307 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_STATUS_R

#define MXM_REG_RX_STATUS_R   ((MXM_41B_REG_ADD_t)0x01u)

RX status register read address.

Definition at line 207 of file mxm_41b_register_map.h.

◆ MXM_REG_RX_WRITE_POINTER_R

#define MXM_REG_RX_WRITE_POINTER_R   ((MXM_41B_REG_ADD_t)0x99u)

RX write pointer register read address.

Definition at line 322 of file mxm_41b_register_map.h.

◆ MXM_REG_TX_INTERRUPT_ENABLE_R

#define MXM_REG_TX_INTERRUPT_ENABLE_R   ((MXM_41B_REG_ADD_t)0x07u)

TX interrupt enable register read address.

Definition at line 227 of file mxm_41b_register_map.h.

◆ MXM_REG_TX_INTERRUPT_ENABLE_W

#define MXM_REG_TX_INTERRUPT_ENABLE_W   ((MXM_41B_REG_ADD_t)0x06u)

TX interrupt enable register write address.

Definition at line 232 of file mxm_41b_register_map.h.

◆ MXM_REG_TX_INTERRUPT_FLAGS_R

#define MXM_REG_TX_INTERRUPT_FLAGS_R   ((MXM_41B_REG_ADD_t)0x0Bu)

TX interrupt flags register read address.

Definition at line 247 of file mxm_41b_register_map.h.

◆ MXM_REG_TX_INTERRUPT_FLAGS_W

#define MXM_REG_TX_INTERRUPT_FLAGS_W   ((MXM_41B_REG_ADD_t)0x0Au)

TX interrupt flags register write address.

Definition at line 252 of file mxm_41b_register_map.h.

◆ MXM_REG_TX_QUEUE_SELECTS_R

#define MXM_REG_TX_QUEUE_SELECTS_R   ((MXM_41B_REG_ADD_t)0x95u)

TX queue selects register read address.

Definition at line 312 of file mxm_41b_register_map.h.

◆ MXM_REG_TX_STATUS_R

#define MXM_REG_TX_STATUS_R   ((MXM_41B_REG_ADD_t)0x03u)

TX status register read address.

Definition at line 212 of file mxm_41b_register_map.h.

◆ MXM_REG_VERSION_R

#define MXM_REG_VERSION_R   ((MXM_41B_REG_ADD_t)0x17u)

Version register read address.

Definition at line 297 of file mxm_41b_register_map.h.

Typedef Documentation

◆ MXM_41B_BUF_CMD_t

typedef uint8_t MXM_41B_BUF_CMD_t

Type for MAX17841B buffer transaction commands.

SPI commands for buffer transactions of the MAX17841B.

Definition at line 65 of file mxm_41b_register_map.h.

◆ MXM_41B_REG_ADD_t

typedef uint8_t MXM_41B_REG_ADD_t

MAX17841B register addresses.

Register addresses for the MAX17841B. Valid register addresses range from 0x01 to 0x1B and 0x95 to 0x9B Odd addresses are read addresses and even addresses are write addresses. Read-only registers have no write address.

Definition at line 76 of file mxm_41b_register_map.h.