foxBMS  1.2.1
The foxBMS Battery Management System API Documentation
mxm_41b_register_map.h
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41 
42 /**
43  * @file mxm_41b_register_map.h
44  * @author foxBMS Team
45  * @date 2020-06-25 (date of creation)
46  * @updated 2021-06-16 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix MXM
49  *
50  * @brief Register map of the MAX17841 bridge IC
51  *
52  */
53 
54 #ifndef FOXBMS__MXM_41B_REGISTER_MAP_H_
55 #define FOXBMS__MXM_41B_REGISTER_MAP_H_
56 
57 /*========== Includes =======================================================*/
58 
59 /*========== Macros and Definitions =========================================*/
60 /**
61  * @brief Type for MAX17841B buffer transaction commands
62  *
63  * SPI commands for buffer transactions of the MAX17841B.
64  */
65 typedef uint8_t MXM_41B_BUF_CMD_t;
66 
67 /**
68  * @brief MAX17841B register addresses
69  *
70  * Register addresses for the MAX17841B.
71  * Valid register addresses range from 0x01 to 0x1B
72  * and 0x95 to 0x9B
73  * Odd addresses are read addresses and even addresses are
74  * write addresses. Read-only registers have no write address.
75  */
76 typedef uint8_t MXM_41B_REG_ADD_t;
77 
78 /* AXIVION Disable Style MisraC2012-2.5: For completeness, this section lists all register addresses even though the driver does not use them. */
79 /**
80  * @brief Reset transmit buffer to default state and clear TX_Q and LD_Q
81  */
82 #define MXM_BUF_CLR_TX_BUF ((MXM_41B_BUF_CMD_t)0x20u)
83 
84 /**
85  * @brief Read receive buffer starting at RX_RD_Pointer
86  */
87 #define MXM_BUF_RD_MSG ((MXM_41B_BUF_CMD_t)0x91u)
88 
89 /**
90  * @brief Read receive buffer starting at the oldest unread message
91  */
92 #define MXM_BUF_RD_NXT_MSG ((MXM_41B_BUF_CMD_t)0x93u)
93 
94 /**
95  * @brief Select next load queue and write starting from location 0
96  */
97 #define MXM_BUF_WR_NXT_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xB0u)
98 
99 /**
100  * @brief Select next load queue and write starting from location 1
101  */
102 #define MXM_BUF_WR_NXT_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xB2u)
103 
104 /**
105  * @brief Select next load queue and write starting from location 2
106  */
107 #define MXM_BUF_WR_NXT_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xB4u)
108 
109 /**
110  * @brief Select next load queue and write starting from location 3
111  */
112 #define MXM_BUF_WR_NXT_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xB6u)
113 
114 /**
115  * @brief Select next load queue and write starting from location 4
116  */
117 #define MXM_BUF_WR_NXT_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xB8u)
118 
119 /**
120  * @brief Select next load queue and write starting from location 5
121  */
122 #define MXM_BUF_WR_NXT_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xBAu)
123 
124 /**
125  * @brief Select next load queue and write starting from location 6
126  */
127 #define MXM_BUF_WR_NXT_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xBCu)
128 
129 /**
130  * @brief Write load queue starting from location 0
131  */
132 #define MXM_BUF_WR_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xC0u)
133 
134 /**
135  * @brief Write load queue starting from location 1
136  */
137 #define MXM_BUF_WR_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xC2u)
138 
139 /**
140  * @brief Write load queue starting from location 2
141  */
142 #define MXM_BUF_WR_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xC4u)
143 
144 /**
145  * @brief Write load queue starting from location 3
146  */
147 #define MXM_BUF_WR_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xC6u)
148 
149 /**
150  * @brief Write load queue starting from location 4
151  */
152 #define MXM_BUF_WR_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xC8u)
153 
154 /**
155  * @brief Write load queue starting from location 5
156  */
157 #define MXM_BUF_WR_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xCAu)
158 
159 /**
160  * @brief Write load queue starting from location 6
161  */
162 #define MXM_BUF_WR_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xCCu)
163 
164 /**
165  * @brief Read load queue starting from location 0
166  */
167 #define MXM_BUF_RD_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xC1u)
168 
169 /**
170  * @brief Read load queue starting from location 1
171  */
172 #define MXM_BUF_RD_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xC3u)
173 
174 /**
175  * @brief Read load queue starting from location 2
176  */
177 #define MXM_BUF_RD_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xC5u)
178 
179 /**
180  * @brief Read load queue starting from location 3
181  */
182 #define MXM_BUF_RD_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xC7u)
183 
184 /**
185  * @brief Read load queue starting from location 4
186  */
187 #define MXM_BUF_RD_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xC9u)
188 
189 /**
190  * @brief Read load queue starting from location 5
191  */
192 #define MXM_BUF_RD_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xCBu)
193 
194 /**
195  * @brief Read load queue starting from location 6
196  */
197 #define MXM_BUF_RD_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xCDu)
198 
199 /**
200  * @brief Reset receive buffer and pointers to default state
201  */
202 #define MXM_BUF_CLR_RX_BUF ((MXM_41B_BUF_CMD_t)0xE0u)
203 
204 /**
205  * @brief RX status register read address
206  */
207 #define MXM_REG_RX_STATUS_R ((MXM_41B_REG_ADD_t)0x01u)
208 
209 /**
210  * @brief TX status register read address
211  */
212 #define MXM_REG_TX_STATUS_R ((MXM_41B_REG_ADD_t)0x03u)
213 
214 /**
215  * @brief RX interrupt enable register read address
216  */
217 #define MXM_REG_RX_INTERRUPT_ENABLE_R ((MXM_41B_REG_ADD_t)0x05u)
218 
219 /**
220  * @brief RX interrupt enable register write address
221  */
222 #define MXM_REG_RX_INTERRUPT_ENABLE_W ((MXM_41B_REG_ADD_t)0x04u)
223 
224 /**
225  * @brief TX interrupt enable register read address
226  */
227 #define MXM_REG_TX_INTERRUPT_ENABLE_R ((MXM_41B_REG_ADD_t)0x07u)
228 
229 /**
230  * @brief TX interrupt enable register write address
231  */
232 #define MXM_REG_TX_INTERRUPT_ENABLE_W ((MXM_41B_REG_ADD_t)0x06u)
233 
234 /**
235  * @brief RX interrupt flags register read address
236  */
237 #define MXM_REG_RX_INTERRUPT_FLAGS_R ((MXM_41B_REG_ADD_t)0x09u)
238 
239 /**
240  * @brief RX interrupt flags register write address
241  */
242 #define MXM_REG_RX_INTERRUPT_FLAGS_W ((MXM_41B_REG_ADD_t)0x08u)
243 
244 /**
245  * @brief TX interrupt flags register read address
246  */
247 #define MXM_REG_TX_INTERRUPT_FLAGS_R ((MXM_41B_REG_ADD_t)0x0Bu)
248 
249 /**
250  * @brief TX interrupt flags register write address
251  */
252 #define MXM_REG_TX_INTERRUPT_FLAGS_W ((MXM_41B_REG_ADD_t)0x0Au)
253 
254 /**
255  * @brief Configuration 1 register read address
256  */
257 #define MXM_REG_CONFIGURATION_1_R ((MXM_41B_REG_ADD_t)0x0Du)
258 
259 /**
260  * @brief Configuration 1 register write address
261  */
262 #define MXM_REG_CONFIGURATION_1_W ((MXM_41B_REG_ADD_t)0x0Cu)
263 
264 /**
265  * @brief Configuration 2 register read address
266  */
267 #define MXM_REG_CONFIGURATION_2_R ((MXM_41B_REG_ADD_t)0x0Fu)
268 
269 /**
270  * @brief Configuration 2 register write address
271  */
272 #define MXM_REG_CONFIGURATION_2_W ((MXM_41B_REG_ADD_t)0x0Eu)
273 
274 /**
275  * @brief Configuration 3 register read address
276  */
277 #define MXM_REG_CONFIGURATION_3_R ((MXM_41B_REG_ADD_t)0x11u)
278 
279 /**
280  * @brief Configuration 3 register write address
281  */
282 #define MXM_REG_CONFIGURATION_3_W ((MXM_41B_REG_ADD_t)0x10u)
283 
284 /**
285  * @brief FMEA register read address
286  */
287 #define MXM_REG_FMEA_R ((MXM_41B_REG_ADD_t)0x13u)
288 
289 /**
290  * @brief Model register read address
291  */
292 #define MXM_REG_MODEL_R ((MXM_41B_REG_ADD_t)0x15u)
293 
294 /**
295  * @brief Version register read address
296  */
297 #define MXM_REG_VERSION_R ((MXM_41B_REG_ADD_t)0x17u)
298 
299 /**
300  * @brief RX byte register read address
301  */
302 #define MXM_REG_RX_BYTE_R ((MXM_41B_REG_ADD_t)0x19u)
303 
304 /**
305  * @brief RX space register read address
306  */
307 #define MXM_REG_RX_SPACE_R ((MXM_41B_REG_ADD_t)0x1Bu)
308 
309 /**
310  * @brief TX queue selects register read address
311  */
312 #define MXM_REG_TX_QUEUE_SELECTS_R ((MXM_41B_REG_ADD_t)0x95u)
313 
314 /**
315  * @brief RX read pointer register read address
316  */
317 #define MXM_REG_RX_READ_POINTER_R ((MXM_41B_REG_ADD_t)0x97u)
318 
319 /**
320  * @brief RX write pointer register read address
321  */
322 #define MXM_REG_RX_WRITE_POINTER_R ((MXM_41B_REG_ADD_t)0x99u)
323 
324 /**
325  * @brief RX next message register read address
326  */
327 #define MXM_REG_RX_NEXT_MESSAGE_R ((MXM_41B_REG_ADD_t)0x9Bu)
328 
329 /* AXIVION Enable Style MisraC2012-2.5: */
330 
331 /*========== Extern Constant and Variable Declarations ======================*/
332 
333 /*========== Extern Function Prototypes =====================================*/
334 
335 /*========== Externalized Static Functions Prototypes (Unit Test) ===========*/
336 
337 #endif /* FOXBMS__MXM_41B_REGISTER_MAP_H_ */
uint8_t MXM_41B_BUF_CMD_t
Type for MAX17841B buffer transaction commands.
uint8_t MXM_41B_REG_ADD_t
MAX17841B register addresses.