foxBMS - Unit Tests  1.2.0
The foxBMS Unit Tests API Documentation
fram.c
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41 
42 /**
43  * @file fram.c
44  * @author foxBMS Team
45  * @date 2020-03-05 (date of creation)
46  * @updated 2021-07-14 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix FRAM
49  *
50  * @brief Driver for the FRAM module
51  *
52  *
53  */
54 
55 /*========== Includes =======================================================*/
56 #include "fram.h"
57 
58 #include "io.h"
59 #include "mcu.h"
60 #include "os.h"
61 #include "spi.h"
62 
63 /*========== Macros and Definitions =========================================*/
64 
65 /** delay in µs after writing the FRAM */
66 #define FRAM_DELAY_AFTER_WRITE_ENABLE_US (5U)
67 
68 /** control commands for the FRAM */
69 /**@{*/
70 #define FRAM_WRITECOMMAND (0x02u)
71 #define FRAM_READCOMMAND (0x03u)
72 #define FRAM_WRITEENABLECOMMAND (0x06u)
73 /**@}*/
74 
75 /** maximal memory address of the FRAM */
76 #define FRAM_MAX_ADDRESS (0x3FFFFu)
77 
78 /*========== Static Constant and Variable Definitions =======================*/
79 
80 /*========== Extern Constant and Variable Definitions =======================*/
81 
82 /*========== Static Function Prototypes =====================================*/
83 
84 /*========== Static Function Implementations ================================*/
85 
86 /*========== Extern Function Implementations ================================*/
87 
88 extern void FRAM_Initialize(void) {
89  uint32_t address = 0;
90 
91  /* find address of all variables in FRAM by parsing length of data*/
92  for (uint16_t i = 0u; i < FRAM_BLOCK_MAX; i++) {
93  (&fram_base_header[0u] + i)->address = address;
94  address += (&fram_base_header[0u] + i)->datalength;
95  }
96 
97  /* ASSERT that size of variables does not exceed FRAM size */
98  FAS_ASSERT(!(address > FRAM_MAX_ADDRESS));
99 }
100 
102  uint8_t *wrt_ptr = NULL_PTR;
103  uint32_t address = 0;
104  uint16_t write = 0;
105  uint16_t read = 0;
106  uint16_t size = 0;
107  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
108 
109  retVal = SPI_Lock(SPI_Interface3);
110 
111  if (retVal == STD_OK) {
112  address = (&fram_base_header[0] + blockId)->address;
113 
114  wrt_ptr = (uint8_t *)((&fram_base_header[0] + blockId)->blockptr);
115  size = (&fram_base_header[0] + blockId)->datalength;
116 
117  /* send write enable command */
119  write = FRAM_WRITEENABLECOMMAND;
123 
124  /* send data to write */
125  /* set chip select low to start transmission */
127 
128  /* send write command */
129  write = FRAM_WRITECOMMAND;
131 
132  /* send upper part of address */
133  write = (address & 0x3F0000u) >> 16u;
135 
136  /* send middle part of address */
137  write = (address & 0xFF00u) >> 8u;
139 
140  /* send lower part of address */
141  write = address & 0xFFu;
143 
144  while (size > 0u) {
145  write = (uint16_t)(*wrt_ptr);
147  wrt_ptr++;
148  size--;
149  }
150 
151  /* set chip select high to start transmission */
153 
155  }
156 
157  return retVal;
158 }
159 
161  uint8_t *rd_ptr = NULL_PTR;
162  uint32_t address = 0;
163  uint16_t write = 0;
164  uint16_t read = 0;
165  uint16_t size = 0;
166  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
167 
168  retVal = SPI_Lock(SPI_Interface3);
169 
170  if (retVal == STD_OK) {
171  address = (&fram_base_header[0] + blockId)->address;
172 
173  rd_ptr = (uint8_t *)((&fram_base_header[0] + blockId)->blockptr);
174  size = (&fram_base_header[0] + blockId)->datalength;
175 
176  /* get data to be read */
177  /* set chip select low to start transmission */
179 
180  /* send write command */
181  write = FRAM_READCOMMAND;
183 
184  /* send upper part of address */
185  write = (address & 0x3F0000u) >> 16u;
187 
188  /* send middle part of address */
189  write = (address & 0xFF00u) >> 8u;
191 
192  /* send lower part of address */
193  write = address & 0xFFu;
195 
196  write = 0;
197  while (size > 0u) {
199  *rd_ptr = read;
200  rd_ptr++;
201  size--;
202  }
203 
204  /* set chip select high to start transmission */
206 
208  }
209 
210  return retVal;
211 }
212 
213 /*========== Externalized Static Function Implementations (Unit Test) =======*/
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:233
void FRAM_Initialize(void)
Initializes the addresses to be written in the FRAM.
Definition: fram.c:88
#define FRAM_DELAY_AFTER_WRITE_ENABLE_US
Definition: fram.c:66
#define FRAM_READCOMMAND
Definition: fram.c:71
STD_RETURN_TYPE_e FRAM_Read(FRAM_BLOCK_ID_e blockId)
Reads a variable from the FRAM.
Definition: fram.c:160
#define FRAM_WRITECOMMAND
Definition: fram.c:70
STD_RETURN_TYPE_e FRAM_Write(FRAM_BLOCK_ID_e blockId)
Writes a variable to the FRAM.
Definition: fram.c:101
#define FRAM_MAX_ADDRESS
Definition: fram.c:76
#define FRAM_WRITEENABLECOMMAND
Definition: fram.c:72
Header for the driver for the FRAM module.
FRAM_BASE_HEADER_s fram_base_header[]
Definition: fram_cfg.c:83
enum FRAM_BLOCK_ID FRAM_BLOCK_ID_e
@ FRAM_BLOCK_MAX
Definition: fram_cfg.h:93
@ STD_NOT_OK
Definition: fstd_types.h:73
@ STD_OK
Definition: fstd_types.h:72
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:66
enum STD_RETURN_TYPE STD_RETURN_TYPE_e
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:84
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:91
Header for the driver for the IO module.
void MCU_delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:80
Headers for the driver for the MCU module.
Implementation of the tasks used by the system, headers.
STD_RETURN_TYPE_e SPI_DirectlyTransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:166
STD_RETURN_TYPE_e SPI_Lock(uint8_t spi)
Locks SPI interfaces.
Definition: spi.c:407
void SPI_Unlock(uint8_t spi)
Unlocks SPI interfaces.
Definition: spi.c:422
Headers for the driver for the SPI module.
SPI_INTERFACE_CONFIG_s spi_framInterface
Definition: spi_cfg.c:204
@ SPI_Interface3
Definition: spi_cfg.h:101
volatile uint32_t * pGioPort
Definition: spi_cfg.h:111