foxBMS - Unit Tests  1.2.0
The foxBMS Unit Tests API Documentation
spi.c
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41 
42 /**
43  * @file spi.c
44  * @author foxBMS Team
45  * @date 2019-12-12 (date of creation)
46  * @updated 2021-07-14 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix SPI
49  *
50  * @brief Driver for the SPI module.
51  *
52  */
53 
54 /*========== Includes =======================================================*/
55 #include "spi.h"
56 
57 #include "HL_reg_spi.h"
58 #include "HL_spi.h"
59 #include "HL_sys_common.h"
60 
61 #include "dma.h"
62 #include "fsystem.h"
63 #include "io.h"
64 #include "mcu.h"
65 #include "os.h"
66 
67 /*========== Macros and Definitions =========================================*/
68 /** Bitfield to check for transmission errors in SPI FLAG register */
69 #define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS (0x5Fu)
70 
71 /*========== Static Constant and Variable Definitions =======================*/
72 
73 /*========== Extern Constant and Variable Definitions =======================*/
74 
75 /*========== Static Function Prototypes =====================================*/
76 
77 /*========== Static Function Implementations ================================*/
78 
79 /*========== Extern Function Implementations ================================*/
80 
81 extern STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay) {
83  uint16_t spi_cmdDummy[1] = {0x00};
84 
85  /* Lock SPI hardware to prevent concurrent read/write commands */
86  if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
87  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
88  uint32_t spiRetval =
89  spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), 1u, spi_cmdDummy);
90  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
91 
92  /* Unlock SPI hardware */
93  SPI_Unlock(pSpiInterface->channel);
94 
95  /* Transmission successful */
96  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
97  retval = STD_OK;
98  }
99  MCU_delay_us(delay);
100  }
101  return retval;
102 }
103 
104 STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint32_t frameLength) {
105  STD_RETURN_TYPE_e retval = STD_NOT_OK;
106 
107  /* Lock SPI hardware to prevent concurrent read/write commands */
108  if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
109  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
110  uint32_t spiRetval =
111  spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), frameLength, pTxBuff);
112  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
113 
114  /* Unlock SPI hardware */
115  SPI_Unlock(pSpiInterface->channel);
116 
117  /* Transmission successful */
118  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
119  retval = STD_OK;
120  }
121  }
122  return retval;
123 }
124 
126  SPI_INTERFACE_CONFIG_s *pSpiInterface,
127  uint32_t delay,
128  uint16_t *pTxBuff,
129  uint32_t frameLength) {
130  STD_RETURN_TYPE_e retval = STD_OK;
131 
132  /* Transmit dummy byte */
133  if (SPI_TransmitDummyByte(pSpiInterface, delay) == STD_OK) {
134  /* Transmit data only if transmission of dummy byte was successful */
135  retval = SPI_TransmitData(pSpiInterface, pTxBuff, frameLength);
136  } else {
137  retval = STD_NOT_OK;
138  }
139  return retval;
140 }
141 
143  SPI_INTERFACE_CONFIG_s *pSpiInterface,
144  uint16 *pTxBuff,
145  uint16 *pRxBuff,
146  uint32 frameLength) {
147  STD_RETURN_TYPE_e retval = STD_NOT_OK;
148 
149  /* Lock SPI hardware to prevent concurrent read/write commands */
150  if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
151  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
152  uint32_t spiRetval = SPI_DirectlyTransmitReceiveData(pSpiInterface, pTxBuff, pRxBuff, frameLength);
153  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
154 
155  /* Unlock SPI hardware */
156  SPI_Unlock(pSpiInterface->channel);
157 
158  /* Transmission successful */
159  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
160  retval = STD_OK;
161  }
162  }
163  return retval;
164 }
165 
167  SPI_INTERFACE_CONFIG_s *pSpiInterface,
168  uint16 *pTxBuff,
169  uint16 *pRxBuff,
170  uint32 frameLength) {
171  STD_RETURN_TYPE_e retval = STD_NOT_OK;
172 
173  uint32_t spiRetval = spiTransmitAndReceiveData(
174  pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), frameLength, pTxBuff, pRxBuff);
175 
176  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
177  /* No error flag set during communication */
178  retval = STD_OK;
179  }
180  return retval;
181 }
182 
184  SPI_INTERFACE_CONFIG_s *pSpiInterface,
185  uint16_t *pTxBuff,
186  uint16_t *pRxBuff,
187  uint32_t frameLength) {
188  FAS_ASSERT(pSpiInterface != NULL_PTR);
189  FAS_ASSERT(pTxBuff != NULL_PTR);
190  FAS_ASSERT(pRxBuff != NULL_PTR);
191 
192  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
193 
195  /* Lock SPI hardware to prevent concurrent read/write commands */
196  if ((*(spi_busyFlags + pSpiInterface->channel) == SPI_IDLE) && (pSpiInterface->channel < spi_nrBusyFlags)) {
197  *(spi_busyFlags + pSpiInterface->channel) = SPI_BUSY;
198  retVal = STD_OK;
199  /* Check that not SPI transmission over DMA is taking place */
200  if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
201  /* Go to privilege mode to write DMA config registers */
203 
204  /* Set Tx buffer address */
205  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ISADDR =
206  (uint32_t)pTxBuff;
207  /* Set number of Tx bytes to send */
208  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ITCOUNT =
209  (frameLength << 16U) | 1U;
210 
211  /* Set Rx buffer address */
212  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].IDADDR =
213  (uint32_t)pRxBuff;
214  /* Set number of Rx bytes to receive */
215  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].ITCOUNT =
216  (frameLength << 16U) | 1U;
217 
218  uint8_t spiFmtRegister = 0U;
219  switch (pSpiInterface->pConfig->DFSEL) {
220  case 0U:
221  spiFmtRegister = 0U;
222  break;
223  case 1U:
224  spiFmtRegister = 1U;
225  break;
226  case 2U:
227  spiFmtRegister = 2U;
228  break;
229  case 3U:
230  spiFmtRegister = 3U;
231  break;
232  default:
233  spiFmtRegister = 0U;
234  break;
235  }
236 
237  /* Re-enable channels; because auto-init is disabled */
238  /* Disable otherwise transmission is constantly ongoping */
239  dmaSetChEnable(
240  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel, (dmaTriggerType_t)DMA_HW);
241  dmaSetChEnable(
242  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel, (dmaTriggerType_t)DMA_HW);
243 
244  /* Store the CS pin to be deactivated in DMA callback */
245  spi_dmaTransmission[pSpiInterface->channel].channel = pSpiInterface->channel;
246  spi_dmaTransmission[pSpiInterface->channel].pConfig = pSpiInterface->pConfig;
247  spi_dmaTransmission[pSpiInterface->channel].pNode = pSpiInterface->pNode;
248  spi_dmaTransmission[pSpiInterface->channel].pGioPort = pSpiInterface->pGioPort;
249  spi_dmaTransmission[pSpiInterface->channel].csPin = pSpiInterface->csPin;
250 
251  /* DMA seems to only be able to use FMT0, save FMT0 config */
252  spi_saveFmt0[pSpiInterface->channel] = pSpiInterface->pNode->FMT0;
253 
254  /* DMA seems to only be able to use FMT0, write actual FMT in FMT0 */
255  switch (spiFmtRegister) {
256  case 0U:
257  break;
258  case 1U:
259  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT1;
260  break;
261  case 2U:
262  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT2;
263  break;
264  case 3U:
265  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT3;
266  break;
267  default:
268  break;
269  }
270 
271  /* DMA config registers written, leave privilege mode */
273 
275 
276  /* Software activate CS */
277  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
278  /* DMA_REQ_Enable */
279  /* Starts DMA requests if SPIEN is also set to 1 */
280  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
281 
282  retVal = STD_OK;
283  }
284  } else {
286  }
287 
288  return retVal;
289 }
290 
292  SPI_INTERFACE_CONFIG_s *pSpiInterface,
293  uint32_t delay,
294  uint16_t *pTxBuff,
295  uint16_t *pRxBuff,
296  uint32_t frameLength) {
297  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
298  uint16_t spi_cmdDummy[1] = {0x00};
299 
301  /* Lock SPI hardware to prevent concurrent read/write commands */
302  if ((*(spi_busyFlags + pSpiInterface->channel) == SPI_IDLE) && (pSpiInterface->channel < spi_nrBusyFlags)) {
303  *(spi_busyFlags + pSpiInterface->channel) = SPI_BUSY;
304  retVal = STD_OK;
305 
306  /* Check that not SPI transmission over DMA is taking place */
307  if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
308  /* Go to privilege mode to write DMA config registers */
310 
311  /* Set Tx buffer address */
312  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ISADDR =
313  (uint32_t)pTxBuff;
314  /* Set number of Tx bytes to transmit */
315  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ITCOUNT =
316  (frameLength << 16U) | 1U;
317 
318  /* Set Rx buffer address */
319  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].IDADDR =
320  (uint32_t)pRxBuff;
321  /* Set number of Rx bytes to receive */
322  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].ITCOUNT =
323  (frameLength << 16U) | 1U;
324 
325  uint8_t spiFmtRegister = 0U;
326  switch (pSpiInterface->pConfig->DFSEL) {
327  case 0U:
328  spiFmtRegister = 0U;
329  break;
330  case 1U:
331  spiFmtRegister = 1U;
332  break;
333  case 2U:
334  spiFmtRegister = 2U;
335  break;
336  case 3U:
337  spiFmtRegister = 3U;
338  break;
339  default:
340  spiFmtRegister = 0U;
341  break;
342  }
343 
344  /* Re-enable channels; because auto-init is disabled */
345  /* Disable otherwise transmission is constantly ongoping */
346  dmaSetChEnable(
347  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel, (dmaTriggerType_t)DMA_HW);
348  dmaSetChEnable(
349  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel, (dmaTriggerType_t)DMA_HW);
350 
351  /* Store the CS pin to be deactivated in DMA callback */
352  spi_dmaTransmission[pSpiInterface->channel].channel = pSpiInterface->channel;
353  spi_dmaTransmission[pSpiInterface->channel].pConfig = pSpiInterface->pConfig;
354  spi_dmaTransmission[pSpiInterface->channel].pNode = pSpiInterface->pNode;
355  spi_dmaTransmission[pSpiInterface->channel].pGioPort = pSpiInterface->pGioPort;
356  spi_dmaTransmission[pSpiInterface->channel].csPin = pSpiInterface->csPin;
357 
358  /* DMA seems to only be able to use FMT0, save FMT0 config */
359  spi_saveFmt0[pSpiInterface->channel] = pSpiInterface->pNode->FMT0;
360 
361  /* DMA seems to only be able to use FMT0, write actual FMT in FMT0 */
362  switch (spiFmtRegister) {
363  case 0U:
364  break;
365  case 1U:
366  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT1;
367  break;
368  case 2U:
369  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT2;
370  break;
371  case 3U:
372  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT3;
373  break;
374  default:
375  break;
376  }
377 
378  /* DMA config registers written, leave privilege mode */
380 
382 
383  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
384  uint32_t spiRetval =
385  spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), 1u, spi_cmdDummy);
386  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
387  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
388  /* No error flag set during communication */
389 
390  MCU_delay_us(delay);
391 
392  /* Software activate CS */
393  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
394  /* DMA_REQ_Enable */
395  /* Starts DMA requests if SPIEN is also set to 1 */
396  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
397  }
398  retVal = STD_OK;
399  }
400  } else {
402  }
403 
404  return retVal;
405 }
406 
407 extern STD_RETURN_TYPE_e SPI_Lock(uint8_t spi) {
408  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
409 
411  if ((*(spi_busyFlags + spi) == SPI_IDLE) && (spi < spi_nrBusyFlags)) {
412  *(spi_busyFlags + spi) = SPI_BUSY;
413  retVal = STD_OK;
414  } else {
415  retVal = STD_NOT_OK;
416  }
418 
419  return retVal;
420 }
421 
422 extern void SPI_Unlock(uint8_t spi) {
424  if (spi < spi_nrBusyFlags) {
425  *(spi_busyFlags + spi) = SPI_IDLE;
426  }
428 }
429 
430 extern void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled) {
431  FAS_ASSERT(pNode != NULL_PTR);
432  FAS_ASSERT(bit <= (enum spiPinSelect)LARGEST_PIN_NUMBER);
433 
434  /* retrieve current configuration */
435  spi_config_reg_t configRegisterBuffer = {0};
436  if (pNode == spiREG1) {
437  spi1GetConfigValue(&configRegisterBuffer, CurrentValue);
438  } else if (pNode == spiREG2) {
439  spi2GetConfigValue(&configRegisterBuffer, CurrentValue);
440  } else if (pNode == spiREG3) {
441  spi3GetConfigValue(&configRegisterBuffer, CurrentValue);
442  } else if (pNode == spiREG4) {
443  spi4GetConfigValue(&configRegisterBuffer, CurrentValue);
444  } else if (pNode == spiREG5) {
445  spi5GetConfigValue(&configRegisterBuffer, CurrentValue);
446  } else {
447  /* invalid SPI node */
449  }
450  uint32_t newPc0 = configRegisterBuffer.CONFIG_PC0;
451 
452  if (hardwareControlled == false) {
453  /* bit has to be cleared */
454  newPc0 &= ~(uint32_t)((uint32_t)1u << (uint8_t)(bit));
455  } else {
456  /* bit has to be set */
457  newPc0 |= (uint32_t)((uint32_t)1u << (uint8_t)(bit));
458  }
459 
460  /* set new port value */
461  spiSetFunctional(pNode, newPc0);
462 }
463 
464 /*========== Externalized Static Function Implementations (Unit Test) =======*/
Headers for the driver for the DMA module.
DMA_CHANNEL_CONFIG_s dma_spiDmaChannels[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:68
#define DMAREQEN_BIT
Definition: dma_cfg.h:108
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:233
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:108
@ STD_NOT_OK
Definition: fstd_types.h:73
@ STD_OK
Definition: fstd_types.h:72
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:66
enum STD_RETURN_TYPE STD_RETURN_TYPE_e
Function to switch between user mode and privilege mode.
#define FSYS_SwitchToUserMode()
Switch back to user mode.
Definition: fsystem.h:111
long FSYS_RaisePrivilege(void)
raise privilege
Definition: test_htsensor.c:66
#define LARGEST_PIN_NUMBER
largest pin number that exists in TMS570LC4357
Definition: general.h:73
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:84
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:91
Header for the driver for the IO module.
void MCU_delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:80
Headers for the driver for the MCU module.
void OS_ExitTaskCritical(void)
Exit Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os.c:178
void OS_EnterTaskCritical(void)
Enter Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os.c:174
Implementation of the tasks used by the system, headers.
STD_RETURN_TYPE_e SPI_TransmitReceiveDataDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:183
void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled)
Sets the functional of a SPI pin.
Definition: spi.c:430
STD_RETURN_TYPE_e SPI_DirectlyTransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:166
STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay)
Sends a dummy byte to wake up the SPI interface.
Definition: spi.c:81
STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint32_t frameLength)
Sends data on SPI without DMA.
Definition: spi.c:104
STD_RETURN_TYPE_e SPI_Lock(uint8_t spi)
Locks SPI interfaces.
Definition: spi.c:407
STD_RETURN_TYPE_e SPI_TransmitReceiveDataWithDummyDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:291
void SPI_Unlock(uint8_t spi)
Unlocks SPI interfaces.
Definition: spi.c:422
STD_RETURN_TYPE_e SPI_TransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:142
STD_RETURN_TYPE_e SPI_TransmitDataWithDummy(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay, uint16_t *pTxBuff, uint32_t frameLength)
Sends data on SPI without DMA, with wake-up byte.
Definition: spi.c:125
#define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS
Definition: spi.c:69
Headers for the driver for the SPI module.
SPI_INTERFACE_CONFIG_s spi_dmaTransmission[]
Variable used for SPI over DMA transmission. Retains the CS pin to deactivate in DMA callback.
Definition: spi_cfg.c:252
SPI_BUSY_STATE_e spi_busyFlags[]
Definition: spi_cfg.c:304
uint32_t spi_saveFmt0[]
Definition: spi_cfg.c:295
const uint8_t spi_nrBusyFlags
Definition: spi_cfg.c:313
@ SPI_IDLE
Definition: spi_cfg.h:93
@ SPI_BUSY
Definition: spi_cfg.h:94
dmaChannel_t rxChannel
Definition: dma_cfg.h:127
dmaChannel_t txChannel
Definition: dma_cfg.h:126
const spiDAT1_t * pConfig
Definition: spi_cfg.h:109
SPI_INTERFACE_e channel
Definition: spi_cfg.h:108
spiBASE_t * pNode
Definition: spi_cfg.h:110
volatile uint32_t * pGioPort
Definition: spi_cfg.h:111