foxBMS-UnitTests  1.0.0
The foxBMS Unit Tests API Documentation
spi.c
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41 
42 /**
43  * @file spi.c
44  * @author foxBMS Team
45  * @date 2019-12-12 (date of creation)
46  * @updated 2019-12-12 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix SPI
49  *
50  * @brief Driver for the SPI module.
51  *
52  */
53 
54 /*========== Includes =======================================================*/
55 #include "spi.h"
56 
57 #include "dma.h"
58 #include "fsystem.h"
59 #include "io.h"
60 #include "mcu.h"
61 #include "os.h"
62 
63 /*========== Macros and Definitions =========================================*/
64 /** Bitfield to check for transmission errors in SPI FLAG register */
65 #define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS (0x5Fu)
66 
67 /*========== Static Constant and Variable Definitions =======================*/
68 
69 /*========== Extern Constant and Variable Definitions =======================*/
70 
71 /*========== Static Function Prototypes =====================================*/
72 
73 /*========== Static Function Implementations ================================*/
74 
75 /*========== Extern Function Implementations ================================*/
76 
77 extern STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay) {
78  STD_RETURN_TYPE_e retval = STD_NOT_OK;
79  uint16_t spi_cmdDummy[1] = {0x00};
80 
81  /* Lock SPI hardware to prevent concurrent read/write commands */
82  if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
83  IO_PinReset((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
84  uint32_t spiRetval =
85  spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), 1u, spi_cmdDummy);
86  IO_PinSet((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
87 
88  /* Unlock SPI hardware */
89  SPI_Unlock(pSpiInterface->channel);
90 
91  /* Transmission successful */
92  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
93  retval = STD_OK;
94  }
95  MCU_delay_us(delay);
96  }
97  return retval;
98 }
99 
100 STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint32_t frameLength) {
101  STD_RETURN_TYPE_e retval = STD_NOT_OK;
102 
103  /* Lock SPI hardware to prevent concurrent read/write commands */
104  if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
105  IO_PinReset((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
106  uint32_t spiRetval =
107  spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), frameLength, pTxBuff);
108  IO_PinSet((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
109 
110  /* Unlock SPI hardware */
111  SPI_Unlock(pSpiInterface->channel);
112 
113  /* Transmission successful */
114  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
115  retval = STD_OK;
116  }
117  }
118  return retval;
119 }
120 
121 STD_RETURN_TYPE_e SPI_TransmitDataWithDummy(
122  SPI_INTERFACE_CONFIG_s *pSpiInterface,
123  uint32_t delay,
124  uint16_t *pTxBuff,
125  uint32_t frameLength) {
126  STD_RETURN_TYPE_e retval = STD_OK;
127 
128  /* Transmit dummy byte */
129  if (SPI_TransmitDummyByte(pSpiInterface, delay) == STD_OK) {
130  /* Transmit data only if transmission of dummy byte was successful */
131  retval = SPI_TransmitData(pSpiInterface, pTxBuff, frameLength);
132  } else {
133  retval = STD_NOT_OK;
134  }
135  return retval;
136 }
137 
138 extern STD_RETURN_TYPE_e SPI_TransmitReceiveData(
139  SPI_INTERFACE_CONFIG_s *pSpiInterface,
140  uint16 *pTxBuff,
141  uint16 *pRxBuff,
142  uint32 frameLength) {
143  STD_RETURN_TYPE_e retval = STD_NOT_OK;
144 
145  /* Lock SPI hardware to prevent concurrent read/write commands */
146  if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
147  IO_PinReset((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
148  uint32_t spiRetval = SPI_DirectlyTransmitReceiveData(pSpiInterface, pTxBuff, pRxBuff, frameLength);
149  IO_PinSet((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
150 
151  /* Unlock SPI hardware */
152  SPI_Unlock(pSpiInterface->channel);
153 
154  /* Transmission successful */
155  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
156  retval = STD_OK;
157  }
158  }
159  return retval;
160 }
161 
162 extern STD_RETURN_TYPE_e SPI_DirectlyTransmitReceiveData(
163  SPI_INTERFACE_CONFIG_s *pSpiInterface,
164  uint16 *pTxBuff,
165  uint16 *pRxBuff,
166  uint32 frameLength) {
167  STD_RETURN_TYPE_e retval = STD_NOT_OK;
168 
169  uint32_t spiRetval = spiTransmitAndReceiveData(
170  pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), frameLength, pTxBuff, pRxBuff);
171 
172  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
173  /* No error flag set during communication */
174  retval = STD_OK;
175  }
176  return retval;
177 }
178 
179 extern STD_RETURN_TYPE_e SPI_TransmitReceiveDataDma(
180  SPI_INTERFACE_CONFIG_s *pSpiInterface,
181  uint16_t *pTxBuff,
182  uint16_t *pRxBuff,
183  uint32_t frameLength) {
184  FAS_ASSERT(pSpiInterface != NULL_PTR);
185  FAS_ASSERT(pTxBuff != NULL_PTR);
186  FAS_ASSERT(pRxBuff != NULL_PTR);
187 
188  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
189 
190  OS_EnterTaskCritical();
191  /* Lock SPI hardware to prevent concurrent read/write commands */
192  if ((*(spi_busyFlags + pSpiInterface->channel) == SPI_IDLE) && (pSpiInterface->channel < spi_nrBusyFlags)) {
193  *(spi_busyFlags + pSpiInterface->channel) = SPI_BUSY;
194  retVal = STD_OK;
195  /* Check that not SPI transmission over DMA is taking place */
196  if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
197  /* Go to privilege mode to write DMA config registers */
198  FSYS_RaisePrivilege();
199 
200  /* Set Tx buffer address */
201  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ISADDR =
202  (uint32_t)pTxBuff;
203  /* Set number of Tx bytes to send */
204  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ITCOUNT =
205  (frameLength << 16U) | 1U;
206 
207  /* Set Rx buffer address */
208  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].IDADDR =
209  (uint32_t)pRxBuff;
210  /* Set number of Rx bytes to receive */
211  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].ITCOUNT =
212  (frameLength << 16U) | 1U;
213 
214  uint8_t spiFmtRegister = 0U;
215  switch (pSpiInterface->pConfig->DFSEL) {
216  case 0U:
217  spiFmtRegister = 0U;
218  break;
219  case 1U:
220  spiFmtRegister = 1U;
221  break;
222  case 2U:
223  spiFmtRegister = 2U;
224  break;
225  case 3U:
226  spiFmtRegister = 3U;
227  break;
228  default:
229  spiFmtRegister = 0U;
230  break;
231  }
232 
233  /* Re-enable channels; because auto-init is disabled */
234  /* Disable otherwise transmission is constantly ongoping */
235  dmaSetChEnable(
236  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel, (dmaTriggerType_t)DMA_HW);
237  dmaSetChEnable(
238  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel, (dmaTriggerType_t)DMA_HW);
239 
240  /* Store the CS pin to be deactivated in DMA callback */
241  spi_dmaTransmission[pSpiInterface->channel].channel = pSpiInterface->channel;
242  spi_dmaTransmission[pSpiInterface->channel].pConfig = pSpiInterface->pConfig;
243  spi_dmaTransmission[pSpiInterface->channel].pNode = pSpiInterface->pNode;
244  spi_dmaTransmission[pSpiInterface->channel].pGioPort = pSpiInterface->pGioPort;
245  spi_dmaTransmission[pSpiInterface->channel].csPin = pSpiInterface->csPin;
246 
247  /* DMA seems to only be able to use FMT0, save FMT0 config */
248  spi_saveFmt0[pSpiInterface->channel] = pSpiInterface->pNode->FMT0;
249 
250  /* DMA seems to only be able to use FMT0, write actual FMT in FMT0 */
251  switch (spiFmtRegister) {
252  case 0U:
253  break;
254  case 1U:
255  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT1;
256  break;
257  case 2U:
258  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT2;
259  break;
260  case 3U:
261  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT3;
262  break;
263  default:
264  break;
265  }
266 
267  /* DMA config registers written, leave privilege mode */
268  FSYS_SwitchToUserMode();
269 
270  OS_ExitTaskCritical();
271 
272  /* Software activate CS */
273  IO_PinReset((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
274  /* DMA_REQ_Enable */
275  /* Starts DMA requests if SPIEN is also set to 1 */
276  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
277 
278  retVal = STD_OK;
279  }
280  } else {
281  OS_ExitTaskCritical();
282  }
283 
284  return retVal;
285 }
286 
287 extern STD_RETURN_TYPE_e SPI_TransmitReceiveDataWithDummyDma(
288  SPI_INTERFACE_CONFIG_s *pSpiInterface,
289  uint32_t delay,
290  uint16_t *pTxBuff,
291  uint16_t *pRxBuff,
292  uint32_t frameLength) {
293  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
294  uint16_t spi_cmdDummy[1] = {0x00};
295 
296  OS_EnterTaskCritical();
297  /* Lock SPI hardware to prevent concurrent read/write commands */
298  if ((*(spi_busyFlags + pSpiInterface->channel) == SPI_IDLE) && (pSpiInterface->channel < spi_nrBusyFlags)) {
299  *(spi_busyFlags + pSpiInterface->channel) = SPI_BUSY;
300  retVal = STD_OK;
301 
302  /* Check that not SPI transmission over DMA is taking place */
303  if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
304  /* Go to privilege mode to write DMA config registers */
305  FSYS_RaisePrivilege();
306 
307  /* Set Tx buffer address */
308  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ISADDR =
309  (uint32_t)pTxBuff;
310  /* Set number of Tx bytes to transmit */
311  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ITCOUNT =
312  (frameLength << 16U) | 1U;
313 
314  /* Set Rx buffer address */
315  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].IDADDR =
316  (uint32_t)pRxBuff;
317  /* Set number of Rx bytes to receive */
318  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].ITCOUNT =
319  (frameLength << 16U) | 1U;
320 
321  uint8_t spiFmtRegister = 0U;
322  switch (pSpiInterface->pConfig->DFSEL) {
323  case 0U:
324  spiFmtRegister = 0U;
325  break;
326  case 1U:
327  spiFmtRegister = 1U;
328  break;
329  case 2U:
330  spiFmtRegister = 2U;
331  break;
332  case 3U:
333  spiFmtRegister = 3U;
334  break;
335  default:
336  spiFmtRegister = 0U;
337  break;
338  }
339 
340  /* Re-enable channels; because auto-init is disabled */
341  /* Disable otherwise transmission is constantly ongoping */
342  dmaSetChEnable(
343  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel, (dmaTriggerType_t)DMA_HW);
344  dmaSetChEnable(
345  (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel, (dmaTriggerType_t)DMA_HW);
346 
347  /* Store the CS pin to be deactivated in DMA callback */
348  spi_dmaTransmission[pSpiInterface->channel].channel = pSpiInterface->channel;
349  spi_dmaTransmission[pSpiInterface->channel].pConfig = pSpiInterface->pConfig;
350  spi_dmaTransmission[pSpiInterface->channel].pNode = pSpiInterface->pNode;
351  spi_dmaTransmission[pSpiInterface->channel].pGioPort = pSpiInterface->pGioPort;
352  spi_dmaTransmission[pSpiInterface->channel].csPin = pSpiInterface->csPin;
353 
354  /* DMA seems to only be able to use FMT0, save FMT0 config */
355  spi_saveFmt0[pSpiInterface->channel] = pSpiInterface->pNode->FMT0;
356 
357  /* DMA seems to only be able to use FMT0, write actual FMT in FMT0 */
358  switch (spiFmtRegister) {
359  case 0U:
360  break;
361  case 1U:
362  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT1;
363  break;
364  case 2U:
365  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT2;
366  break;
367  case 3U:
368  pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT3;
369  break;
370  default:
371  break;
372  }
373 
374  /* DMA config registers written, leave privilege mode */
375  FSYS_SwitchToUserMode();
376 
377  OS_ExitTaskCritical();
378 
379  IO_PinReset((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
380  uint32_t spiRetval =
381  spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), 1u, spi_cmdDummy);
382  IO_PinSet((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
383  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
384  /* No error flag set during communication */
385 
386  MCU_delay_us(delay);
387 
388  /* Software activate CS */
389  IO_PinReset((uint32_t *)pSpiInterface->pGioPort, pSpiInterface->csPin);
390  /* DMA_REQ_Enable */
391  /* Starts DMA requests if SPIEN is also set to 1 */
392  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
393  }
394  retVal = STD_OK;
395  }
396  } else {
397  OS_ExitTaskCritical();
398  }
399 
400  return retVal;
401 }
402 
403 extern STD_RETURN_TYPE_e SPI_Lock(uint8_t spi) {
404  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
405 
406  OS_EnterTaskCritical();
407  if ((*(spi_busyFlags + spi) == SPI_IDLE) && (spi < spi_nrBusyFlags)) {
408  *(spi_busyFlags + spi) = SPI_BUSY;
409  retVal = STD_OK;
410  } else {
411  retVal = STD_NOT_OK;
412  }
413  OS_ExitTaskCritical();
414 
415  return retVal;
416 }
417 
418 extern void SPI_Unlock(uint8_t spi) {
419  OS_EnterTaskCritical();
420  if (spi < spi_nrBusyFlags) {
421  *(spi_busyFlags + spi) = SPI_IDLE;
422  }
423  OS_ExitTaskCritical();
424 }
425 
426 /*========== Externalized Static Function Implementations (Unit Test) =======*/
os.h
Implementation of the tasks used by the system, headers.
DMA_CHANNEL_CONFIG::rxChannel
dmaChannel_t rxChannel
Definition: dma_cfg.h:109
SPI_BUSY
@ SPI_BUSY
Definition: spi_cfg.h:94
SPI_TransmitDataWithDummy
STD_RETURN_TYPE_e SPI_TransmitDataWithDummy(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay, uint16_t *pTxBuff, uint32_t frameLength)
Sends data on SPI without DMA, with wake-up byte.
Definition: spi.c:121
SPI_INTERFACE_CONFIG::pGioPort
volatile uint32_t * pGioPort
Definition: spi_cfg.h:111
spi_dmaTransmission
SPI_INTERFACE_CONFIG_s spi_dmaTransmission[]
Variable used for SPI over DMA transmission. Retains the CS pin to deactivate in DMA callback.
Definition: spi_cfg.c:229
STD_RETURN_TYPE_e
enum STD_RETURN_TYPE STD_RETURN_TYPE_e
spi.h
Headers for the driver for the SPI module.
SPI_IDLE
@ SPI_IDLE
Definition: spi_cfg.h:93
SPI_INTERFACE_CONFIG::channel
SPI_INTERFACE_e channel
Definition: spi_cfg.h:108
FSYS_RaisePrivilege
long FSYS_RaisePrivilege(void)
raise privilege
Definition: test_nxpfs85xx.c:94
SPI_INTERFACE_CONFIG::pNode
spiBASE_t * pNode
Definition: spi_cfg.h:110
FAS_ASSERT
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:233
SPI_Lock
STD_RETURN_TYPE_e SPI_Lock(uint8_t spi)
Locks SPI interfaces.
Definition: spi.c:403
OS_ExitTaskCritical
void OS_ExitTaskCritical(void)
Exit Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os.c:178
SPI_TransmitReceiveData
STD_RETURN_TYPE_e SPI_TransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:138
MCU_delay_us
void MCU_delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:80
mcu.h
Headers for the driver for the MCU module.
STD_OK
@ STD_OK
Definition: fstd_types.h:72
SPI_INTERFACE_CONFIG
Definition: spi_cfg.h:107
spi_busyFlags
SPI_BUSY_STATE_e spi_busyFlags[]
Definition: spi_cfg.c:281
SPI_DirectlyTransmitReceiveData
STD_RETURN_TYPE_e SPI_DirectlyTransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:162
SPI_TransmitReceiveDataWithDummyDma
STD_RETURN_TYPE_e SPI_TransmitReceiveDataWithDummyDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:287
OS_EnterTaskCritical
void OS_EnterTaskCritical(void)
Enter Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os.c:174
STD_NOT_OK
@ STD_NOT_OK
Definition: fstd_types.h:73
fsystem.h
Function to switch between user mode and privilege mode.
spi_saveFmt0
uint32_t spi_saveFmt0[]
Definition: spi_cfg.c:272
IO_PinReset
void IO_PinReset(uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:79
SPI_INTERFACE_CONFIG::pConfig
const spiDAT1_t * pConfig
Definition: spi_cfg.h:109
NULL_PTR
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:66
SPI_FLAG_REGISTER_TRANSMISSION_ERRORS
#define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS
Definition: spi.c:65
SPI_TransmitData
STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint32_t frameLength)
Sends data on SPI without DMA.
Definition: spi.c:100
io.h
Header for the driver for the IO module.
SPI_INTERFACE_CONFIG::csPin
uint32_t csPin
Definition: spi_cfg.h:112
DMAREQEN_BIT
#define DMAREQEN_BIT
Definition: dma_cfg.h:90
IO_PinSet
void IO_PinSet(uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:72
SPI_TransmitDummyByte
STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay)
Sends a dummy byte to wake up the SPI interface.
Definition: spi.c:77
DMA_CHANNEL_CONFIG::txChannel
dmaChannel_t txChannel
Definition: dma_cfg.h:108
SPI_Unlock
void SPI_Unlock(uint8_t spi)
Unlocks SPI interfaces.
Definition: spi.c:418
SPI_TransmitReceiveDataDma
STD_RETURN_TYPE_e SPI_TransmitReceiveDataDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:179
FSYS_SwitchToUserMode
#define FSYS_SwitchToUserMode()
Switch back to user mode.
Definition: fsystem.h:111
dma.h
Headers for the driver for the DMA module.
spi_nrBusyFlags
const uint8_t spi_nrBusyFlags
Definition: spi_cfg.c:290
dma_spiDmaChannels
DMA_CHANNEL_CONFIG_s dma_spiDmaChannels[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:68