foxBMS  1.1.0
The foxBMS Battery Management System API Documentation
mxm_register_map.h
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41 
42 /**
43  * @file mxm_register_map.h
44  * @author foxBMS Team
45  * @date 2019-03-05 (date of creation)
46  * @updated 2021-06-16 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix MXM
49  *
50  * @brief Register map of the MAX1785x monitoring IC
51  *
52  * @details Register map with named registers of the monitoring ICs
53  * MAX17852 and MAX17853 by Maxim Integrated
54  *
55  */
56 
57 #ifndef FOXBMS__MXM_REGISTER_MAP_H_
58 #define FOXBMS__MXM_REGISTER_MAP_H_
59 
60 /*========== Includes =======================================================*/
61 #include "general.h"
62 
63 /*========== Macros and Definitions =========================================*/
64 /**
65  * @brief MAX1785x register names
66  * @details Register names and addresses of the monitoring ICs MAX17852 and
67  * MAX17853. Please note that the MAX17853 only supports a subset
68  * of these register values.
69  */
70 typedef enum MXM_REG_NAME {
71  MXM_REG_VERSION = 0x00u, /*!< VERSION is a read only
72  * accessible register which returns information on the device */
73  MXM_REG_ADDRESS = 0x01u, /*!< ADDRESS is a read and write
74  * accessible register which sets the first, last, and device address
75  * used by a device in a UART chain (UARTSEL=1). This register has no NOLINT
76  * effect on a device operating in SPI mode (UARTSEL=0). NOLINT */
77  MXM_REG_STATUS1 = 0x02u, /*!< STATUS1 is a read and write
78  * accessible register which relates the current status of the device.
79  * STATUS1 also contains summary information on STATUS2, STATUS3, and
80  * FMEA registers, and other selected registers indicating if additional
81  * read back checks are required. */
82  MXM_REG_STATUS2 = 0x03u, /*!< STATUS2 is a read and write
83  * accessible register which contains summary information on alerts
84  * related to interface and communication faults. */
85  MXM_REG_STATUS3 = 0x04u, /*!< STATUS3 is a read and write
86  * accessible register which contains summary information on alerts
87  * related to automated cell balancing operations. */
88  MXM_REG_FMEA1 = 0x05u, /*!< FMEA1 is a read and write
89  * accessible register which relates current information on possible
90  * fault conditions. */
91  MXM_REG_FMEA2 = 0x06u, /*!< FMEA2 is a read and write
92  * accessible register which relates current information on possible
93  * fault conditions. */
94  MXM_REG_ALRTSUM = 0x07u, /*!< ALRTSUM is a read accessible
95  * register which relates added, detailed information on the current
96  * states of the device, breaking out several summary bits in STATUS1. */
97  MXM_REG_ALRTOVCELL = 0x08u, /*!< ALRTOVCELL is a read
98  * accessible register which relates current information on cell over
99  * voltage fault alerts based on ADC measurements. */
100  MXM_REG_ALRTUVCELL = 0x09u, /*!< ALRTUVCELL is a read
101  * accessible register which relates current information on cell under
102  * voltage fault alerts based on ADC measurements. */
103  MXM_REG_MINMAXCELL = 0x0Au, /*!< MINMAX is a read accessible
104  * register which relates the cell locations with the highest and lowest
105  * values measured. */
106  MXM_REG_ALRTAUXPRTCT = 0x0Bu, /*!< ALRTAUXPRTCT is a read
107  * accessible register which relates current information on auxiliary
108  * input protection fault alerts. */
109  MXM_REG_ALRTAUXOV = 0x0Cu, /*!< ALRTAUXOV is a read
110  * accessible register which relates current information on auxiliary
111  * over voltage (cold) fault alerts. NOLINT */
112  MXM_REG_ALRTAUXUV = 0x0Du, /*!< ALRTAUXUV is a read accessible
113  * register which relates current information on auxiliary under voltage
114  * fault (hot) alerts. NOLINT */
115  MXM_REG_ALRTCOMPOV = 0x0Eu, /*!< ALRTCOMPOV is a read accessible
116  * register which relates current information on cell over voltage fault
117  * alerts based on the redundant comparator. */
118  MXM_REG_ALRTCOMPUV = 0x0Fu, /*!< ALRTCOMPUV is a read accessible
119  * register which relates current information on cell under voltage fault
120  * alerts based on the redundant comparator. */
121  MXM_REG_ALRTCOMPAUXOV = 0x10u, /*!< ALRTCOMPAUXOV is a read
122  * accessible register which relates current information on auxiliary over
123  * voltage fault (cold) alerts based on the redundant comparator. NOLINT */
124  MXM_REG_ALRTCOMPAUXUV = 0x11u, /*!< ALRTCOMPAUXUV is a read
125  * accessible register which relates current information on auxiliary under
126  * voltage fault (hot) alerts based on the redundant comparator. NOLINT */
127  MXM_REG_ALRTBALSW = 0x12u, /*!< ALRTBALSW is a read accessible
128  * register which relates current summary information on balancing switch
129  * fault alerts. */
130  MXM_REG_SWACTION = 0x13u, /*!< SWACTION is a read and write
131  * accessible register which contains bits allowing software exit and
132  * reset requests. These requests are not recommended for general use,
133  * but may be of use in case of error. */
134  MXM_REG_DEVCFG1 = 0x14u, /*!< DEVCFG1 is a read and write
135  * accessible register which governs the configuration of the device
136  * interface operation. */
137  MXM_REG_DEVCFG2 = 0x15u, /*!< DEVCFG2 is a read and write
138  * accessible register which governs the configuration of the device
139  * filtering, several top level diagnostic modes, and timeout monitors. */
140  MXM_REG_AUXGPIOCFG = 0x16u, /*!< AUXGPIOCFG is a read and write
141  * accessible register which governs the configuration of the AUX/GPIO
142  * multifunction pins. */
143  MXM_REG_GPIOCFG = 0x17u, /*!< GPIOCFG is a read and write
144  * accessible register which governs the output state of GPIO outputs and
145  * reads back the input state of GPIO inputs. */
146  MXM_REG_PACKCFG = 0x18u, /*!< PACKCFG is a read and write
147  * accessible register which configures the part such that the top most
148  * cell and block used in the application is known. Details of Flex Pack
149  * applications are also configured within this register. */
150  MXM_REG_ALRTIRQEN = 0x19u, /*!< ALRTIRQEN is a read and write
151  * accessible register which selects which STATS1 alerts trigger interrupts
152  * via the ALERT interface port(s), and are included in the DCByte and
153  * Alert Packet (UART) or ALERT bit (SPI) notifications. Note the information NOLINT
154  * in the STATUS1 register itself (or any component terms rolled up into NOLINT
155  * STATUS1) is not masked/disabled by these settings, allowing the
156  * underlying data to always be available via STATUS1 readback. */
157  MXM_REG_ALRTOVEN = 0x1Au, /*!< ALRTOVEN is a read and write
158  * accessible register which enables over voltage fault checks on selected
159  * input channels during scans using either the ADC or Comparator. */
160  MXM_REG_ALRTUVEN = 0x1Bu, /*!< ALRTUVEN is a read and write
161  * accessible register which enables under voltage fault checks on selected
162  * input channels during scans using either the ADC or Comparator. */
163  MXM_REG_ALRTAUXOVEN = 0x1Cu, /*!< ALRTAUXOVEN is a read and write
164  * accessible register which enables auxiliary over voltage (cold) fault NOLINT
165  * checks on selected Auxiliary channels during scans using either the
166  * ADC or Comparator. */
167  MXM_REG_ALRTAUXUVEN = 0x1Du, /*!< ALRTAUXUVEN is a read and write
168  * accessible register which enables auxiliary under voltage (hot) fault NOLINT
169  * checks on selected Auxiliary channels using either the
170  * ADC or Comparator. */
171  MXM_REG_ALRTCALTST = 0x1Eu, /*!< ALRTCALTST is a read and write
172  * accessible register which allows the user to force Calibration alerts
173  * to test readback and interrupt logic. The forced alert(s) will remain
174  * forced until this register is written back to zeros (assuming the NOLINT
175  * existing calibration data is within range) */
176  MXM_REG_OVTHCLR = 0x1Fu, /*!< OVTHCLR is a read and write
177  * accessible register which selects the cell over voltage alert
178  * clear threshold used with unipolar ADC measurements. */
179  MXM_REG_OVTHSET = 0x20u, /*!< OVTHSET is a read and write
180  * accessible register which selects the cell over voltage alert set
181  * threshold used with unipolar ADC measurements. */
182  MXM_REG_UVTHCLR = 0x21u, /*!< UVTHCLR is a read and write
183  * accessible register which selects the cell under voltage alert clear
184  * threshold used with unipolar ADC measurements. */
185  MXM_REG_UVTHSET = 0x22u, /*!< UVTHSET is a read and write
186  * accessible register which selects the cell under voltage alert set
187  * threshold used with unipolar ADC measurements. */
188  MXM_REG_MSMTCH = 0x23u, /*!< MSMTCH is a read and write
189  * accessible register which selects the cell voltage mismatch alert
190  * threshold used with ADC cell scan measurements. */
191  MXM_REG_BIPOVTHCLR = 0x24u, /*!< BIPOVTHCLR is a read and write
192  * accessible register which selects the cell over voltage alert clear
193  * threshold used with bipolar ADC measurements. */
194  MXM_REG_BIPOVTHSET = 0x25u, /*!< BIPOVTHSET is a read and write
195  * accessible register which selects the cell over voltage alert set
196  * threshold used with bipolar ADC measurements. */
197  MXM_REG_BIPUVTHCLR = 0x26u, /*!< BIPUVTHCLR is a read and write
198  * accessible register which selects the cell under voltage alert clear
199  * threshold used with bipolar ADC measurements. */
200  MXM_REG_BIPUVTHSET = 0x27u, /*!< BIPUVTHSET is a read and write
201  * accessible register which selects the cell under voltage alert set
202  * threshold used with bipolar ADC measurements. */
203  MXM_REG_BLKOVTHCLR = 0x28u, /*!< BLKOVTHCLR is a read and write
204  * accessible register which selects the block over voltage alert clear
205  * threshold used with ADC measurements. */
206  MXM_REG_BLKOVTHSET = 0x29u, /*!< BLKOVTHSET is a read and write
207  * accessible register which selects the block over voltage alert set
208  * threshold used with ADC measurements. */
209  MXM_REG_BLKUVTHCLR = 0x2Au, /*!< BLKUVTHCLR is a read and write
210  * accessible register which selects the block under voltage alert clear
211  * threshold used with ADC measurements. */
212  MXM_REG_BLKUVTHSET = 0x2Bu, /*!< BLKUVTHSET is a read and write
213  * accessible register which selects the block under voltage alert set
214  * threshold used with ADC measurements. */
215  MXM_REG_CSAOVTHCLR = 0x2Cu, /*!< MAX17852 only: CSAOVTHCLR is a
216  * read and write accessible register which selects the CSA over voltage
217  * alert clear threshold used with ADC measurements. */
218  MXM_REG_CSAOVTHSET = 0x2Du, /*!< MAX17852 only: CSAOVTHSET is a
219  * read and write accessible register which selects the CSA over voltage
220  * alert set threshold used with ADC measurements. */
221  MXM_REG_CSAUVTHCLR = 0x2Eu, /*!< MAX17852 only: CSAUVTHCLR is a
222  * read and write accessible register which selects the CSA under voltage
223  * alert clear threshold used with ADC measurements. */
224  MXM_REG_CSAUVTHSET = 0x2Fu, /*!< MAX17852 only: CSAUVTHSET is a
225  * read and write accessible register which selects the CSA under voltage
226  * alert set threshold used with ADC measurements. */
227  MXM_REG_AUXROVTHCLR = 0x30u, /*!< AUXROVTHCLR is a read and write
228  * accessible register which selects the over voltage (cold) alert NOLINT
229  * clear threshold used with Ratiometric Auxiliary ADC measurements. */
230  MXM_REG_AUXROVTHSET = 0x31u, /*!< AUXROVTHSET is a read and write
231  * accessible register which selects the over voltage (cold) alert set NOLINT
232  * threshold used with Ratiometric Auxiliary ADC measurements. */
233  MXM_REG_AUXRUVTHCLR = 0x32u, /*!< AUXRUVTHCLR is a read and write
234  * accessible register which selects the under voltage (hot) alert clear NOLINT
235  * threshold used with Ratiometric Auxiliary ADC measurements. */
236  MXM_REG_AUXRUVTHSET = 0x33u, /*!< AUXRUVTHSET is a read and write
237  * accessible register which selects the under voltage (hot) alert set NOLINT
238  * threshold used with Ratiometric Auxiliary ADC measurements. */
239  MXM_REG_AUXOVTHCLR = 0x34u, /*!< AUXOVTHCLR is a read and write
240  * accessible register which selects the over voltage alert clear
241  * threshold used with Absolute Auxiliary ADC measurements. */
242  MXM_REG_AUXAOVTHSET = 0x35u, /*!< AUXAOVTHSET is a read and write
243  * accessible register which selects the over voltage alert set
244  * threshold used with Absolute Auxiliary ADC measurements. */
245  MXM_REG_AUXAUVTHCLR = 0x36u, /*!< AUXAUVTHCLR is a read and write
246  * accessible register which selects the under voltage alert clear
247  * threshold used with Absolute Auxiliary ADC measurements. */
248  MXM_REG_AUXAUVTHSET = 0x37u, /*!< AUXAUVTHSET is a read and write
249  * accessible register which selects the under voltage alert set threshold
250  * used with Absolute Auxiliary ADC measurements. */
251  MXM_REG_COMPOVTH = 0x38u, /*!< COMPOVTH is a read and write
252  * accessible register which selects the cell over voltage alert threshold
253  * for the redundant comparator. */
254  MXM_REG_COMPUVTH = 0x39u, /*!< COMPUVTH is a read and write
255  * accessible register which selects the cell under voltage alert threshold
256  * for the redundant comparator. */
257  MXM_REG_COMPAUXROVTH = 0x3Au, /*!< COMPAUXROVTH is a read and write
258  * accessible register which selects the over voltage (cold) alert threshold NOLINT
259  * applied during Ratiometric Auxiliary comparator measurements. */
260  MXM_REG_COMPAUXRUVTH = 0x3Bu, /*!< COMPAUXRUVTH is a read and write
261  * accessible register which selects the under voltage (hot) alert threshold NOLINT
262  * applied during Ratiometric Auxiliary comparator measurements. */
263  MXM_REG_COMPAUXAOVTH = 0x3Cu, /*!< COMPAUXAOVTH is a read and write
264  * accessible register which selects the over voltage alert threshold
265  * applied during Absolute Auxiliary comparator measurements. */
266  MXM_REG_COMPAUXAUVTH = 0x3Du, /*!< COMPAUXAUVTH is a read and write
267  * accessible register which selects the under voltage alert threshold
268  * applied during Absolute Auxiliary comparator measurements. */
269  MXM_REG_COMPOPNTH = 0x3Eu, /*!< COMPOPNTH is a read and write
270  * accessible register which selects the under voltage alert threshold
271  * applied to Unipolar Cell inputs in Open Diagnostic Mode. */
272  MXM_REG_COMPAUXROPNTH = 0x3Fu, /*!< COMPAUXROPNTH is a read and write
273  * accessible register which selects the under voltage alert threshold
274  * applied to Ratiometric Auxiliary inputs in Open Diagnostic Mode. */
275  MXM_REG_COMPAUXAOPNTH = 0x40u, /*!< COMPAUXAOPNTH is a read and write
276  * accessible register which selects the under voltage alert threshold
277  * applied to Absolute Auxiliary inputs in Open Diagnostic Mode. */
278  MXM_REG_COMPACCOVTH = 0x41u, /*!< COMPACCOVTH is a read and write
279  * accessible register which selects the over voltage alert threshold
280  * applied during comparator accuracy diagnostics. */
281  MXM_REG_COMPACCUVTH = 0x42u, /*!< COMPACCUVTH is a read and write
282  * accessible register which selects the under voltage alert threshold
283  * applied during comparator accuracy diagnostics. */
284  MXM_REG_BALSHRTTHR = 0x43u, /*!< BALSHRTTHR is a read and write
285  * accessible register which selects alert threshold used during the
286  * Balance Switch Short Diagnostic mode. */
287  MXM_REG_BALLOWTHR = 0x44u, /*!< BALLOWTHR is a read and write
288  * accessible register which selects alert low threshold used during the
289  * Balance Switch Open Diagnostic Mode. */
290  MXM_REG_BALHIGHTHR = 0x45u, /*!< BALHIGHTHR is a read and write
291  * accessible register which selects alert High threshold used during the
292  * Balance Switch Open Diagnostic mode. */
293  MXM_REG_CSA = 0x46u, /*!< MAX17852 only: CSA is a read
294  * accessible register which holds the current value for each enabled
295  * individual auxiliary measurement result. */
296  MXM_REG_CELL1 = 0x47u, /*!< CELLn is a read accessible
297  * register which holds the current value for each individual cell
298  * measurement result. */
299  MXM_REG_CELL2 = 0x48u, /*!< CELLn is a read accessible
300  * register which holds the current value for each individual cell
301  * measurement result. */
302  MXM_REG_CELL3 = 0x49u, /*!< CELLn is a read accessible
303  * register which holds the current value for each individual cell
304  * measurement result. */
305  MXM_REG_CELL4 = 0x4Au, /*!< CELLn is a read accessible
306  * register which holds the current value for each individual cell
307  * measurement result. */
308  MXM_REG_CELL5 = 0x4Bu, /*!< CELLn is a read accessible
309  * register which holds the current value for each individual cell
310  * measurement result. */
311  MXM_REG_CELL6 = 0x4Cu, /*!< CELLn is a read accessible
312  * register which holds the current value for each individual cell
313  * measurement result. */
314  MXM_REG_CELL7 = 0x4Du, /*!< CELLn is a read accessible
315  * register which holds the current value for each individual cell
316  * measurement result. */
317  MXM_REG_CELL8 = 0x4Eu, /*!< CELLn is a read accessible
318  * register which holds the current value for each individual cell
319  * measurement result. */
320  MXM_REG_CELL9 = 0x4Fu, /*!< CELLn is a read accessible
321  * register which holds the current value for each individual cell
322  * measurement result. */
323  MXM_REG_CELL10 = 0x50u, /*!< CELLn is a read accessible
324  * register which holds the current value for each individual cell
325  * measurement result. */
326  MXM_REG_CELL11 = 0x51u, /*!< CELLn is a read accessible
327  * register which holds the current value for each individual cell
328  * measurement result. */
329  MXM_REG_CELL12 = 0x52u, /*!< CELLn is a read accessible
330  * register which holds the current value for each individual cell
331  * measurement result. */
332  MXM_REG_CELL13 = 0x53u, /*!< CELLn is a read accessible
333  * register which holds the current value for each individual cell
334  * measurement result. */
335  MXM_REG_CELL14 = 0x54u, /*!< CELLn is a read accessible
336  * register which holds the current value for each individual cell
337  * measurement result. */
338  MXM_REG_BLOCK = 0x55u, /*!< BLOCK is a read accessible
339  * register which holds the current value for the total block
340  * measurement result. */
341  MXM_REG_TOTAL = 0x56u, /*!< TOTAL is a read accessible
342  * register which holds the current value for the sum of all enabled
343  * measurement results within the stack. */
344  MXM_REG_DIAG1 = 0x57u, /*!< DIAG1 is a read-only
345  * register which contains the Diagnostic result requested by the
346  * DIAGCFG:DIAGSEL1 selection taken during the last ADC acquisition. */
347  MXM_REG_DIAG2 = 0x58u, /*!< DIAG2 is a read-only
348  * register which contains the Diagnostic result requested by the
349  * DIAGCFG:DIAGSEL2 selection taken during the last ADC acquisition. */
350  MXM_REG_AUX0 = 0x59u, /*!< AUXn is a read accessible
351  * register which holds the current value for each enabled individual
352  * auxiliary measurement result. */
353  MXM_REG_AUX1 = 0x5Au, /*!< AUXn is a read accessible
354  * register which holds the current value for each enabled individual
355  * auxiliary measurement result. */
356  MXM_REG_AUX2 = 0x5Bu, /*!< AUXn is a read accessible
357  * register which holds the current value for each enabled individual
358  * auxiliary measurement result. */
359  MXM_REG_AUX3 = 0x5Cu, /*!< AUXn is a read accessible
360  * register which holds the current value for each enabled individual
361  * auxiliary measurement result. */
362  MXM_REG_AUX4 = 0x5Du, /*!< MAX17853 only: AUXn is a
363  * read accessible register which holds the current value for each
364  * enabled individual auxiliary measurement result. */
365  MXM_REG_AUX5 = 0x5Eu, /*!< MAX17853 only: AUXn is a
366  * read accessible register which holds the current value for each
367  * enabled individual auxiliary measurement result. */
368  MXM_REG_POLARITYCTRL = 0x5Fu, /*!< POLARITYCTRL is a read and
369  * write accessible register which governs the measurement type
370  * used during scans. In general, Unipolar mode indicates a Cell and
371  * Bipolar mode indicates a Bus-Bar. */
372  MXM_REG_AUXREFCTRL = 0x60u, /*!< AUXREFCTRL is a read and
373  * write accessible register which governs the reference range used
374  * for enabled Auxiliary channels during ADC and COMP acquisition
375  * sequences. */
376  MXM_REG_AUXTIME = 0x61u, /*!< AUXTIME is a read
377  * and write accessible register which governs the setting time
378  * allowed for biasing AUX/GPIO pins prior to measurements. */
379  MXM_REG_ACQCFG = 0x62u, /*!< ACQCFG is a read and write
380  * accessible register which governs several aspects of the
381  * measurement and acquisition procedure. */
382  MXM_REG_BALSWDLY = 0x63u, /*!< BALSWDLY is a read and
383  * write accessible register which selects the delay intervals
384  * used within Manual and Automated Cell Balancing operations
385  * when ADC measurements are requested. */
386  MXM_REG_MEASUREEN1 = 0x64u, /*!< MEASUREEN1 is a read and write
387  * accessible register which governs the channels measured during
388  * ADC and COMP acquisition sequences. */
389  MXM_REG_MEASUREEN2 = 0x65u, /*!< MEASUREEN2 is a read and write
390  * accessible register which governs the auxiliary channels measured
391  * during ADC and COMP acquisition sequences, as well as
392  * IIR initialization. */
393  MXM_REG_SCANCTRL = 0x66u, /*!< SCANCTRL is a read and write
394  * accessible register which governs the internal measurement
395  * acquisitions (scan) requested of the device. The register also manages NOLINT
396  * the handling of data generated as a result of any scan request.
397  *
398  * ADC Scans are used for precision measurements of cell and auxiliary
399  * voltages.
400  *
401  * COMP Scans are used for periodic safety/redundancy checking
402  * of ADC results, and in some cases, enhanced communication efficiency.
403  *
404  * On Demand Calibration will run an internal calibration of the ADC and
405  * update the Calibration Data Registers. All ADC measurements requested
406  * by Scan and Diagnostic Configuration and Control settings will be
407  * ignored.
408  *
409  * Balance Switch and Cell Sense Wire Open ADC Diagnostic Scans are a
410  * special class of ADC Scan. Use of these settings temporarily
411  * overrides other Scan and Diagnostic Configuration and Control settings.
412  * See BALSW and Cell Sense Wire Diagnostics for details. */
413  MXM_REG_ADCTEST1A = 0x67u, /*!< ADCTEST1A is a read and write
414  * accessible register which contains user specified arguments used in ALU
415  * Diagnostics. */
416  MXM_REG_ADCTEST1B = 0x68u, /*!< ADCTEST1B is a read and write
417  * accessible register which contains user specified arguments used in ALU
418  * Diagnostics. */
419  MXM_REG_ADCTEST2A = 0x69u, /*!< ADCTEST2A is a read and write
420  * accessible register which contains user specified arguments used in ALU
421  * Diagnostics. */
422  MXM_REG_ADCTEST2B = 0x6Au, /*!< ADCTEST2B is a read and write
423  * accessible register which contains user specified arguments used in ALU
424  * Diagnostics. */
425  MXM_REG_DIAGCFG = 0x6Bu, /*!< DIAGCFG is a read and write
426  * accessible register which governs diagnostic source and mode options
427  * applied to the internal measurement acquisitions (scans). NOLINT */
428  MXM_REG_CTSTCFG = 0x6Cu, /*!< CTSTCFG is a read and write
429  * accessible register which controls the application of diagnostic
430  * current sources to selected cell input channels. */
431  MXM_REG_AUXSTCFG = 0x6Du, /*!< AUXSTCFG is a read and write
432  * accessible register which controls the application of diagnostic modes
433  * and current source to selected Auxiliary and/or CSA input channels. */
434  MXM_REG_DIAGGENCFG = 0x6Eu, /*!< DIAGGENCFG is a read and write
435  * accessible register which controls the application of general diagnostic
436  * modes to the selected Auxiliary and/or CSA input paths. */
437  MXM_REG_BALSWCTRL = 0x6Fu, /*!< BALSWCTRL is a read and write
438  * accessible register which governs the behavior of the Charge Balancing
439  * Switches in Manual and Auto Cell Balancing modes.
440  *
441  * Write access to this register is blocked during Automated Cell
442  * Balancing operations (CBMODE=001, 1xx). NOLINT */
443  MXM_REG_BALEXP1 = 0x70u, /*!< BALEXPn is a read and write
444  * accessible register which holds the Cell Balancing Expiration Time
445  * for CELLn (using the switch across SWn and SWn-1).
446  *
447  * BALEXP1 sets the Expiration Time for all Group Auto Cell Balancing and
448  * Discharge modes and the Watchdog time out for Manual Cell Balancing mode.
449  *
450  * Write access to this register is blocked during all Cell Balancing
451  * operations (CBMODE!=000). NOLINT */
452  MXM_REG_BALEXP2 = 0x71u, /*!< BALEXPn is a read and write
453  * accessible register which holds the Cell Balancing Expiration Time
454  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
455  * Auto Cell Balancing modes only.
456  *
457  * Write access to this register is blocked during Automatic Cell
458  * Balancing operations (CBMODE=1xx). NOLINT */
459  MXM_REG_BALEXP3 = 0x72u, /*!< BALEXPn is a read and write
460  * accessible register which holds the Cell Balancing Expiration Time
461  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
462  * Auto Cell Balancing modes only.
463  *
464  * Write access to this register is blocked during Automatic Cell
465  * Balancing operations (CBMODE=1xx). NOLINT */
466  MXM_REG_BALEXP4 = 0x73u, /*!< BALEXPn is a read and write
467  * accessible register which holds the Cell Balancing Expiration Time
468  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
469  * Auto Cell Balancing modes only.
470  *
471  * Write access to this register is blocked during Automatic Cell
472  * Balancing operations (CBMODE=1xx). NOLINT */
473  MXM_REG_BALEXP5 = 0x74u, /*!< BALEXPn is a read and write
474  * accessible register which holds the Cell Balancing Expiration Time
475  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
476  * Auto Cell Balancing modes only.
477  *
478  * Write access to this register is blocked during Automatic Cell
479  * Balancing operations (CBMODE=1xx). NOLINT */
480  MXM_REG_BALEXP6 = 0x75u, /*!< BALEXPn is a read and write
481  * accessible register which holds the Cell Balancing Expiration Time
482  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
483  * Auto Cell Balancing modes only.
484  *
485  * Write access to this register is blocked during Automatic Cell
486  * Balancing operations (CBMODE=1xx). NOLINT */
487  MXM_REG_BALEXP7 = 0x76u, /*!< BALEXPn is a read and write
488  * accessible register which holds the Cell Balancing Expiration Time
489  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
490  * Auto Cell Balancing modes only.
491  *
492  * Write access to this register is blocked during Automatic Cell
493  * Balancing operations (CBMODE=1xx). NOLINT */
494  MXM_REG_BALEXP8 = 0x77u, /*!< BALEXPn is a read and write
495  * accessible register which holds the Cell Balancing Expiration Time
496  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
497  * Auto Cell Balancing modes only.
498  *
499  * Write access to this register is blocked during Automatic Cell
500  * Balancing operations (CBMODE=1xx). NOLINT */
501  MXM_REG_BALEXP9 = 0x78u, /*!< BALEXPn is a read and write
502  * accessible register which holds the Cell Balancing Expiration Time
503  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
504  * Auto Cell Balancing modes only.
505  *
506  * Write access to this register is blocked during Automatic Cell
507  * Balancing operations (CBMODE=1xx). NOLINT */
508  MXM_REG_BALEXP10 = 0x79u, /*!< BALEXPn is a read and write
509  * accessible register which holds the Cell Balancing Expiration Time
510  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
511  * Auto Cell Balancing modes only.
512  *
513  * Write access to this register is blocked during Automatic Cell
514  * Balancing operations (CBMODE=1xx). NOLINT */
515  MXM_REG_BALEXP11 = 0x7Au, /*!< BALEXPn is a read and write
516  * accessible register which holds the Cell Balancing Expiration Time
517  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
518  * Auto Cell Balancing modes only.
519  *
520  * Write access to this register is blocked during Automatic Cell
521  * Balancing operations (CBMODE=1xx). NOLINT */
522  MXM_REG_BALEXP12 = 0x7Bu, /*!< BALEXPn is a read and write
523  * accessible register which holds the Cell Balancing Expiration Time
524  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
525  * Auto Cell Balancing modes only.
526  *
527  * Write access to this register is blocked during Automatic Cell
528  * Balancing operations (CBMODE=1xx). NOLINT */
529  MXM_REG_BALEXP13 = 0x7Cu, /*!< BALEXPn is a read and write
530  * accessible register which holds the Cell Balancing Expiration Time
531  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
532  * Auto Cell Balancing modes only.
533  *
534  * Write access to this register is blocked during Automatic Cell
535  * Balancing operations (CBMODE=1xx). NOLINT */
536  MXM_REG_BALEXP14 = 0x7Du, /*!< BALEXPn is a read and write
537  * accessible register which holds the Cell Balancing Expiration Time
538  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
539  * Auto Cell Balancing modes only.
540  *
541  * Write access to this register is blocked during Automatic Cell
542  * Balancing operations (CBMODE=1xx). NOLINT */
543  MXM_REG_BALAUTOUVTHR = 0x7Eu, /*!< BALAUTOUVTHR is a read and write
544  * accessible register which selects the cell under voltage exit threshold
545  * for the ADC when used in Automated Cell Balancing operations.
546  *
547  * A write to this register allows direct setting or automatic selection
548  * of this threshold.
549  *
550  * Write access to this register is blocked during Automatic Cell
551  * Balancing operations (CBMODE=1xx). Also, during active measurement scans, NOLINT
552  * all writes with CBUVMINCELL=1 will be blocked and will result in ALRTRJCT NOLINT
553  * being issued (since the MINCELL data may be altered as a result of the NOLINT
554  * scan in progress).
555  *
556  * A read from this register will display the current value of the threshold
557  * and the method used for its selection. */
558  MXM_REG_BALDLYCTRL = 0x7Fu, /*!< BALDLYCTRL is a read and write
559  * accessible register which selects the delay/timing intervals used within
560  * Automated Cell Balancing operations.
561  *
562  * Write access to this register is blocked during Automated Cell Balancing
563  * operations (CBMODE=001, 1xx). NOLINT */
564  MXM_REG_BALCTRL = 0x80u, /*!< BALCTRL is a read and write
565  * accessible register which initiates and controls all internal Cell
566  * Balancing modes and operations.
567  *
568  * Any write to this register to a mode other than CBMODE=000 (Disable) NOLINT
569  * will restart the CBTIMER at zero and launch the requested mode of
570  * operation. */
571  MXM_REG_BALSTAT = 0x81u, /*!< BALSTAT is a read accessible
572  * register which allows the monitoring of any Automated Cell Balancing
573  * operations currently in progress.
574  *
575  * Once a CBMODE is initiated, all status bits persist and are cleared
576  * only when CBMODE is written to 000 (Disabled) or when a new CBMODE
577  * operation is initiated via CBSTART. */
578  MXM_REG_BALUVSTAT = 0x82u, /*!< BALUVSTAT is a read accessible
579  * register which relates current summary information on the Cell
580  * voltages vs. the CBUVTHR undervoltage threshold. */
581  MXM_REG_BALDATA = 0x83u, /*!< BALDATA is a read accessible
582  * register which relates current summary information on the Cell voltage
583  * vs. the CBUVTHR undervoltage threshold. */
584  MXM_REG_I2CPNTR = 0x84u, /*!< MAX17852 only: I2CPNTR is a
585  * read and write accessible register which contains two Pointer bytes
586  * (Register Addresses) available for I2C Master transactions.
587  *
588  * Once I2CSEND initiates a read or write transaction, attempts to write
589  * I2CPNTR during the transaction will be ignored and will case an
590  * I2CRJCT fault to be issued. */
591  MXM_REG_I2CWDATA1 = 0x85u, /*!< MAX17852 only: I2CWDATA1 is a
592  * read and write accessible register which contains the upper data bytes
593  * available for I2C Master Write Mode transactions.
594  *
595  * Once I2CSEND initiates an I2C read or write transaction, attempts to
596  * write I2CWDATA1 during the transaction will be ignored and will cause
597  * an I2CRJCT fault to be issued. */
598  MXM_REG_I2CWDATA2 = 0x86u, /*!< MAX17852 only: I2CWDATA2 is a
599  * read and write accessible register which contains the lower data bytes
600  * available for I2C Master Write Mode transactions.
601  *
602  * Once I2CSEND initiates an I2C read or write transaction, attempts to
603  * write I2CWDATA2 during the transaction will be ignored and will cause
604  * an I2CRJCT fault to be issued. */
605  MXM_REG_I2CRDATA1 = 0x87u, /*!< MAX17852 only: I2CRDATA1 is a
606  * read accessible register which contains the upper data bytes received
607  * for I2C Master Read Mode transactions.
608  *
609  * Note during I2C read transactions, data is updated as each byte is
610  * received/acknowledged, so reading back this register during active
611  * I2C read transactions will cause an I2CRJCT fault to be issued. */
612  MXM_REG_I2CRDATA2 = 0x88u, /*!< MAX17852 only: I2CRDATA2 is a
613  * read accessible register which contains the lower data bytes received
614  * for I2C Master Read Mode transactions.
615  *
616  * Note during I2C read transactions, data is updated as each byte is
617  * received/acknowledged, so reading back this register during active
618  * I2C read transactions will cause an I2CRJCT fault to be issued. */
619  MXM_REG_I2CCFG = 0x89u, /*!< MAX17852 only: I2CCFG is a
620  * read and write accessible register which configures I2C Master
621  * modes and transaction formats.
622  *
623  * Once I2CSEND initiates a read or write transaction, attempts to
624  * write I2CCFG during the transaction will be ignored and will cause
625  * and I2CRJCT fault to be issued. */
626  MXM_REG_I2CSTAT = 0x8Au, /*!< MAX17852 only: I2CSTAT is
627  * a read and write accessible register which shows the current status
628  * of the I2C Master.
629  *
630  * The I2CSTATUS bits are updated in real time, indicating the current
631  * state of the I2C Master and any requested transaction. This status
632  * can be cleared by write operations and modified by transaction progress
633  * or subsequent transaction requests.
634  *
635  * The second byte contains I2C Fault bits, indicating a fault was
636  * observed during an I2C transaction. These bits are updated as they
637  * occur and are only cleared by writing to zero. Several faults may
638  * occur during a corrupted transaction, so it is best to wait until
639  * I2CSTATUS reads 10 (Transaction Error) to ensure all errors have NOLINT
640  * been reported.
641  *
642  * While not advisable, if further I2C transactions are requested before
643  * the I2C Fault bits from previous transactions are read back and cleared,
644  * a cumulative history of faults will be listed, even if subsequent
645  * transactions are successful. */
646  MXM_REG_I2CSEND = 0x8Bu, /*!< MAX17852 only: I2CSEND is a
647  * read and write accessible register which configures and initiates
648  * an I2C Master transaction.
649  *
650  * A write to this register will initiate an I2C Master transaction.
651  * Only one transaction is supported at any given time. If a write to
652  * I2CSEND occurs during an active I2C transaction already in progress,
653  * the latest transaction request will be ignored and the I2CSEND
654  * contents will not be updated. If this occurs, an I2CRJCT fault will
655  * be issued.
656  *
657  * A read from this register will readback the current contents. This
658  * will represent the last transaction request accepted by the I2C Master. */
659  MXM_REG_ID1 = 0x8Cu, /*!< ID1 is a read accessible register
660  * which contains the 2 LSBytes of the unique Device ID stored in ROM and
661  * subject to ROMCRC validation. */
662  MXM_REG_ID2 = 0x8Du, /*!< ID2 is a read accessible register
663  * which contains the 2 MSBytes of the unique Device ID stored in ROM and
664  * subject to ROMCRC validation. */
665  MXM_REG_OTP2 = 0x8Eu, /*!< Factory Calibration Data ROM
666  * and subject to ROMCRC validation. */
667  MXM_REG_OTP3 = 0x8Fu, /*!< Factory Calibration Data ROM
668  * and subject to ROMCRC validation. */
669  MXM_REG_OTP4 = 0x90u, /*!< Factory Calibration Data ROM
670  * and subject to ROMCRC validation. */
671  MXM_REG_OTP5 = 0x91u, /*!< Factory Calibration Data ROM
672  * and subject to ROMCRC validation. */
673  MXM_REG_OTP6 = 0x92u, /*!< Factory Calibration Data ROM
674  * and subject to ROMCRC validation. */
675  MXM_REG_OTP7 = 0x93u, /*!< Factory Calibration Data ROM
676  * and subject to ROMCRC validation. */
677  MXM_REG_OTP8 = 0x94u, /*!< Factory Calibration Data ROM
678  * and subject to ROMCRC validation. */
679  MXM_REG_OTP9 = 0x95u, /*!< Factory Calibration Data ROM
680  * and subject to ROMCRC validation. */
681  MXM_REG_OTP10 = 0x96u, /*!< Factory Calibration Data ROM
682  * and subject to ROMCRC validation. */
683  MXM_REG_OTP11 = 0x97u, /*!< Factory Calibration Data ROM
684  * and subject to ROMCRC validation. */
685  MXM_REG_OTP12 = 0x98u, /*!< Factory Calibration Data ROM
686  * and subject to ROMCRC validation. */
688 
689 /**
690  * @brief Type for register access for monitoring ICs.
691  */
692 typedef uint16_t MXM_REG_BM;
693 
694 /**
695  * @brief Define enumeration values for bitmasks
696  * @details Generates a bitmask from start to end.
697  * Examples:
698  * - 0000 0001b == MXM_REG_BIT_DEFN(0, 0)
699  * - 0000 1000b == MXM_REG_BIT_DEFN(3, 3)
700  * - 0011 1000b == MXM_REG_BIT_DEFN(3, 5)
701  */
702 #define MXM_REG_BIT_DEFN(start, end) ((((MXM_REG_BM)1u << ((end) - (start) + 1u)) - 1u) << (start))
703 
704 /**
705  * @defgroup mxm_bm Bitmasks for register access of MAX1785x
706  * @{
707  */
708 /**
709  * @brief Monitoring Register Null byte
710  */
711 #define MXM_BM_NULL ((MXM_REG_BM)0x00u)
712 /**
713  * @brief Monitoring Register LSB
714  */
715 #define MXM_BM_LSB ((MXM_REG_BM)MXM_REG_BIT_DEFN(0u, 7u))
716 /**
717  * @brief Monitoring Register MSB
718  */
719 #define MXM_BM_MSB ((MXM_REG_BM)MXM_REG_BIT_DEFN(8u, 15u))
720 /**
721  * @brief All bits of monitoring register
722  */
723 #define MXM_BM_WHOLE_REG ((MXM_REG_BM)MXM_REG_BIT_DEFN(0u, 15u))
724 /**
725  * @brief Monitoring Register Version/Model
726  */
727 #define MXM_REG_VERSION_MOD ((MXM_REG_BM)MXM_REG_BIT_DEFN(4u, 15u))
728 /**
729  * @brief Monitoring Register Version/Silicon Version
730  */
731 #define MXM_REG_VERSION_VER ((MXM_REG_BM)MXM_REG_BIT_DEFN(0u, 3u))
732 /**
733  * @brief Monitoring Register 14bit ADC value
734  */
735 #define MXM_REG_ADC_14BIT_VALUE ((MXM_REG_BM)MXM_REG_BIT_DEFN(2u, 15u))
736 
737 /**
738  * @}
739  */
740 
741 /*========== Extern Constant and Variable Declarations ======================*/
742 
743 /*========== Extern Function Prototypes =====================================*/
744 
745 /*========== Externalized Static Functions Prototypes (Unit Test) ===========*/
746 
747 #endif /* FOXBMS__MXM_REGISTER_MAP_H_ */
General macros and definitions for the whole platform.
enum MXM_REG_NAME MXM_REG_NAME_e
MAX1785x register names.
MXM_REG_NAME
MAX1785x register names.
@ MXM_REG_AUXREFCTRL
@ MXM_REG_CTSTCFG
@ MXM_REG_COMPOVTH
@ MXM_REG_ADCTEST2A
@ MXM_REG_MINMAXCELL
@ MXM_REG_PACKCFG
@ MXM_REG_ADCTEST1B
@ MXM_REG_CELL1
@ MXM_REG_CELL4
@ MXM_REG_AUXSTCFG
@ MXM_REG_BALSHRTTHR
@ MXM_REG_GPIOCFG
@ MXM_REG_BIPUVTHSET
@ MXM_REG_BALEXP11
@ MXM_REG_MSMTCH
@ MXM_REG_STATUS1
@ MXM_REG_ALRTAUXUV
@ MXM_REG_BALAUTOUVTHR
@ MXM_REG_BALEXP6
@ MXM_REG_AUX4
@ MXM_REG_STATUS3
@ MXM_REG_CSAUVTHSET
@ MXM_REG_STATUS2
@ MXM_REG_BALEXP2
@ MXM_REG_OTP4
@ MXM_REG_AUXROVTHSET
@ MXM_REG_OTP3
@ MXM_REG_I2CRDATA2
@ MXM_REG_SWACTION
@ MXM_REG_COMPACCOVTH
@ MXM_REG_AUX0
@ MXM_REG_CSA
@ MXM_REG_ALRTSUM
@ MXM_REG_CELL10
@ MXM_REG_OTP5
@ MXM_REG_BALEXP13
@ MXM_REG_BALLOWTHR
@ MXM_REG_ALRTUVCELL
@ MXM_REG_I2CCFG
@ MXM_REG_OVTHCLR
@ MXM_REG_BALEXP5
@ MXM_REG_ALRTAUXOVEN
@ MXM_REG_COMPACCUVTH
@ MXM_REG_I2CWDATA2
@ MXM_REG_UVTHSET
@ MXM_REG_BALEXP10
@ MXM_REG_OTP9
@ MXM_REG_AUX3
@ MXM_REG_BIPOVTHSET
@ MXM_REG_ALRTOVCELL
@ MXM_REG_BALEXP1
@ MXM_REG_COMPAUXAOPNTH
@ MXM_REG_UVTHCLR
@ MXM_REG_SCANCTRL
@ MXM_REG_BALSTAT
@ MXM_REG_BIPUVTHCLR
@ MXM_REG_CSAOVTHSET
@ MXM_REG_ALRTIRQEN
@ MXM_REG_OTP11
@ MXM_REG_VERSION
@ MXM_REG_MEASUREEN2
@ MXM_REG_ALRTCOMPAUXOV
@ MXM_REG_I2CSTAT
@ MXM_REG_COMPAUXAOVTH
@ MXM_REG_ID1
@ MXM_REG_AUX5
@ MXM_REG_BALEXP14
@ MXM_REG_I2CPNTR
@ MXM_REG_AUXAUVTHSET
@ MXM_REG_ALRTAUXUVEN
@ MXM_REG_CELL9
@ MXM_REG_AUXTIME
@ MXM_REG_BLOCK
@ MXM_REG_DEVCFG2
@ MXM_REG_ALRTAUXOV
@ MXM_REG_COMPOPNTH
@ MXM_REG_COMPAUXRUVTH
@ MXM_REG_OTP10
@ MXM_REG_AUXGPIOCFG
@ MXM_REG_I2CWDATA1
@ MXM_REG_BLKOVTHCLR
@ MXM_REG_AUXAOVTHSET
@ MXM_REG_OTP7
@ MXM_REG_CELL3
@ MXM_REG_BALEXP8
@ MXM_REG_FMEA1
@ MXM_REG_CSAUVTHCLR
@ MXM_REG_I2CRDATA1
@ MXM_REG_ID2
@ MXM_REG_BALEXP9
@ MXM_REG_ALRTCALTST
@ MXM_REG_TOTAL
@ MXM_REG_BALUVSTAT
@ MXM_REG_CELL14
@ MXM_REG_CELL6
@ MXM_REG_OTP8
@ MXM_REG_I2CSEND
@ MXM_REG_ACQCFG
@ MXM_REG_BALCTRL
@ MXM_REG_CELL2
@ MXM_REG_BLKUVTHCLR
@ MXM_REG_BALEXP7
@ MXM_REG_CSAOVTHCLR
@ MXM_REG_DIAG1
@ MXM_REG_BIPOVTHCLR
@ MXM_REG_BALDLYCTRL
@ MXM_REG_ALRTUVEN
@ MXM_REG_BLKUVTHSET
@ MXM_REG_BLKOVTHSET
@ MXM_REG_COMPAUXROVTH
@ MXM_REG_DIAG2
@ MXM_REG_BALEXP3
@ MXM_REG_DIAGCFG
@ MXM_REG_ADCTEST2B
@ MXM_REG_CELL11
@ MXM_REG_AUXAUVTHCLR
@ MXM_REG_ALRTAUXPRTCT
@ MXM_REG_MEASUREEN1
@ MXM_REG_BALSWDLY
@ MXM_REG_BALDATA
@ MXM_REG_CELL5
@ MXM_REG_OTP2
@ MXM_REG_POLARITYCTRL
@ MXM_REG_CELL13
@ MXM_REG_OVTHSET
@ MXM_REG_AUX2
@ MXM_REG_DIAGGENCFG
@ MXM_REG_BALSWCTRL
@ MXM_REG_OTP6
@ MXM_REG_FMEA2
@ MXM_REG_COMPAUXROPNTH
@ MXM_REG_AUX1
@ MXM_REG_CELL7
@ MXM_REG_AUXOVTHCLR
@ MXM_REG_ALRTCOMPOV
@ MXM_REG_AUXRUVTHCLR
@ MXM_REG_ALRTCOMPAUXUV
@ MXM_REG_ADDRESS
@ MXM_REG_BALEXP12
@ MXM_REG_AUXROVTHCLR
@ MXM_REG_ALRTCOMPUV
@ MXM_REG_DEVCFG1
@ MXM_REG_OTP12
@ MXM_REG_ALRTOVEN
@ MXM_REG_ADCTEST1A
@ MXM_REG_COMPUVTH
@ MXM_REG_CELL8
@ MXM_REG_AUXRUVTHSET
@ MXM_REG_COMPAUXAUVTH
@ MXM_REG_CELL12
@ MXM_REG_BALHIGHTHR
@ MXM_REG_ALRTBALSW
@ MXM_REG_BALEXP4
uint16_t MXM_REG_BM
Type for register access for monitoring ICs.