foxBMS
1.1.0
The foxBMS Battery Management System API Documentation
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Header for the driver for the FRAM module. More...
#include "fram_cfg.h"
#include "nxpfs85xx_cfg.h"
#include "sbc_fs8x.h"
#include "sbc_fs8x_communication.h"
#include "spi.h"
Go to the source code of this file.
Data Structures | |
struct | FS85X_FS_REGISTERS |
struct | FS85X_MAIN_REGISTERS |
struct | FS85X_FIN_CONFIGURATION |
struct | SBC_NVRAM_INFO |
struct | FS85xx_STATE |
Typedefs | |
typedef struct FS85X_FS_REGISTERS | FS85X_FS_REGISTER_s |
typedef struct FS85X_MAIN_REGISTERS | FS85X_MAIN_REGISTERS_s |
typedef enum FS85X_OPERATION_MODE | FS85X_OPERATION_MODE_e |
typedef struct FS85X_FIN_CONFIGURATION | FS85X_FIN_CONFIGURATION_s |
typedef struct SBC_NVRAM_INFO | SBC_NVRAM_INFO_s |
typedef struct FS85xx_STATE | FS85xx_STATE_s |
Enumerations | |
enum | FS85X_OPERATION_MODE { SBC_NORMAL_MODE , SBC_DEBUG_MODE } |
Functions | |
STD_RETURN_TYPE_e | FS85X_InitFS (FS85xx_STATE_s *pInstance) |
Configures SBC during INIT_FS phase. More... | |
STD_RETURN_TYPE_e | FS85X_Init_ReqWDGRefreshes (FS85xx_STATE_s *pInstance, uint8_t *requiredWatchdogRefreshes) |
Calculates the number of required watchdog refresh to reset fault error counter. More... | |
STD_RETURN_TYPE_e | FS85X_CheckFaultErrorCounter (FS85xx_STATE_s *pInstance) |
Checks if fault error counter is zero. More... | |
STD_RETURN_TYPE_e | FS85X_SafetyPathChecks (FS85xx_STATE_s *pInstance) |
Performs SBC safety path checks. More... | |
STD_RETURN_TYPE_e | SBC_TriggerWatchdog (FS85xx_STATE_s *pInstance) |
Trigger watchdog. More... | |
Variables | |
FS85xx_STATE_s | fs85xx_mcuSupervisor |
Header for the driver for the FRAM module.
SPDX-License-Identifier: BSD-3-Clause
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It must always be used when creating new c header files.
Definition in file nxpfs85xx.h.
typedef struct FS85X_FIN_CONFIGURATION FS85X_FIN_CONFIGURATION_s |
struct for FIN configuration
typedef struct FS85X_FS_REGISTERS FS85X_FS_REGISTER_s |
struct for fail-safe registers for register description see datasheet FS84_FS85 - Rev. 3.0 - 9 April 2019
typedef struct FS85X_MAIN_REGISTERS FS85X_MAIN_REGISTERS_s |
struct for main registers for register description see datasheet FS84_FS85 - Rev. 3.0 - 9 April 2019
typedef enum FS85X_OPERATION_MODE FS85X_OPERATION_MODE_e |
typedef struct FS85xx_STATE FS85xx_STATE_s |
state struct to create SBC instance
typedef struct SBC_NVRAM_INFO SBC_NVRAM_INFO_s |
stores a pointer to the persistent entry in the FRAM
enum FS85X_OPERATION_MODE |
Enumerator | |
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SBC_NORMAL_MODE | |
SBC_DEBUG_MODE |
Definition at line 109 of file nxpfs85xx.h.
STD_RETURN_TYPE_e FS85X_CheckFaultErrorCounter | ( | FS85xx_STATE_s * | pInstance | ) |
Checks if fault error counter is zero.
[in,out] | pInstance | SBC instance where fault error counter is checked |
Definition at line 898 of file nxpfs85xx.c.
STD_RETURN_TYPE_e FS85X_Init_ReqWDGRefreshes | ( | FS85xx_STATE_s * | pInstance, |
uint8_t * | requiredWatchdogRefreshes | ||
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Calculates the number of required watchdog refresh to reset fault error counter.
[in,out] | pInstance | SBC instance that is initialized |
[out] | requiredWatchdogRefreshes | number of required good watchdog refreshes |
Clear the fault error counter to 0 with consecutive good WD refreshes. The watchdog refresh counter is used to decrement the fault error counter. Each time the watchdog is properly refreshed, the watchdog refresh counter is incremented by '1'. Each time the watchdog refresh counter reaches its maximum value ('6' by default) and if next WD refresh is also good, the fault error counter is decremented by '1'. Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog, the watchdog refresh counter is reset to '0'.
Read out FS_I_WD_CFG register to get watchdog refresh counter limit and value
Get refresh counter value
Get refresh counter limit register value
Get fault error counter
Get number of required watchdog refreshes to clear fault error counter to 0
Definition at line 844 of file nxpfs85xx.c.
STD_RETURN_TYPE_e FS85X_InitFS | ( | FS85xx_STATE_s * | pInstance | ) |
Configures SBC during INIT_FS phase.
Checks first if SBC currently is in INIT_FS phase and if not transfers SBC back into INIT_FS. Verifies basic checks, configures fail-safe registers and closes INIT_FS afterwards.
[in,out] | pInstance | SBC instance that is initialized |
First: Verify following conditions:
Second: Configure FS_I and FS_I_NOT registers
Third: Execute
The FS85 is now ready. If everything is OK for the MCU, it can release its own safety path and the ECU starts.
1.: Verify LBIST and ABIST1
Read FS STATES register
2.: Check if debug mode is active
3.: Verify that no OPT CRC error
-----— Second: Configure fail-safe init registers ---------------—
Check if SBC is in FS_INIT state, if not switch SBC in FS_INIT state. Specific configurations can only be done in FS_INIT state
1.: Configure VCOREMON_OV_UV impact on RSTB and FS0B
2.: Configure VDDIO_OV_UV impact on RSTB and FS0B
4.: Configure ABIST2 assignment
Select VCOREMON_OV options:
Select VCOREMON_UV options:
Select VDDIO_OV options:
Select VDDIO_UV options:
Select ABIST2 options:
3.: Configure VMONx_OV_UV impact on RSTB and FS0B
Select VMONx_OV options:
Select VMONx_UV options:
5.: Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and FS0B. Ensure that the configuration does not violate the FTTI requirement at system level.
WD window period options:
WD window duty cycle options:
WD fault recovery strategy
6.: Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value
Configure the RSTB pulse duration
Configure FS0B short to high impact on RSTB
Fault Error Counter limit options:
Fault Error Counter impact options:
7.: RSTB pulse duration options:
10.: FS0B short to high impact on RSTB options:
After POR fault-error counter is set to 1 on default, it is reset after two consecutive good WD refreshes. This part of the register is read-only so a write access has no influence. Set this bit for a successful comparison between written and read register value
8.: Configure MCU FCCU error monitoring and its impact on RSTB and FS0B
9.: Configure Ext. IC error monitoring and its impact on RSTB and FS0B
MCU FCCU error monitoring options:
Ext. IC error monitoring options:
1.: Close INIT_FS by sending the first good WD refresh
2.: Execute ABIST2 and verify it is pass
ABIST2 is executed automatically after closing of INIT_FS, duration: 1.2ms max
3.: Clear all the flags by writing in FS_DIAG_SAFETY
Flags are cleared by writting '1' to register
Clear all the flags by writing in FS_OVUVREG_STATUS
Flags are cleared by writting '1' to register
Clear flags FLAG1 register
Clear flags FLAG2 register
Read out all registers for debug purpose
Definition at line 461 of file nxpfs85xx.c.
STD_RETURN_TYPE_e FS85X_SafetyPathChecks | ( | FS85xx_STATE_s * | pInstance | ) |
Performs SBC safety path checks.
Function perform safety path checks for FIN, FS0B and RSTB to ensure that all pins work as expected
[in,out] | pInstance | where the safety paths are checked |
Definition at line 910 of file nxpfs85xx.c.
STD_RETURN_TYPE_e SBC_TriggerWatchdog | ( | FS85xx_STATE_s * | pInstance | ) |
Trigger watchdog.
Triggers watchdog of passed SBC instance and verify if it was good refresh within the configured window
[in,out] | pInstance | SBC instance where the watchdog is triggered |
Definition at line 973 of file nxpfs85xx.c.
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extern |
Definition at line 80 of file nxpfs85xx.c.