foxBMS  1.1.1
The foxBMS Battery Management System API Documentation
Data Structures | Typedefs | Enumerations | Functions | Variables
nxpfs85xx.h File Reference

Header for the driver for the FRAM module. More...

#include "fram_cfg.h"
#include "nxpfs85xx_cfg.h"
#include "sbc_fs8x.h"
#include "sbc_fs8x_communication.h"
#include "spi.h"
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Data Structures

struct  FS85X_FS_REGISTERS
 
struct  FS85X_MAIN_REGISTERS
 
struct  FS85X_FIN_CONFIGURATION
 
struct  SBC_NVRAM_INFO
 
struct  FS85xx_STATE
 

Typedefs

typedef struct FS85X_FS_REGISTERS FS85X_FS_REGISTER_s
 
typedef struct FS85X_MAIN_REGISTERS FS85X_MAIN_REGISTERS_s
 
typedef enum FS85X_OPERATION_MODE FS85X_OPERATION_MODE_e
 
typedef struct FS85X_FIN_CONFIGURATION FS85X_FIN_CONFIGURATION_s
 
typedef struct SBC_NVRAM_INFO SBC_NVRAM_INFO_s
 
typedef struct FS85xx_STATE FS85xx_STATE_s
 

Enumerations

enum  FS85X_OPERATION_MODE { SBC_NORMAL_MODE , SBC_DEBUG_MODE }
 

Functions

STD_RETURN_TYPE_e FS85X_InitFS (FS85xx_STATE_s *pInstance)
 Configures SBC during INIT_FS phase. More...
 
STD_RETURN_TYPE_e FS85X_Init_ReqWDGRefreshes (FS85xx_STATE_s *pInstance, uint8_t *requiredWatchdogRefreshes)
 Calculates the number of required watchdog refresh to reset fault error counter. More...
 
STD_RETURN_TYPE_e FS85X_CheckFaultErrorCounter (FS85xx_STATE_s *pInstance)
 Checks if fault error counter is zero. More...
 
STD_RETURN_TYPE_e FS85X_SafetyPathChecks (FS85xx_STATE_s *pInstance)
 Performs SBC safety path checks. More...
 
STD_RETURN_TYPE_e SBC_TriggerWatchdog (FS85xx_STATE_s *pInstance)
 Trigger watchdog. More...
 

Variables

FS85xx_STATE_s fs85xx_mcuSupervisor
 

Detailed Description

Header for the driver for the FRAM module.

Copyright
© 2010 - 2021, Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V. All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

We kindly request you to use one or more of the following phrases to refer to foxBMS in your hardware, software, documentation or advertising materials:

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Author
foxBMS Team
Date
2020-03-18 (date of creation)
Updated
2020-03-18 (date of last update)
Prefix
FS85X

It must always be used when creating new c header files.

Definition in file nxpfs85xx.h.

Typedef Documentation

◆ FS85X_FIN_CONFIGURATION_s

typedef struct FS85X_FIN_CONFIGURATION FS85X_FIN_CONFIGURATION_s

struct for FIN configuration

◆ FS85X_FS_REGISTER_s

typedef struct FS85X_FS_REGISTERS FS85X_FS_REGISTER_s

struct for fail-safe registers for register description see datasheet FS84_FS85 - Rev. 3.0 - 9 April 2019

◆ FS85X_MAIN_REGISTERS_s

typedef struct FS85X_MAIN_REGISTERS FS85X_MAIN_REGISTERS_s

struct for main registers for register description see datasheet FS84_FS85 - Rev. 3.0 - 9 April 2019

◆ FS85X_OPERATION_MODE_e

typedef enum FS85X_OPERATION_MODE FS85X_OPERATION_MODE_e

◆ FS85xx_STATE_s

typedef struct FS85xx_STATE FS85xx_STATE_s

state struct to create SBC instance

◆ SBC_NVRAM_INFO_s

typedef struct SBC_NVRAM_INFO SBC_NVRAM_INFO_s

stores a pointer to the persistent entry in the FRAM

Enumeration Type Documentation

◆ FS85X_OPERATION_MODE

enum FS85X_OPERATION_MODE
Enumerator
SBC_NORMAL_MODE 
SBC_DEBUG_MODE 

Definition at line 109 of file nxpfs85xx.h.

Function Documentation

◆ FS85X_CheckFaultErrorCounter()

STD_RETURN_TYPE_e FS85X_CheckFaultErrorCounter ( FS85xx_STATE_s *  pInstance)

Checks if fault error counter is zero.

Parameters
[in,out]pInstanceSBC instance where fault error counter is checked
Returns
STD_OK if fault error counter equals zero, otherwise STD_NOT_OK

Definition at line 898 of file nxpfs85xx.c.

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◆ FS85X_Init_ReqWDGRefreshes()

STD_RETURN_TYPE_e FS85X_Init_ReqWDGRefreshes ( FS85xx_STATE_s *  pInstance,
uint8_t *  requiredWatchdogRefreshes 
)

Calculates the number of required watchdog refresh to reset fault error counter.

Parameters
[in,out]pInstanceSBC instance that is initialized
[out]requiredWatchdogRefreshesnumber of required good watchdog refreshes
Returns
STD_OK if required watchdog refreshes were calculated successfully, otherwise STD_NOT_OK

Clear the fault error counter to 0 with consecutive good WD refreshes. The watchdog refresh counter is used to decrement the fault error counter. Each time the watchdog is properly refreshed, the watchdog refresh counter is incremented by '1'. Each time the watchdog refresh counter reaches its maximum value ('6' by default) and if next WD refresh is also good, the fault error counter is decremented by '1'. Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog, the watchdog refresh counter is reset to '0'.

Read out FS_I_WD_CFG register to get watchdog refresh counter limit and value

Get refresh counter value

Get refresh counter limit register value

Get fault error counter

Get number of required watchdog refreshes to clear fault error counter to 0

Definition at line 844 of file nxpfs85xx.c.

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◆ FS85X_InitFS()

STD_RETURN_TYPE_e FS85X_InitFS ( FS85xx_STATE_s *  pInstance)

Configures SBC during INIT_FS phase.

Checks first if SBC currently is in INIT_FS phase and if not transfers SBC back into INIT_FS. Verifies basic checks, configures fail-safe registers and closes INIT_FS afterwards.

Parameters
[in,out]pInstanceSBC instance that is initialized
Returns
STD_OK if all checks were successful and SBC configured correctly, otherwise STD_NOT_OK

First: Verify following conditions:

  1. Verify LBIST (logical-built-in-self-test) and ABIST1 (analog-built-in-self-test1) are pass
  2. Verify Debug mode is not activated
  3. Verify there is no OTP CRC error
  4. Verify PGOOD was released: PGOOD is connected to power-on-reset of the MCU

Second: Configure FS_I and FS_I_NOT registers

  • Write the desired data in the FS_I_Register_A (DATA)
  • Write the opposite in the FS_I_NOT_Register_A (DATA_NOT)
  • Only the utility bits must be inverted in the DATA_NOT content. The RESERVED bits are not considered and can be written at '0'. If the comparison result is correct, then the REG_CORRUPT is set to '0'. If the comparison result is wrong, then the REG_CORRUPT bit is set to '1'. The REG_CORRUPT monitoring is active as soon as the INIT_FS is closed by the first good watchdog refresh. INIT_FS must be closed by the first good watchdog refresh before 256ms timeout.
  1. Configure VCOREMON_OV_UV impact on RSTB and FS0B
  2. Configure VDDIO_OV_UV impact on RSTB and FS0B
  3. Configure VMONx_OV_UV impact on RSTB and FS0B
  4. Configure ABIST2 assignment
  5. Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and FS0B. Ensure that the configuration does not violate the FTTI requirement at system level.
  6. Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value
  7. Configure the RSTB pulse duration
  8. Configure MCU FCCU error monitoring and its impact on RSTB and FS0B
  9. Configure Ext. IC error monitoring and its impact on RSTB and FS0B 10.Configure FS0B short to high impact on RSTB

Third: Execute

  1. Close INIT_FS by sending the first good WD refresh
  2. Execute ABIST2 and verify it is pass
  3. Clear all the flags by writing in FS_DIAG_SAFETY, FS_OVUVREG_STATUS
  4. Clear the fault error counter to 0 with consecutive good WD refresh
  5. Perform RSTB path check (repeat steps 1 to 4 after RSTB is released)
  6. Release FS0B pin
  7. Perform FS0B safety path check
  8. Refresh the WD according to its configuration
  9. Check FS_GRL_FLAGS register after each WD refresh

The FS85 is now ready. If everything is OK for the MCU, it can release its own safety path and the ECU starts.

1.: Verify LBIST and ABIST1

Read FS STATES register

2.: Check if debug mode is active

3.: Verify that no OPT CRC error

-----— Second: Configure fail-safe init registers ---------------—

Check if SBC is in FS_INIT state, if not switch SBC in FS_INIT state. Specific configurations can only be done in FS_INIT state

1.: Configure VCOREMON_OV_UV impact on RSTB and FS0B

2.: Configure VDDIO_OV_UV impact on RSTB and FS0B

4.: Configure ABIST2 assignment

Select VCOREMON_OV options:

  • FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B
  • FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B_RSTB

Select VCOREMON_UV options:

  • FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B
  • FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B_RSTB

Select VDDIO_OV options:

  • FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B
  • FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B_RSTB

Select VDDIO_UV options:

  • FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B
  • FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B_RSTB

Select ABIST2 options:

  • VCOREMON
    • FS8X_FS_I_VCOREMON_ABIST2_NO_ABIST
    • FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST
  • VDDIO
    • FS8X_FS_I_VDDIO_ABIST2_NO_ABIST
    • FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST
  • VMONx (VMON1 - VMON4)
    • FS8X_FS_I_VMONx_ABIST2_NO_ABIST
    • FS8X_FS_I_VMONx_ABIST2_VMONx_BIST

3.: Configure VMONx_OV_UV impact on RSTB and FS0B

Select VMONx_OV options:

  • FS8X_FS_I_VMONx_OV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B
  • FS8X_FS_I_VMONx_OV_FS_IMPACT_FS0B_RSTB

Select VMONx_UV options:

  • FS8X_FS_I_VMONx_UV_FS_IMPACT_NO_EFFECT
  • FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B
  • FS8X_FS_I_VMONx_UV_FS_IMPACT_FS0B_RSTB

5.: Configure the WD window period, the WD window duty cycle, the WD counters limits, and its impact on RSTB and FS0B. Ensure that the configuration does not violate the FTTI requirement at system level.

WD window period options:

  • FS8X_FS_WD_WINDOW_DISABLE
  • FS8X_FS_WD_WINDOW_xxxxMS

WD window duty cycle options:

  • FS8X_FS_WDW_DC_31_25
  • FS8X_FS_WDW_DC_37_5
  • FS8X_FS_WDW_DC_50
  • FS8X_FS_WDW_DC_62_5
  • FS8X_FS_WDW_DC_68_75

WD fault recovery strategy

  • FS8X_FS_WDW_RECOVERY_DISABLE
  • FS8X_FS_WDW_RECOVERY_xxxxMS

6.: Configure the Fault Error Counter limit and its impact on RSTB and FS0B at intermediate value

Configure the RSTB pulse duration

Configure FS0B short to high impact on RSTB

Fault Error Counter limit options:

  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_2
  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_4
  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_6
  • FS8X_FS_I_FLT_ERR_CNT_LIMIT_8

Fault Error Counter impact options:

  • FS8X_FS_I_FLT_ERR_IMPACT_NO_EFFECT
  • FS8X_FS_I_FLT_ERR_IMPACT_FS0B
  • FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB

7.: RSTB pulse duration options:

  • FS8X_FS_I_RSTB_DUR_1MS
  • FS8X_FS_I_RSTB_DUR_10MS

10.: FS0B short to high impact on RSTB options:

  • FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION
  • FS8X_FS_I_FS0B_SC_HIGH_CFG_RESET_ASSERTED

After POR fault-error counter is set to 1 on default, it is reset after two consecutive good WD refreshes. This part of the register is read-only so a write access has no influence. Set this bit for a successful comparison between written and read register value

8.: Configure MCU FCCU error monitoring and its impact on RSTB and FS0B

9.: Configure Ext. IC error monitoring and its impact on RSTB and FS0B

MCU FCCU error monitoring options:

  • Input option:
    • FS8X_FS_I_FCCU_CFG_NO_MONITORING
    • FS8X_FS_I_FCCU_CFG_FCCU1_INPUT
    • FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_INPUT
    • FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_PAIR (bi-stable protocol)
  • Polarity option (independent):
    • FS8X_FS_I_FCCUx_FLT_POL_FCCUx_L
    • FS8X_FS_I_FCCUx_FLT_POL_FCCUx_H
  • Polarity option (bi-stable)
    • FS8X_FS_I_FCCU12_FLT_POL_FCCU1_L_FCCU2_H
    • FS8X_FS_I_FCCU12_FLT_POL_FCCU1_H_FCCU2_L
  • Impact option (independent)
    • FS8X_FS_I_FCCUx_FS_REACT_FS0B
    • FS8X_FS_I_FCCUx_FS_REACT_FS0B_RSTB
  • Impact option (bi-stable)
    • FS8X_FS_I_FCCU12_FS_IMPACT_FS0B
    • FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB

Ext. IC error monitoring options:

  • Polarity options:
    • FS8X_FS_I_ERRMON_FLT_POLARITY_NEGATIVE_EDGE
    • FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE
  • Error acknowledgment time options:
    • FS8X_FS_I_ERRMON_ACK_TIME_1MS
    • FS8X_FS_I_ERRMON_ACK_TIME_8MS
    • FS8X_FS_I_ERRMON_ACK_TIME_16MS
    • FS8X_FS_I_ERRMON_ACK_TIME_32MS
  • Error monitoring impact options:
    • FS8X_FS_I_ERRMON_FS_IMPACT_FS0B
    • FS8X_FS_I_ERRMON_FS_IMPACT_FS0B_RSTB

1.: Close INIT_FS by sending the first good WD refresh

2.: Execute ABIST2 and verify it is pass

ABIST2 is executed automatically after closing of INIT_FS, duration: 1.2ms max

3.: Clear all the flags by writing in FS_DIAG_SAFETY

Flags are cleared by writting '1' to register

Clear all the flags by writing in FS_OVUVREG_STATUS

Flags are cleared by writting '1' to register

Clear flags FLAG1 register

Clear flags FLAG2 register

Read out all registers for debug purpose

Definition at line 461 of file nxpfs85xx.c.

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◆ FS85X_SafetyPathChecks()

STD_RETURN_TYPE_e FS85X_SafetyPathChecks ( FS85xx_STATE_s *  pInstance)

Performs SBC safety path checks.

Function perform safety path checks for FIN, FS0B and RSTB to ensure that all pins work as expected

Parameters
[in,out]pInstancewhere the safety paths are checked
Returns
STD_OK if safety path check successful, otherwise STD_NOT_OK

Definition at line 910 of file nxpfs85xx.c.

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◆ SBC_TriggerWatchdog()

STD_RETURN_TYPE_e SBC_TriggerWatchdog ( FS85xx_STATE_s *  pInstance)

Trigger watchdog.

Triggers watchdog of passed SBC instance and verify if it was good refresh within the configured window

Parameters
[in,out]pInstanceSBC instance where the watchdog is triggered
Returns
STD_OK if watchdog has been triggered successfully, otherwise STD_NOT_OK

Definition at line 973 of file nxpfs85xx.c.

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Variable Documentation

◆ fs85xx_mcuSupervisor

FS85xx_STATE_s fs85xx_mcuSupervisor
extern

Definition at line 80 of file nxpfs85xx.c.