spi.c

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 *
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/**
 * @file    spi.c
 * @author  foxBMS Team
 * @date    2019-12-12 (date of creation)
 * @updated 2021-07-14 (date of last update)
 * @ingroup DRIVERS
 * @prefix  SPI
 *
 * @brief   Driver for the SPI module.
 *
 */
 
/*========== Includes =======================================================*/
#include "spi.h"
 
#include "HL_reg_spi.h"
#include "HL_spi.h"
#include "HL_sys_common.h"
 
#include "dma.h"
#include "fsystem.h"
#include "io.h"
#include "mcu.h"
#include "os.h"
 
/*========== Macros and Definitions =========================================*/
/** Bitfield to check for transmission errors in SPI FLAG register */
#define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS (0x5Fu)
 
/*========== Static Constant and Variable Definitions =======================*/
 
/*========== Extern Constant and Variable Definitions =======================*/
 
/*========== Static Function Prototypes =====================================*/
 
/*========== Static Function Implementations ================================*/
 
/*========== Extern Function Implementations ================================*/
 
extern STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay) {
    STD_RETURN_TYPE_e retval = STD_NOT_OK;
    uint16_t spi_cmdDummy[1] = {0x00};
 
    /* Lock SPI hardware to prevent concurrent read/write commands */
    if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
        IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
        uint32_t spiRetval =
            spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), 1u, spi_cmdDummy);
        IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
 
        /* Unlock SPI hardware */
        SPI_Unlock(pSpiInterface->channel);
 
        /* Transmission successful */
        if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
            retval = STD_OK;
        }
        MCU_delay_us(delay);
    }
    return retval;
}
 
STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint32_t frameLength) {
    STD_RETURN_TYPE_e retval = STD_NOT_OK;
 
    /* Lock SPI hardware to prevent concurrent read/write commands */
    if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
        IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
        uint32_t spiRetval =
            spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), frameLength, pTxBuff);
        IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
 
        /* Unlock SPI hardware */
        SPI_Unlock(pSpiInterface->channel);
 
        /* Transmission successful */
        if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
            retval = STD_OK;
        }
    }
    return retval;
}
 
STD_RETURN_TYPE_e SPI_TransmitDataWithDummy(
    SPI_INTERFACE_CONFIG_s *pSpiInterface,
    uint32_t delay,
    uint16_t *pTxBuff,
    uint32_t frameLength) {
    STD_RETURN_TYPE_e retval = STD_OK;
 
    /* Transmit dummy byte */
    if (SPI_TransmitDummyByte(pSpiInterface, delay) == STD_OK) {
        /* Transmit data only if transmission of dummy byte was successful */
        retval = SPI_TransmitData(pSpiInterface, pTxBuff, frameLength);
    } else {
        retval = STD_NOT_OK;
    }
    return retval;
}
 
extern STD_RETURN_TYPE_e SPI_TransmitReceiveData(
    SPI_INTERFACE_CONFIG_s *pSpiInterface,
    uint16 *pTxBuff,
    uint16 *pRxBuff,
    uint32 frameLength) {
    STD_RETURN_TYPE_e retval = STD_NOT_OK;
 
    /* Lock SPI hardware to prevent concurrent read/write commands */
    if (STD_OK == SPI_Lock(pSpiInterface->channel)) {
        IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
        uint32_t spiRetval = SPI_DirectlyTransmitReceiveData(pSpiInterface, pTxBuff, pRxBuff, frameLength);
        IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
 
        /* Unlock SPI hardware */
        SPI_Unlock(pSpiInterface->channel);
 
        /* Transmission successful */
        if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
            retval = STD_OK;
        }
    }
    return retval;
}
 
extern STD_RETURN_TYPE_e SPI_DirectlyTransmitReceiveData(
    SPI_INTERFACE_CONFIG_s *pSpiInterface,
    uint16 *pTxBuff,
    uint16 *pRxBuff,
    uint32 frameLength) {
    STD_RETURN_TYPE_e retval = STD_NOT_OK;
 
    uint32_t spiRetval = spiTransmitAndReceiveData(
        pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), frameLength, pTxBuff, pRxBuff);
 
    if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
        /* No error flag set during communication */
        retval = STD_OK;
    }
    return retval;
}
 
extern STD_RETURN_TYPE_e SPI_TransmitReceiveDataDma(
    SPI_INTERFACE_CONFIG_s *pSpiInterface,
    uint16_t *pTxBuff,
    uint16_t *pRxBuff,
    uint32_t frameLength) {
    FAS_ASSERT(pSpiInterface != NULL_PTR);
    FAS_ASSERT(pTxBuff != NULL_PTR);
    FAS_ASSERT(pRxBuff != NULL_PTR);
 
    STD_RETURN_TYPE_e retVal = STD_NOT_OK;
 
    OS_EnterTaskCritical();
    /* Lock SPI hardware to prevent concurrent read/write commands */
    if ((*(spi_busyFlags + pSpiInterface->channel) == SPI_IDLE) && (pSpiInterface->channel < spi_nrBusyFlags)) {
        *(spi_busyFlags + pSpiInterface->channel) = SPI_BUSY;
        retVal                                    = STD_OK;
        /* Check that not SPI transmission over DMA is taking place */
        if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
            /* Go to privilege mode to write DMA config registers */
            FSYS_RaisePrivilege();
 
            /* Set Tx buffer address */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ISADDR =
                (uint32_t)pTxBuff;
            /* Set number of Tx bytes to send */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ITCOUNT =
                (frameLength << 16U) | 1U;
 
            /* Set Rx buffer address */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].IDADDR =
                (uint32_t)pRxBuff;
            /* Set number of Rx bytes to receive */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].ITCOUNT =
                (frameLength << 16U) | 1U;
 
            uint8_t spiFmtRegister = 0U;
            switch (pSpiInterface->pConfig->DFSEL) {
                case 0U:
                    spiFmtRegister = 0U;
                    break;
                case 1U:
                    spiFmtRegister = 1U;
                    break;
                case 2U:
                    spiFmtRegister = 2U;
                    break;
                case 3U:
                    spiFmtRegister = 3U;
                    break;
                default:
                    spiFmtRegister = 0U;
                    break;
            }
 
            /* Re-enable channels; because auto-init is disabled */
            /* Disable otherwise transmission  is constantly ongoping */
            dmaSetChEnable(
                (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel, (dmaTriggerType_t)DMA_HW);
            dmaSetChEnable(
                (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel, (dmaTriggerType_t)DMA_HW);
 
            /* Store the CS pin to be deactivated in DMA callback */
            spi_dmaTransmission[pSpiInterface->channel].channel  = pSpiInterface->channel;
            spi_dmaTransmission[pSpiInterface->channel].pConfig  = pSpiInterface->pConfig;
            spi_dmaTransmission[pSpiInterface->channel].pNode    = pSpiInterface->pNode;
            spi_dmaTransmission[pSpiInterface->channel].pGioPort = pSpiInterface->pGioPort;
            spi_dmaTransmission[pSpiInterface->channel].csPin    = pSpiInterface->csPin;
 
            /* DMA seems to only be able to use FMT0, save FMT0 config */
            spi_saveFmt0[pSpiInterface->channel] = pSpiInterface->pNode->FMT0;
 
            /* DMA seems to only be able to use FMT0, write actual FMT in FMT0 */
            switch (spiFmtRegister) {
                case 0U:
                    break;
                case 1U:
                    pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT1;
                    break;
                case 2U:
                    pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT2;
                    break;
                case 3U:
                    pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT3;
                    break;
                default:
                    break;
            }
 
            /* DMA config registers written, leave privilege mode */
            FSYS_SwitchToUserMode();
 
            OS_ExitTaskCritical();
 
            /* Software activate CS */
            IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
            /* DMA_REQ_Enable */
            /* Starts DMA requests if SPIEN is also set to 1 */
            pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
 
            retVal = STD_OK;
        }
    } else {
        OS_ExitTaskCritical();
    }
 
    return retVal;
}
 
extern STD_RETURN_TYPE_e SPI_TransmitReceiveDataWithDummyDma(
    SPI_INTERFACE_CONFIG_s *pSpiInterface,
    uint32_t delay,
    uint16_t *pTxBuff,
    uint16_t *pRxBuff,
    uint32_t frameLength) {
    STD_RETURN_TYPE_e retVal = STD_NOT_OK;
    uint16_t spi_cmdDummy[1] = {0x00};
 
    OS_EnterTaskCritical();
    /* Lock SPI hardware to prevent concurrent read/write commands */
    if ((*(spi_busyFlags + pSpiInterface->channel) == SPI_IDLE) && (pSpiInterface->channel < spi_nrBusyFlags)) {
        *(spi_busyFlags + pSpiInterface->channel) = SPI_BUSY;
        retVal                                    = STD_OK;
 
        /* Check that not SPI transmission over DMA is taking place */
        if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
            /* Go to privilege mode to write DMA config registers */
            FSYS_RaisePrivilege();
 
            /* Set Tx buffer address */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ISADDR =
                (uint32_t)pTxBuff;
            /* Set number of Tx bytes to transmit */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel].ITCOUNT =
                (frameLength << 16U) | 1U;
 
            /* Set Rx buffer address */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].IDADDR =
                (uint32_t)pRxBuff;
            /* Set number of Rx bytes to receive */
            dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel].ITCOUNT =
                (frameLength << 16U) | 1U;
 
            uint8_t spiFmtRegister = 0U;
            switch (pSpiInterface->pConfig->DFSEL) {
                case 0U:
                    spiFmtRegister = 0U;
                    break;
                case 1U:
                    spiFmtRegister = 1U;
                    break;
                case 2U:
                    spiFmtRegister = 2U;
                    break;
                case 3U:
                    spiFmtRegister = 3U;
                    break;
                default:
                    spiFmtRegister = 0U;
                    break;
            }
 
            /* Re-enable channels; because auto-init is disabled */
            /* Disable otherwise transmission  is constantly ongoping */
            dmaSetChEnable(
                (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].txChannel, (dmaTriggerType_t)DMA_HW);
            dmaSetChEnable(
                (dmaChannel_t)dma_spiDmaChannels[pSpiInterface->channel].rxChannel, (dmaTriggerType_t)DMA_HW);
 
            /* Store the CS pin to be deactivated in DMA callback */
            spi_dmaTransmission[pSpiInterface->channel].channel  = pSpiInterface->channel;
            spi_dmaTransmission[pSpiInterface->channel].pConfig  = pSpiInterface->pConfig;
            spi_dmaTransmission[pSpiInterface->channel].pNode    = pSpiInterface->pNode;
            spi_dmaTransmission[pSpiInterface->channel].pGioPort = pSpiInterface->pGioPort;
            spi_dmaTransmission[pSpiInterface->channel].csPin    = pSpiInterface->csPin;
 
            /* DMA seems to only be able to use FMT0, save FMT0 config */
            spi_saveFmt0[pSpiInterface->channel] = pSpiInterface->pNode->FMT0;
 
            /* DMA seems to only be able to use FMT0, write actual FMT in FMT0 */
            switch (spiFmtRegister) {
                case 0U:
                    break;
                case 1U:
                    pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT1;
                    break;
                case 2U:
                    pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT2;
                    break;
                case 3U:
                    pSpiInterface->pNode->FMT0 = pSpiInterface->pNode->FMT3;
                    break;
                default:
                    break;
            }
 
            /* DMA config registers written, leave privilege mode */
            FSYS_SwitchToUserMode();
 
            OS_ExitTaskCritical();
 
            IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
            uint32_t spiRetval =
                spiTransmitData(pSpiInterface->pNode, ((spiDAT1_t *)pSpiInterface->pConfig), 1u, spi_cmdDummy);
            IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
            if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
                /* No error flag set during communication */
 
                MCU_delay_us(delay);
 
                /* Software activate CS */
                IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
                /* DMA_REQ_Enable */
                /* Starts DMA requests if SPIEN is also set to 1 */
                pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
            }
            retVal = STD_OK;
        }
    } else {
        OS_ExitTaskCritical();
    }
 
    return retVal;
}
 
extern STD_RETURN_TYPE_e SPI_Lock(uint8_t spi) {
    STD_RETURN_TYPE_e retVal = STD_NOT_OK;
 
    OS_EnterTaskCritical();
    if ((*(spi_busyFlags + spi) == SPI_IDLE) && (spi < spi_nrBusyFlags)) {
        *(spi_busyFlags + spi) = SPI_BUSY;
        retVal                 = STD_OK;
    } else {
        retVal = STD_NOT_OK;
    }
    OS_ExitTaskCritical();
 
    return retVal;
}
 
extern void SPI_Unlock(uint8_t spi) {
    OS_EnterTaskCritical();
    if (spi < spi_nrBusyFlags) {
        *(spi_busyFlags + spi) = SPI_IDLE;
    }
    OS_ExitTaskCritical();
}
 
extern void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled) {
    FAS_ASSERT(pNode != NULL_PTR);
    FAS_ASSERT(bit <= (enum spiPinSelect)LARGEST_PIN_NUMBER);
 
    /* retrieve current configuration */
    spi_config_reg_t configRegisterBuffer = {0};
    if (pNode == spiREG1) {
        spi1GetConfigValue(&configRegisterBuffer, CurrentValue);
    } else if (pNode == spiREG2) {
        spi2GetConfigValue(&configRegisterBuffer, CurrentValue);
    } else if (pNode == spiREG3) {
        spi3GetConfigValue(&configRegisterBuffer, CurrentValue);
    } else if (pNode == spiREG4) {
        spi4GetConfigValue(&configRegisterBuffer, CurrentValue);
    } else if (pNode == spiREG5) {
        spi5GetConfigValue(&configRegisterBuffer, CurrentValue);
    } else {
        /* invalid SPI node */
        FAS_ASSERT(FAS_TRAP);
    }
    uint32_t newPc0 = configRegisterBuffer.CONFIG_PC0;
 
    if (hardwareControlled == false) {
        /* bit has to be cleared */
        newPc0 &= ~(uint32_t)((uint32_t)1u << (uint8_t)(bit));
    } else {
        /* bit has to be set */
        newPc0 |= (uint32_t)((uint32_t)1u << (uint8_t)(bit));
    }
 
    /* set new port value */
    spiSetFunctional(pNode, newPc0);
}
 
/*========== Externalized Static Function Implementations (Unit Test) =======*/