55 #ifndef FOXBMS__DMA_CFG_H_
56 #define FOXBMS__DMA_CFG_H_
64 #include "HL_sys_dma.h"
70 #define DMA_CHANNEL_SPI1_TX (DMA_CH0)
71 #define DMA_CHANNEL_SPI1_RX (DMA_CH1)
72 #define DMA_CHANNEL_SPI2_TX (DMA_CH2)
73 #define DMA_CHANNEL_SPI2_RX (DMA_CH3)
74 #define DMA_CHANNEL_SPI3_TX (DMA_CH4)
75 #define DMA_CHANNEL_SPI3_RX (DMA_CH5)
76 #define DMA_CHANNEL_SPI4_TX (DMA_CH6)
77 #define DMA_CHANNEL_SPI4_RX (DMA_CH7)
78 #define DMA_CHANNEL_SPI5_TX (DMA_CH8)
79 #define DMA_CHANNEL_SPI5_RX (DMA_CH9)
80 #define DMA_CHANNEL_I2C_TX (DMA_CH10)
81 #define DMA_CHANNEL_I2C_RX (DMA_CH11)
86 #define DMA_REQ_LINE_SPI1_TX (DMA_REQ1)
87 #define DMA_REQ_LINE_SPI1_RX (DMA_REQ0)
88 #define DMA_REQ_LINE_SPI2_TX (DMA_REQ3)
89 #define DMA_REQ_LINE_SPI2_RX (DMA_REQ2)
90 #define DMA_REQ_LINE_SPI3_TX (DMA_REQ15)
91 #define DMA_REQ_LINE_SPI3_RX (DMA_REQ14)
92 #define DMA_REQ_LINE_SPI4_TX (DMA_REQ25)
93 #define DMA_REQ_LINE_SPI4_RX (DMA_REQ24)
94 #define DMA_REQ_LINE_SPI5_TX (DMA_REQ31)
95 #define DMA_REQ_LINE_SPI5_RX (DMA_REQ30)
96 #define DMA_REQ_LINE_I2C_TX (DMA_REQ11)
97 #define DMA_REQ_LINE_I2C_RX (DMA_REQ10)
101 #define DMA_BIG_ENDIAN_ADDRESS_8BIT (3u)
103 #define DMA_BIG_ENDIAN_ADDRESS_16BIT (2u)
106 #define DMA_NUMBER_SPI_INTERFACES 5u
108 #define DMAREQEN_BIT (0x10000U)
110 #define SPIEN_BIT (0x1000000U)
114 #define DMA_REQ_LINE_LTC_TX (DMA_REQ_LINE_SPI1_TX)
115 #define DMA_REQ_LINE_LTC_RX (DMA_REQ_LINE_SPI1_RX)
120 #define DMA_REQ_LINE_N775_TX (DMA_REQ_LINE_SPI1_TX)
121 #define DMA_REQ_LINE_N775_RX (DMA_REQ_LINE_SPI5_RX)
Configuration of the battery system (e.g., number of battery modules, battery cells,...
struct DMA_REQUEST_CONFIG DMA_REQUEST_CONFIG_s
#define DMA_NUMBER_SPI_INTERFACES
DMA_REQUEST_CONFIG_s dma_spiDmaRequests[DMA_NUMBER_SPI_INTERFACES]
spiBASE_t * dma_spiInterfaces[DMA_NUMBER_SPI_INTERFACES]
struct DMA_CHANNEL_CONFIG DMA_CHANNEL_CONFIG_s
DMA_CHANNEL_CONFIG_s dma_spiDmaChannels[DMA_NUMBER_SPI_INTERFACES]
General macros and definitions for the whole platform.