foxBMS - Unit Tests
1.2.1
The foxBMS Unit Tests API Documentation
sbc_fs8x_map.h
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1
/*
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* Copyright (c) 2016 - 2018, NXP Semiconductors, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file sbc_fs8x_map.h
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* @brief FS8x register map.
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*
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* This header file contains addresses, masks, shifts and shifted discreet values
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* for runtime registers of the FS8x. Note that some registers have the same address;
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* the reason is that there are 2 register groups: main and fail-safe.
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* See data sheet for details.
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*
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* @author nxf44615
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* @version 1.1
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* @date 9-Oct-2018
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* @copyright Copyright (c) 2016 - 2018, NXP Semiconductors, Inc.
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*
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* @warning Some macro names are not compliant with MISRA rule 5.4 if C90 standard is used
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* (the first 31 characters of macro identifiers are significant).
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* If C99 standard is used, there is no issue, as the first 63 characters of macro
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* identifiers are significant.
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*/
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50
#ifndef SBC_FS8X_MAP_H__
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#define SBC_FS8X_MAP_H__
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53
/******************************************************************************/
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/* M_FLAG - Type: RW */
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/******************************************************************************/
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57
#define FS8X_M_FLAG_ADDR 0x00U
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#define FS8X_M_FLAG_DEFAULT 0x0000U
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60
/**
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* Invalid Main Domain I2C access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address).
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*/
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#define FS8X_M_I2C_M_REQ_MASK 0x0001U
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/**
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* Main Domain I2C communication CRC issue.
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*/
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#define FS8X_M_I2C_M_CRC_MASK 0x0002U
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/**
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* Main Domain SPI communication CRC issue
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*/
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#define FS8X_M_SPI_M_CRC_MASK 0x0004U
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/**
73
* Invalid Main domain SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address).
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*/
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#define FS8X_M_SPI_M_REQ_MASK 0x0008U
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/**
77
* Main Domain SPI SCLK error detection.
78
*/
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#define FS8X_M_SPI_M_CLK_MASK 0x0010U
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/**
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* Report an event on LDO2 (status change or failure)
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*/
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#define FS8X_M_VLDO2_G_MASK 0x0080U
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/**
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* Report an event on LDO1 (status change or failure)
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*/
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#define FS8X_M_VLDO1_G_MASK 0x0100U
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/**
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* Report an event on BUCK3 (status change or failure)
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*/
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#define FS8X_M_VBUCK3_G_MASK 0x0200U
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/**
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* Report an event on BUCK2 (status change or failure)
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*/
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#define FS8X_M_VBUCK2_G_MASK 0x0400U
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/**
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* Report an event on BUCK1 (status change or failure)
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*/
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#define FS8X_M_VBUCK1_G_MASK 0x0800U
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/**
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* Report an event on VBOOST (status change or failure)
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*/
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#define FS8X_M_VBOOST_G_MASK 0x1000U
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/**
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* Report an event on VPRE (status change or failure)
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*/
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#define FS8X_M_VPRE_G_MASK 0x2000U
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/**
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* Report a wake-up event. Logical OR of WAKE1 and WAKE2 source
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*/
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#define FS8X_M_WU_G_MASK 0x4000U
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/**
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* Report an error in the Communication (SPI or I2C)
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*/
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#define FS8X_M_COM_ERR_MASK 0x8000U
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117
/**
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* Invalid Main Domain I2C access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address).
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*/
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#define FS8X_M_I2C_M_REQ_SHIFT 0x0000U
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/**
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* Main Domain I2C communication CRC issue.
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*/
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#define FS8X_M_I2C_M_CRC_SHIFT 0x0001U
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/**
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* Main Domain SPI communication CRC issue
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*/
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#define FS8X_M_SPI_M_CRC_SHIFT 0x0002U
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/**
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* Invalid Main domain SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address).
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*/
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#define FS8X_M_SPI_M_REQ_SHIFT 0x0003U
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/**
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* Main Domain SPI SCLK error detection.
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*/
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#define FS8X_M_SPI_M_CLK_SHIFT 0x0004U
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/**
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* Report an event on LDO2 (status change or failure)
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*/
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#define FS8X_M_VLDO2_G_SHIFT 0x0007U
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/**
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* Report an event on LDO1 (status change or failure)
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*/
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#define FS8X_M_VLDO1_G_SHIFT 0x0008U
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/**
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* Report an event on BUCK3 (status change or failure)
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*/
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#define FS8X_M_VBUCK3_G_SHIFT 0x0009U
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/**
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* Report an event on BUCK2 (status change or failure)
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*/
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#define FS8X_M_VBUCK2_G_SHIFT 0x000AU
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/**
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* Report an event on BUCK1 (status change or failure)
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*/
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#define FS8X_M_VBUCK1_G_SHIFT 0x000BU
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/**
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* Report an event on VBOOST (status change or failure)
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*/
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#define FS8X_M_VBOOST_G_SHIFT 0x000CU
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/**
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* Report an event on VPRE (status change or failure)
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*/
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#define FS8X_M_VPRE_G_SHIFT 0x000DU
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/**
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* Report a wake-up event. Logical OR of WAKE1 and WAKE2 source
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*/
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#define FS8X_M_WU_G_SHIFT 0x000EU
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/**
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* Report an error in the Communication (SPI or I2C)
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*/
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#define FS8X_M_COM_ERR_SHIFT 0x000FU
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174
/**
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* No error
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*/
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#define FS8X_M_I2C_M_REQ_NO_ERROR (0x0000U << FS8X_M_I2C_M_REQ_SHIFT)
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/**
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* I2C Violation
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*/
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#define FS8X_M_I2C_M_REQ_I2C_V (0x0001U << FS8X_M_I2C_M_REQ_SHIFT)
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/**
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* No error
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*/
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#define FS8X_M_I2C_M_CRC_NO_ERROR (0x0000U << FS8X_M_I2C_M_CRC_SHIFT)
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/**
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* Error detected in the I2C CRC
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*/
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#define FS8X_M_I2C_M_CRC_ERROR (0x0001U << FS8X_M_I2C_M_CRC_SHIFT)
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/**
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* No error
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*/
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#define FS8X_M_SPI_M_CRC_NO_ERROR (0x0000U << FS8X_M_SPI_M_CRC_SHIFT)
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/**
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* Error detected in the SPI CRC
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*/
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#define FS8X_M_SPI_M_CRC_ERROR (0x0001U << FS8X_M_SPI_M_CRC_SHIFT)
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201
/**
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* No error
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*/
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#define FS8X_M_SPI_M_REQ_NO_ERROR (0x0000U << FS8X_M_SPI_M_REQ_SHIFT)
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/**
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* SPI Violation
207
*/
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#define FS8X_M_SPI_M_REQ_SPI_V (0x0001U << FS8X_M_SPI_M_REQ_SHIFT)
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210
/**
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* No error
212
*/
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#define FS8X_M_SPI_M_CLK_NO_ERROR (0x0000U << FS8X_M_SPI_M_CLK_SHIFT)
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/**
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* Wrong number of clock cycles (<32 or >32)
216
*/
217
#define FS8X_M_SPI_M_CLK_WRONG (0x0001U << FS8X_M_SPI_M_CLK_SHIFT)
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219
/**
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* No event
221
*/
222
#define FS8X_M_VLDO2_G_NO_EVENT (0x0000U << FS8X_M_VLDO2_G_SHIFT)
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/**
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* Event occurred
225
*/
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#define FS8X_M_VLDO2_G_EVENT_OCCURRED (0x0001U << FS8X_M_VLDO2_G_SHIFT)
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228
/**
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* No event
230
*/
231
#define FS8X_M_VLDO1_G_NO_EVENT (0x0000U << FS8X_M_VLDO1_G_SHIFT)
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/**
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* Event occurred
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*/
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#define FS8X_M_VLDO1_G_EVENT_OCCURRED (0x0001U << FS8X_M_VLDO1_G_SHIFT)
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237
/**
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* No event
239
*/
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#define FS8X_M_VBUCK3_G_NO_EVENT (0x0000U << FS8X_M_VBUCK3_G_SHIFT)
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/**
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* Event occurred
243
*/
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#define FS8X_M_VBUCK3_G_EVENT_OCCURRED (0x0001U << FS8X_M_VBUCK3_G_SHIFT)
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/**
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* No event
248
*/
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#define FS8X_M_VBUCK2_G_NO_EVENT (0x0000U << FS8X_M_VBUCK2_G_SHIFT)
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/**
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* Event occurred
252
*/
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#define FS8X_M_VBUCK2_G_EVENT_OCCURRED (0x0001U << FS8X_M_VBUCK2_G_SHIFT)
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255
/**
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* No event
257
*/
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#define FS8X_M_VBUCK1_G_NO_EVENT (0x0000U << FS8X_M_VBUCK1_G_SHIFT)
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/**
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* Event occurred
261
*/
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#define FS8X_M_VBUCK1_G_EVENT_OCCURRED (0x0001U << FS8X_M_VBUCK1_G_SHIFT)
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/**
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* No event
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*/
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#define FS8X_M_VBOOST_G_NO_EVENT (0x0000U << FS8X_M_VBOOST_G_SHIFT)
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/**
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* Event occurred
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*/
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#define FS8X_M_VBOOST_G_EVENT_OCCURRED (0x0001U << FS8X_M_VBOOST_G_SHIFT)
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/**
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* No event
275
*/
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#define FS8X_M_VPRE_G_NO_EVENT (0x0000U << FS8X_M_VPRE_G_SHIFT)
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/**
278
* Event occurred
279
*/
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#define FS8X_M_VPRE_G_EVENT_OCCURRED (0x0001U << FS8X_M_VPRE_G_SHIFT)
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282
/**
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* No Wake event
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*/
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#define FS8X_M_WU_G_NO_WAKE_EVENT (0x0000U << FS8X_M_WU_G_SHIFT)
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/**
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* Wake event
288
*/
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#define FS8X_M_WU_G_WAKE_EVENT (0x0001U << FS8X_M_WU_G_SHIFT)
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291
/**
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* No Failure
293
*/
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#define FS8X_M_COM_ERR_NO_FAILURE (0x0000U << FS8X_M_COM_ERR_SHIFT)
295
/**
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* Failure
297
*/
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#define FS8X_M_COM_ERR_FAILURE (0x0001U << FS8X_M_COM_ERR_SHIFT)
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300
/******************************************************************************/
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/* M_MODE - Type: RW */
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/******************************************************************************/
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#define FS8X_M_MODE_ADDR 0x01U
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#define FS8X_M_MODE_DEFAULT 0x0000U
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307
/**
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* Entry in Standby mode
309
*/
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#define FS8X_M_GOTOSTBY_MASK 0x0001U
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/**
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* WAKE1 wake up disable
313
*/
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#define FS8X_M_W1DIS_MASK 0x0002U
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/**
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* WAKE2 wake up disable
317
*/
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#define FS8X_M_W2DIS_MASK 0x0004U
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/**
320
* State machine Normal mode
321
*/
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#define FS8X_M_MAIN_NORMAL_MASK 0x0020U
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/**
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* EXT FIN selection disable at PLL input request
325
*/
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#define FS8X_M_EXT_FIN_DIS_MASK 0x0040U
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/**
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* Real time status of FIN clock selection
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*/
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#define FS8X_M_EXT_FIN_SEL_RT_MASK 0x0080U
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/**
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* Real time status of PLL lock flag
333
*/
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#define FS8X_M_PLL_LOCK_RT_MASK 0x0100U
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336
/**
337
* Entry in Standby mode
338
*/
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#define FS8X_M_GOTOSTBY_SHIFT 0x0000U
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/**
341
* WAKE1 wake up disable
342
*/
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#define FS8X_M_W1DIS_SHIFT 0x0001U
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/**
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* WAKE2 wake up disable
346
*/
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#define FS8X_M_W2DIS_SHIFT 0x0002U
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/**
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* State machine Normal mode
350
*/
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#define FS8X_M_MAIN_NORMAL_SHIFT 0x0005U
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/**
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* EXT FIN selection disable at PLL input request
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*/
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#define FS8X_M_EXT_FIN_DIS_SHIFT 0x0006U
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/**
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* Real time status of FIN clock selection
358
*/
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#define FS8X_M_EXT_FIN_SEL_RT_SHIFT 0x0007U
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/**
361
* Real time status of PLL lock flag
362
*/
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#define FS8X_M_PLL_LOCK_RT_SHIFT 0x0008U
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365
/**
366
* Device remains in current state
367
*/
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#define FS8X_M_GOTOSTBY_REMAINS_IN_CURRENT_STATE (0x0000U << FS8X_M_GOTOSTBY_SHIFT)
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/**
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* Device will enter in Standby mode
371
*/
372
#define FS8X_M_GOTOSTBY_ENTER_IN_STANDBY_MODE (0x0001U << FS8X_M_GOTOSTBY_SHIFT)
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374
/**
375
* wake up enable
376
*/
377
#define FS8X_M_W1DIS_WAKE_UP_ENABLE (0x0000U << FS8X_M_W1DIS_SHIFT)
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/**
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* wake up disable
380
*/
381
#define FS8X_M_W1DIS_WAKE_UP_DISABLE (0x0001U << FS8X_M_W1DIS_SHIFT)
382
383
/**
384
* wake up enable
385
*/
386
#define FS8X_M_W2DIS_WAKE_UP_ENABLE (0x0000U << FS8X_M_W2DIS_SHIFT)
387
/**
388
* wake up disable
389
*/
390
#define FS8X_M_W2DIS_WAKE_UP_DISABLE (0x0001U << FS8X_M_W2DIS_SHIFT)
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392
/**
393
* State Machine NOT in Normal mode
394
*/
395
#define FS8X_M_MAIN_NORMAL_NOT_IN_NORMAL_MODE (0x0000U << FS8X_M_MAIN_NORMAL_SHIFT)
396
/**
397
* State Machine in Normal mode - Entry in Standby mode possible
398
*/
399
#define FS8X_M_MAIN_NORMAL_IN_NORMAL_MODE (0x0001U << FS8X_M_MAIN_NORMAL_SHIFT)
400
401
/**
402
* No effect
403
*/
404
#define FS8X_M_EXT_FIN_DIS_NO_EFFECT (0x0000U << FS8X_M_EXT_FIN_DIS_SHIFT)
405
/**
406
* Disable FIN selection
407
*/
408
#define FS8X_M_EXT_FIN_DIS_DISABLE_FIN (0x0001U << FS8X_M_EXT_FIN_DIS_SHIFT)
409
410
/**
411
* Internal clock oscillator is selected
412
*/
413
#define FS8X_M_EXT_FIN_SEL_RT_INT_OSC (0x0000U << FS8X_M_EXT_FIN_SEL_RT_SHIFT)
414
/**
415
* External FIN clock is selected
416
*/
417
#define FS8X_M_EXT_FIN_SEL_RT_EXT_OSC (0x0001U << FS8X_M_EXT_FIN_SEL_RT_SHIFT)
418
419
/**
420
* PLL not locked
421
*/
422
#define FS8X_M_PLL_LOCK_RT_UNLOCKED (0x0000U << FS8X_M_PLL_LOCK_RT_SHIFT)
423
/**
424
* PLL locked
425
*/
426
#define FS8X_M_PLL_LOCK_RT_LOCKED (0x0001U << FS8X_M_PLL_LOCK_RT_SHIFT)
427
428
/******************************************************************************/
429
/* M_REG_CTRL1 - Type: RW */
430
/******************************************************************************/
431
432
#define FS8X_M_REG_CTRL1_ADDR 0x02U
433
#define FS8X_M_REG_CTRL1_DEFAULT 0x0000U
434
435
/**
436
* Enable request of LDO2
437
*/
438
#define FS8X_M_LDO2EN_MASK 0x0001U
439
/**
440
* Enable request of LDO1
441
*/
442
#define FS8X_M_LDO1EN_MASK 0x0002U
443
/**
444
* Enable request of BUCK3
445
*/
446
#define FS8X_M_BUCK3EN_MASK 0x0004U
447
/**
448
* Enable request of BUCK2
449
*/
450
#define FS8X_M_BUCK2EN_MASK 0x0008U
451
/**
452
* Enable request of BUCK1
453
*/
454
#define FS8X_M_BUCK1EN_MASK 0x0010U
455
/**
456
* Enable request of BOOST
457
*/
458
#define FS8X_M_BOOSTEN_MASK 0x0020U
459
/**
460
* Enable request of VPRE
461
*/
462
#define FS8X_M_VPEN_MASK 0x0040U
463
/**
464
* Disable request of LDO2
465
*/
466
#define FS8X_M_LDO2DIS_MASK 0x0100U
467
/**
468
* Disable request of LDO1
469
*/
470
#define FS8X_M_LDO1DIS_MASK 0x0200U
471
/**
472
* Disable request of BUCK3
473
*/
474
#define FS8X_M_BUCK3DIS_MASK 0x0400U
475
/**
476
* Disable request of BUCK2
477
*/
478
#define FS8X_M_BUCK2DIS_MASK 0x0800U
479
/**
480
* Disable request of BUCK1
481
*/
482
#define FS8X_M_BUCK1DIS_MASK 0x1000U
483
/**
484
* Disable request of BOOST
485
*/
486
#define FS8X_M_BOOSTDIS_MASK 0x2000U
487
/**
488
* Disable request of VPRE
489
*/
490
#define FS8X_M_VPDIS_MASK 0x4000U
491
/**
492
* Force disable of VPRE pull down.
493
*/
494
#define FS8X_M_VPRE_PD_DIS_MASK 0x8000U
495
496
/**
497
* Enable request of LDO2
498
*/
499
#define FS8X_M_LDO2EN_SHIFT 0x0000U
500
/**
501
* Enable request of LDO1
502
*/
503
#define FS8X_M_LDO1EN_SHIFT 0x0001U
504
/**
505
* Enable request of BUCK3
506
*/
507
#define FS8X_M_BUCK3EN_SHIFT 0x0002U
508
/**
509
* Enable request of BUCK2
510
*/
511
#define FS8X_M_BUCK2EN_SHIFT 0x0003U
512
/**
513
* Enable request of BUCK1
514
*/
515
#define FS8X_M_BUCK1EN_SHIFT 0x0004U
516
/**
517
* Enable request of BOOST
518
*/
519
#define FS8X_M_BOOSTEN_SHIFT 0x0005U
520
/**
521
* Enable request of VPRE
522
*/
523
#define FS8X_M_VPEN_SHIFT 0x0006U
524
/**
525
* Disable request of LDO2
526
*/
527
#define FS8X_M_LDO2DIS_SHIFT 0x0008U
528
/**
529
* Disable request of LDO1
530
*/
531
#define FS8X_M_LDO1DIS_SHIFT 0x0009U
532
/**
533
* Disable request of BUCK3
534
*/
535
#define FS8X_M_BUCK3DIS_SHIFT 0x000AU
536
/**
537
* Disable request of BUCK2
538
*/
539
#define FS8X_M_BUCK2DIS_SHIFT 0x000BU
540
/**
541
* Disable request of BUCK1
542
*/
543
#define FS8X_M_BUCK1DIS_SHIFT 0x000CU
544
/**
545
* Disable request of BOOST
546
*/
547
#define FS8X_M_BOOSTDIS_SHIFT 0x000DU
548
/**
549
* Disable request of VPRE
550
*/
551
#define FS8X_M_VPDIS_SHIFT 0x000EU
552
/**
553
* Force disable of VPRE pull down.
554
*/
555
#define FS8X_M_VPRE_PD_DIS_SHIFT 0x000FU
556
557
/**
558
* no effect (regulator remains in existing state - if ON it remains ON, if OFF it remains OFF)
559
*/
560
#define FS8X_M_LDO2EN_NO_EFFECT (0x0000U << FS8X_M_LDO2EN_SHIFT)
561
/**
562
* LDO2 Enable Request
563
*/
564
#define FS8X_M_LDO2EN_LDO2_ENABLE_REQUEST (0x0001U << FS8X_M_LDO2EN_SHIFT)
565
566
/**
567
* no effect (regulator remains in existing state)
568
*/
569
#define FS8X_M_LDO1EN_NO_EFFECT (0x0000U << FS8X_M_LDO1EN_SHIFT)
570
/**
571
* LDO1 Enable Request
572
*/
573
#define FS8X_M_LDO1EN_LDO1_ENABLE_REQUEST (0x0001U << FS8X_M_LDO1EN_SHIFT)
574
575
/**
576
* no effect (regulator remains in existing state)
577
*/
578
#define FS8X_M_BUCK3EN_NO_EFFECT (0x0000U << FS8X_M_BUCK3EN_SHIFT)
579
/**
580
* BUCK3 Enable Request
581
*/
582
#define FS8X_M_BUCK3EN_BUCK3_ENABLE_REQUEST (0x0001U << FS8X_M_BUCK3EN_SHIFT)
583
584
/**
585
* no effect (regulator remains in existing state)
586
*/
587
#define FS8X_M_BUCK2EN_NO_EFFECT (0x0000U << FS8X_M_BUCK2EN_SHIFT)
588
/**
589
* BUCK2 Enable Request
590
*/
591
#define FS8X_M_BUCK2EN_BUCK2_ENABLE_REQUEST (0x0001U << FS8X_M_BUCK2EN_SHIFT)
592
593
/**
594
* no effect (regulator remains in existing state)
595
*/
596
#define FS8X_M_BUCK1EN_NO_EFFECT (0x0000U << FS8X_M_BUCK1EN_SHIFT)
597
/**
598
* BUCK1 Enable Request
599
*/
600
#define FS8X_M_BUCK1EN_BUCK1_ENABLE_REQUEST (0x0001U << FS8X_M_BUCK1EN_SHIFT)
601
602
/**
603
* no effect (regulator remains in existing state)
604
*/
605
#define FS8X_M_BOOSTEN_NO_EFFECT (0x0000U << FS8X_M_BOOSTEN_SHIFT)
606
/**
607
* BOOST Enable Request
608
*/
609
#define FS8X_M_BOOSTEN_BOOST_ENABLE_REQUEST (0x0001U << FS8X_M_BOOSTEN_SHIFT)
610
611
/**
612
* no effect (regulator remains in existing state)
613
*/
614
#define FS8X_M_VPEN_NO_EFFECT (0x0000U << FS8X_M_VPEN_SHIFT)
615
/**
616
* VPRE Enable Request
617
*/
618
#define FS8X_M_VPEN_VPRE_ENABLE_REQUEST (0x0001U << FS8X_M_VPEN_SHIFT)
619
620
/**
621
* no effect (regulator remains in existing state)
622
*/
623
#define FS8X_M_LDO2DIS_NO_EFFECT (0x0000U << FS8X_M_LDO2DIS_SHIFT)
624
/**
625
* LDO2 Disable Request
626
*/
627
#define FS8X_M_LDO2DIS_LDO2_DISABLE_REQUEST (0x0001U << FS8X_M_LDO2DIS_SHIFT)
628
629
/**
630
* no effect (regulator remains in existing state)
631
*/
632
#define FS8X_M_LDO1DIS_NO_EFFECT (0x0000U << FS8X_M_LDO1DIS_SHIFT)
633
/**
634
* LDO1 Disable Request
635
*/
636
#define FS8X_M_LDO1DIS_LDO1_DISABLE_REQUEST (0x0001U << FS8X_M_LDO1DIS_SHIFT)
637
638
/**
639
* no effect (regulator remains in existing state)
640
*/
641
#define FS8X_M_BUCK3DIS_NO_EFFECT (0x0000U << FS8X_M_BUCK3DIS_SHIFT)
642
/**
643
* BUCK3 Disable Request
644
*/
645
#define FS8X_M_BUCK3DIS_BUCK3_DISABLE_REQUEST (0x0001U << FS8X_M_BUCK3DIS_SHIFT)
646
647
/**
648
* no effect (regulator remains in existing state)
649
*/
650
#define FS8X_M_BUCK2DIS_NO_EFFECT (0x0000U << FS8X_M_BUCK2DIS_SHIFT)
651
/**
652
* BUCK2 Disable Request
653
*/
654
#define FS8X_M_BUCK2DIS_BUCK2_DISABLE_REQUEST (0x0001U << FS8X_M_BUCK2DIS_SHIFT)
655
656
/**
657
* no effect (regulator remains in existing state)
658
*/
659
#define FS8X_M_BUCK1DIS_NO_EFFECT (0x0000U << FS8X_M_BUCK1DIS_SHIFT)
660
/**
661
* BUCK1 Disable Request
662
*/
663
#define FS8X_M_BUCK1DIS_BUCK1_DISABLE_REQUEST (0x0001U << FS8X_M_BUCK1DIS_SHIFT)
664
665
/**
666
* no effect (regulator remains in existing state)
667
*/
668
#define FS8X_M_BOOSTDIS_NO_EFFECT (0x0000U << FS8X_M_BOOSTDIS_SHIFT)
669
/**
670
* BOOST Disable Request
671
*/
672
#define FS8X_M_BOOSTDIS_BOOST_DISABLE_REQUEST (0x0001U << FS8X_M_BOOSTDIS_SHIFT)
673
674
/**
675
* no effect (regulator remains in existing state)
676
*/
677
#define FS8X_M_VPDIS_NO_EFFECT (0x0000U << FS8X_M_VPDIS_SHIFT)
678
/**
679
* VPRE Disable Request
680
*/
681
#define FS8X_M_VPDIS_VPRE_DISABLE_REQUEST (0x0001U << FS8X_M_VPDIS_SHIFT)
682
683
/**
684
* no effect (VPRE pull down is automatically controlled by the logic)
685
*/
686
#define FS8X_M_VPRE_PD_DIS_NO_EFFECT (0x0000U << FS8X_M_VPRE_PD_DIS_SHIFT)
687
/**
688
* VPRE pull down disable Request
689
*/
690
#define FS8X_M_VPRE_PD_DIS_VPRE_DISABLE_REQUEST (0x0001U << FS8X_M_VPRE_PD_DIS_SHIFT)
691
692
/******************************************************************************/
693
/* M_REG_CTRL2 - Type: RW */
694
/******************************************************************************/
695
696
#define FS8X_M_REG_CTRL2_ADDR 0x03U
697
#define FS8X_M_REG_CTRL2_DEFAULT 0x0009U
698
699
/**
700
* VPRE High Side slew rate control
701
*/
702
#define FS8X_M_VPRESRHS_MASK 0x0003U
703
/**
704
* VPRE Low Side slew rate control
705
*/
706
#define FS8X_M_VPRESRLS_MASK 0x0018U
707
/**
708
* Regulator behavior in case of TSD
709
*/
710
#define FS8X_M_LDO2TSDCFG_MASK 0x0100U
711
/**
712
* Regulator behavior in case of TSD
713
*/
714
#define FS8X_M_LDO1TSDCFG_MASK 0x0200U
715
/**
716
* Regulator behavior in case of TSD
717
*/
718
#define FS8X_M_BUCK3TSDCFG_MASK 0x0400U
719
/**
720
* Regulator behavior in case of TSD
721
*/
722
#define FS8X_M_BUCK2TSDCFG_MASK 0x0800U
723
/**
724
* Regulator behavior in case of TSD
725
*/
726
#define FS8X_M_BUCK1TSDCFG_MASK 0x1000U
727
/**
728
* Regulator behavior in case of TSD
729
*/
730
#define FS8X_M_BOOSTTSDCFG_MASK 0x2000U
731
/**
732
* VBOOST Low Side slew rate control
733
*/
734
#define FS8X_M_VBSTSR_MASK 0xC000U
735
736
/**
737
* VPRE High Side slew rate control
738
*/
739
#define FS8X_M_VPRESRHS_SHIFT 0x0000U
740
/**
741
* VPRE Low Side slew rate control
742
*/
743
#define FS8X_M_VPRESRLS_SHIFT 0x0003U
744
/**
745
* Regulator behavior in case of TSD
746
*/
747
#define FS8X_M_LDO2TSDCFG_SHIFT 0x0008U
748
/**
749
* Regulator behavior in case of TSD
750
*/
751
#define FS8X_M_LDO1TSDCFG_SHIFT 0x0009U
752
/**
753
* Regulator behavior in case of TSD
754
*/
755
#define FS8X_M_BUCK3TSDCFG_SHIFT 0x000AU
756
/**
757
* Regulator behavior in case of TSD
758
*/
759
#define FS8X_M_BUCK2TSDCFG_SHIFT 0x000BU
760
/**
761
* Regulator behavior in case of TSD
762
*/
763
#define FS8X_M_BUCK1TSDCFG_SHIFT 0x000CU
764
/**
765
* Regulator behavior in case of TSD
766
*/
767
#define FS8X_M_BOOSTTSDCFG_SHIFT 0x000DU
768
/**
769
* VBOOST Low Side slew rate control
770
*/
771
#define FS8X_M_VBSTSR_SHIFT 0x000EU
772
773
/**
774
* 130mA typical drive capability - slow
775
*/
776
#define FS8X_M_VPRESRHS_130MA_DRIVE_CAPABILITY (0x0000U << FS8X_M_VPRESRHS_SHIFT)
777
/**
778
* 260mA typical drive capability - medium
779
*/
780
#define FS8X_M_VPRESRHS_260MA_DRIVE_CAPABILITY (0x0001U << FS8X_M_VPRESRHS_SHIFT)
781
/**
782
* 520mA typical drive capability - fast
783
*/
784
#define FS8X_M_VPRESRHS_520MA_DRIVE_CAPABILITY (0x0002U << FS8X_M_VPRESRHS_SHIFT)
785
/**
786
* 900mA typical drive capability - ultra fast
787
*/
788
#define FS8X_M_VPRESRHS_900MA_DRIVE_CAPABILITY (0x0003U << FS8X_M_VPRESRHS_SHIFT)
789
790
/**
791
* 130mA typical drive capability - slow
792
*/
793
#define FS8X_M_VPRESRLS_130MA_DRIVE_CAPABILITY (0x0000U << FS8X_M_VPRESRLS_SHIFT)
794
/**
795
* 260mA typical drive capability - medium
796
*/
797
#define FS8X_M_VPRESRLS_260MA_DRIVE_CAPABILITY (0x0001U << FS8X_M_VPRESRLS_SHIFT)
798
/**
799
* 520mA typical drive capability - fast
800
*/
801
#define FS8X_M_VPRESRLS_520MA_DRIVE_CAPABILITY (0x0002U << FS8X_M_VPRESRLS_SHIFT)
802
/**
803
* 900mA typical drive capability - ultra fast
804
*/
805
#define FS8X_M_VPRESRLS_900MA_DRIVE_CAPABILITY (0x0003U << FS8X_M_VPRESRLS_SHIFT)
806
807
/**
808
* Regulator Shutdown
809
*/
810
#define FS8X_M_LDO2TSDCFG_REGULATOR_SHUTDOWN (0x0000U << FS8X_M_LDO2TSDCFG_SHIFT)
811
/**
812
* Regulator Shutdown + State machine transition to Standby mode
813
*/
814
#define FS8X_M_LDO2TSDCFG_REGULATOR_SHUTDOWN_AND_DEEP_FAIL_SAFE (0x0001U << FS8X_M_LDO2TSDCFG_SHIFT)
815
816
/**
817
* Regulator Shutdown
818
*/
819
#define FS8X_M_LDO1TSDCFG_REGULATOR_SHUTDOWN (0x0000U << FS8X_M_LDO1TSDCFG_SHIFT)
820
/**
821
* Regulator Shutdown + State machine transition to Standby mode
822
*/
823
#define FS8X_M_LDO1TSDCFG_REGULATOR_SHUTDOWN_AND_DEEP_FAIL_SAFE (0x0001U << FS8X_M_LDO1TSDCFG_SHIFT)
824
825
/**
826
* Regulator Shutdown
827
*/
828
#define FS8X_M_BUCK3TSDCFG_REGULATOR_SHUTDOWN (0x0000U << FS8X_M_BUCK3TSDCFG_SHIFT)
829
/**
830
* Regulator Shutdown + State machine transition to Standby mode
831
*/
832
#define FS8X_M_BUCK3TSDCFG_REGULATOR_SHUTDOWN_AND_DEEP_FAIL_SAFE (0x0001U << FS8X_M_BUCK3TSDCFG_SHIFT)
833
834
/**
835
* Regulator Shutdown
836
*/
837
#define FS8X_M_BUCK2TSDCFG_REGULATOR_SHUTDOWN (0x0000U << FS8X_M_BUCK2TSDCFG_SHIFT)
838
/**
839
* Regulator Shutdown + State machine transition to Standby mode
840
*/
841
#define FS8X_M_BUCK2TSDCFG_REGULATOR_SHUTDOWN_AND_DEEP_FAIL_SAFE (0x0001U << FS8X_M_BUCK2TSDCFG_SHIFT)
842
843
/**
844
* Regulator Shutdown
845
*/
846
#define FS8X_M_BUCK1TSDCFG_REGULATOR_SHUTDOWN (0x0000U << FS8X_M_BUCK1TSDCFG_SHIFT)
847
/**
848
* Regulator Shutdown + State machine transition to Standby mode
849
*/
850
#define FS8X_M_BUCK1TSDCFG_REGULATOR_SHUTDOWN_AND_DEEP_FAIL_SAFE (0x0001U << FS8X_M_BUCK1TSDCFG_SHIFT)
851
852
/**
853
* Regulator Shutdown
854
*/
855
#define FS8X_M_BOOSTTSDCFG_REGULATOR_SHUTDOWN (0x0000U << FS8X_M_BOOSTTSDCFG_SHIFT)
856
/**
857
* Regulator Shutdown + State machine transition to Standby mode
858
*/
859
#define FS8X_M_BOOSTTSDCFG_REGULATOR_SHUTDOWN_AND_DEEP_FAIL_SAFE (0x0001U << FS8X_M_BOOSTTSDCFG_SHIFT)
860
861
/**
862
* 50V/us
863
*/
864
#define FS8X_M_VBSTSR_50V_US (0x0000U << FS8X_M_VBSTSR_SHIFT)
865
/**
866
* 100V/us
867
*/
868
#define FS8X_M_VBSTSR_100V_US (0x0001U << FS8X_M_VBSTSR_SHIFT)
869
/**
870
* 300V/us
871
*/
872
#define FS8X_M_VBSTSR_300V_US (0x0002U << FS8X_M_VBSTSR_SHIFT)
873
/**
874
* 500V/us
875
*/
876
#define FS8X_M_VBSTSR_500V_US (0x0003U << FS8X_M_VBSTSR_SHIFT)
877
878
/******************************************************************************/
879
/* M_AMUX - Type: RW */
880
/******************************************************************************/
881
882
#define FS8X_M_AMUX_ADDR 0x04U
883
#define FS8X_M_AMUX_DEFAULT 0x0000U
884
885
/**
886
* Signal selection for AMUX output
887
*/
888
#define FS8X_M_AMUX_MASK 0x001FU
889
/**
890
* Selection of divider ratio for Vsup, Wake1, Wake 2 inputs
891
*/
892
#define FS8X_M_RATIO_MASK 0x0020U
893
894
/**
895
* Signal selection for AMUX output
896
*/
897
#define FS8X_M_AMUX_SHIFT 0x0000U
898
/**
899
* Selection of divider ratio for Vsup, Wake1, Wake 2 inputs
900
*/
901
#define FS8X_M_RATIO_SHIFT 0x0005U
902
903
/**
904
* GND
905
*/
906
#define FS8X_M_AMUX_GND (0x0000U << FS8X_M_AMUX_SHIFT)
907
/**
908
* VDDIO
909
*/
910
#define FS8X_M_AMUX_VDDIO (0x0001U << FS8X_M_AMUX_SHIFT)
911
/**
912
* Temperature Sensor : T(_C) = (VAMUX _ VTEMP25) / VTEMP_COEFF + 25
913
*/
914
#define FS8X_M_AMUX_TEMPERATURE_SENSOR (0x0002U << FS8X_M_AMUX_SHIFT)
915
/**
916
* Band Gap Main
917
*/
918
#define FS8X_M_AMUX_BAND_GAP_MAIN (0x0003U << FS8X_M_AMUX_SHIFT)
919
/**
920
* Band Gap Fail Safe
921
*/
922
#define FS8X_M_AMUX_BAND_GAP_FAIL_SAFE (0x0004U << FS8X_M_AMUX_SHIFT)
923
/**
924
* VBUCK1 voltage
925
*/
926
#define FS8X_M_AMUX_VBUCK1_VOLTAGE (0x0005U << FS8X_M_AMUX_SHIFT)
927
/**
928
* VBUCK2 voltage
929
*/
930
#define FS8X_M_AMUX_VBUCK2_VOLTAGE (0x0006U << FS8X_M_AMUX_SHIFT)
931
/**
932
* VBUCK3 voltage divided by 2.5
933
*/
934
#define FS8X_M_AMUX_VBUCK3_VOLTAGE_DIVIDED (0x0007U << FS8X_M_AMUX_SHIFT)
935
/**
936
* VPRE voltage divided by 2.5
937
*/
938
#define FS8X_M_AMUX_VPRE_VOLTAGE_DIVIDED (0x0008U << FS8X_M_AMUX_SHIFT)
939
/**
940
* VBOOST Voltage divided by 2.5
941
*/
942
#define FS8X_M_AMUX_VBOOST_VOLTAGE_DIVIDED (0x0009U << FS8X_M_AMUX_SHIFT)
943
/**
944
* VLDO1 voltage divided by 2.5
945
*/
946
#define FS8X_M_AMUX_VLDO1_VOLTAGE_DIVIDED (0x000AU << FS8X_M_AMUX_SHIFT)
947
/**
948
* VLDO2 voltage divided by 2.5
949
*/
950
#define FS8X_M_AMUX_VLDO2_VOLTAGE_DIVIDED (0x000BU << FS8X_M_AMUX_SHIFT)
951
/**
952
* VBOS voltage divided by 2.5
953
*/
954
#define FS8X_M_AMUX_VBOS_VOLTAGE_DIVIDED (0x000CU << FS8X_M_AMUX_SHIFT)
955
/**
956
* RESERVED
957
*/
958
#define FS8X_M_AMUX_RESERVED (0x000DU << FS8X_M_AMUX_SHIFT)
959
/**
960
* VSUP1 voltage divided by 7.5 or 14 (SPI/I2C configuration with bit RATIO)
961
*/
962
#define FS8X_M_AMUX_VSUP1_VOLTAGE_DIVIDED (0x000EU << FS8X_M_AMUX_SHIFT)
963
/**
964
* WAKE1 voltage divided by 7.5 or 14 (SPI/I2C configuration with bit RATIO)
965
*/
966
#define FS8X_M_AMUX_WAKE1_VOLTAGE_DIVIDED (0x000FU << FS8X_M_AMUX_SHIFT)
967
/**
968
* WAKE2 voltage divided by 7.5 or 14 (SPI/I2C configuration with bit RATIO)
969
*/
970
#define FS8X_M_AMUX_WAKE2_VOLTAGE_DIVIDED (0x0010U << FS8X_M_AMUX_SHIFT)
971
/**
972
* Vana: internal Main analog voltage supp
973
*/
974
#define FS8X_M_AMUX_VANA (0x0011U << FS8X_M_AMUX_SHIFT)
975
/**
976
* Vdig: internal Main digital voltage suppl
977
*/
978
#define FS8X_M_AMUX_VDIG (0x0012U << FS8X_M_AMUX_SHIFT)
979
/**
980
* Vdig_fs: internal Fail Safe digital voltage supp
981
*/
982
#define FS8X_M_AMUX_VDIG_FS (0x0013U << FS8X_M_AMUX_SHIFT)
983
/**
984
* PSYNC voltage
985
*/
986
#define FS8X_M_AMUX_PSYNC_VOLTAGE (0x0014U << FS8X_M_AMUX_SHIFT)
987
988
/**
989
* Ratio = 7.5
990
*/
991
#define FS8X_M_RATIO_RATIO_7_5 (0x0000U << FS8X_M_RATIO_SHIFT)
992
/**
993
* Ratio = 14
994
*/
995
#define FS8X_M_RATIO_RATIO_14 (0x0001U << FS8X_M_RATIO_SHIFT)
996
997
/******************************************************************************/
998
/* M_CLOCK - Type: RW */
999
/******************************************************************************/
1000
1001
#define FS8X_M_CLOCK_ADDR 0x05U
1002
#define FS8X_M_CLOCK_DEFAULT 0x0000U
1003
1004
/**
1005
* Oscillator Frequency [MHz]
1006
*/
1007
#define FS8X_M_CLK_TUNE_MASK 0x000FU
1008
/**
1009
* CLOCK Modulation
1010
*/
1011
#define FS8X_M_MOD_EN_MASK 0x0010U
1012
/**
1013
* FIN input signal divider selection
1014
*/
1015
#define FS8X_M_FIN_DIV_MASK 0x0020U
1016
/**
1017
* EXT FIN selection at PLL input
1018
*/
1019
#define FS8X_M_EXT_FIN_SEL_MASK 0x0040U
1020
/**
1021
* FOUT frequency selection (CLK1 or CLK2)
1022
*/
1023
#define FS8X_M_FOUT_CLK_SEL_MASK 0x0080U
1024
/**
1025
* FOUT phase shifting configuration.
1026
*/
1027
#define FS8X_M_FOUT_PHASE_MASK 0x0700U
1028
/**
1029
* Fout Multiplexer selection
1030
*/
1031
#define FS8X_M_FOUT_MUX_SEL_MASK 0x7800U
1032
/**
1033
* CLOCK Modulation Configuration
1034
*/
1035
#define FS8X_M_MOD_CONF_MASK 0x8000U
1036
1037
/**
1038
* Oscillator Frequency [MHz]
1039
*/
1040
#define FS8X_M_CLK_TUNE_SHIFT 0x0000U
1041
/**
1042
* CLOCK Modulation
1043
*/
1044
#define FS8X_M_MOD_EN_SHIFT 0x0004U
1045
/**
1046
* FIN input signal divider selection
1047
*/
1048
#define FS8X_M_FIN_DIV_SHIFT 0x0005U
1049
/**
1050
* EXT FIN selection at PLL input
1051
*/
1052
#define FS8X_M_EXT_FIN_SEL_SHIFT 0x0006U
1053
/**
1054
* FOUT frequency selection (CLK1 or CLK2)
1055
*/
1056
#define FS8X_M_FOUT_CLK_SEL_SHIFT 0x0007U
1057
/**
1058
* FOUT phase shifting configuration.
1059
*/
1060
#define FS8X_M_FOUT_PHASE_SHIFT 0x0008U
1061
/**
1062
* Fout Multiplexer selection
1063
*/
1064
#define FS8X_M_FOUT_MUX_SEL_SHIFT 0x000BU
1065
/**
1066
* CLOCK Modulation Configuration
1067
*/
1068
#define FS8X_M_MOD_CONF_SHIFT 0x000FU
1069
1070
/**
1071
* 20
1072
*/
1073
#define FS8X_M_CLK_TUNE_20 (0x0000U << FS8X_M_CLK_TUNE_SHIFT)
1074
/**
1075
* 21
1076
*/
1077
#define FS8X_M_CLK_TUNE_21 (0x0001U << FS8X_M_CLK_TUNE_SHIFT)
1078
/**
1079
* 22
1080
*/
1081
#define FS8X_M_CLK_TUNE_22 (0x0002U << FS8X_M_CLK_TUNE_SHIFT)
1082
/**
1083
* 23
1084
*/
1085
#define FS8X_M_CLK_TUNE_23 (0x0003U << FS8X_M_CLK_TUNE_SHIFT)
1086
/**
1087
* 24
1088
*/
1089
#define FS8X_M_CLK_TUNE_24 (0x0004U << FS8X_M_CLK_TUNE_SHIFT)
1090
/**
1091
* 16
1092
*/
1093
#define FS8X_M_CLK_TUNE_16 (0x0009U << FS8X_M_CLK_TUNE_SHIFT)
1094
/**
1095
* 17
1096
*/
1097
#define FS8X_M_CLK_TUNE_17 (0x000AU << FS8X_M_CLK_TUNE_SHIFT)
1098
/**
1099
* 18
1100
*/
1101
#define FS8X_M_CLK_TUNE_18 (0x000BU << FS8X_M_CLK_TUNE_SHIFT)
1102
/**
1103
* 19
1104
*/
1105
#define FS8X_M_CLK_TUNE_19 (0x000CU << FS8X_M_CLK_TUNE_SHIFT)
1106
1107
/**
1108
* Modulation Disable
1109
*/
1110
#define FS8X_M_MOD_EN_MODULATION_DISABLE (0x0000U << FS8X_M_MOD_EN_SHIFT)
1111
/**
1112
* Modulation Enable
1113
*/
1114
#define FS8X_M_MOD_EN_MODULATION_ENABLE (0x0001U << FS8X_M_MOD_EN_SHIFT)
1115
1116
/**
1117
* Divider by 1
1118
*/
1119
#define FS8X_M_FIN_DIV_DIVIDER_BY_1 (0x0000U << FS8X_M_FIN_DIV_SHIFT)
1120
/**
1121
* Divider by 6
1122
*/
1123
#define FS8X_M_FIN_DIV_DIVIDER_BY_6 (0x0001U << FS8X_M_FIN_DIV_SHIFT)
1124
1125
/**
1126
* DIS
1127
*/
1128
#define FS8X_M_EXT_FIN_SEL_DIS (0x0000U << FS8X_M_EXT_FIN_SEL_SHIFT)
1129
/**
1130
* EN
1131
*/
1132
#define FS8X_M_EXT_FIN_SEL_EN (0x0001U << FS8X_M_EXT_FIN_SEL_SHIFT)
1133
1134
/**
1135
* CLK1
1136
*/
1137
#define FS8X_M_FOUT_CLK_SEL_CLK1 (0x0000U << FS8X_M_FOUT_CLK_SEL_SHIFT)
1138
/**
1139
* CLK2
1140
*/
1141
#define FS8X_M_FOUT_CLK_SEL_CLK2 (0x0001U << FS8X_M_FOUT_CLK_SEL_SHIFT)
1142
1143
/**
1144
* No shift
1145
*/
1146
#define FS8X_M_FOUT_PHASE_NO_SHIFT (0x0000U << FS8X_M_FOUT_PHASE_SHIFT)
1147
/**
1148
* Shifted by 1 clock cycle of CLK running at 20MHz
1149
*/
1150
#define FS8X_M_FOUT_PHASE_1CLK (0x0001U << FS8X_M_FOUT_PHASE_SHIFT)
1151
/**
1152
* Shifted by 2 clock cycle of CLK running at 20MHz
1153
*/
1154
#define FS8X_M_FOUT_PHASE_2CLK (0x0002U << FS8X_M_FOUT_PHASE_SHIFT)
1155
/**
1156
* Shifted by 3 clock cycle of CLK running at 20MHz
1157
*/
1158
#define FS8X_M_FOUT_PHASE_3CLK (0x0003U << FS8X_M_FOUT_PHASE_SHIFT)
1159
/**
1160
* Shifted by 4 clock cycle of CLK running at 20MHz
1161
*/
1162
#define FS8X_M_FOUT_PHASE_4CLK (0x0004U << FS8X_M_FOUT_PHASE_SHIFT)
1163
/**
1164
* Shifted by 5 clock cycle of CLK running at 20MHz
1165
*/
1166
#define FS8X_M_FOUT_PHASE_5CLK (0x0005U << FS8X_M_FOUT_PHASE_SHIFT)
1167
/**
1168
* Shifted by 6 clock cycle of CLK running at 20MHz
1169
*/
1170
#define FS8X_M_FOUT_PHASE_6CLK (0x0006U << FS8X_M_FOUT_PHASE_SHIFT)
1171
/**
1172
* Shifted by 7 clock cycle of CLK running at 20MHz
1173
*/
1174
#define FS8X_M_FOUT_PHASE_7CLK (0x0007U << FS8X_M_FOUT_PHASE_SHIFT)
1175
1176
/**
1177
* No signal, Fout Low
1178
*/
1179
#define FS8X_M_FOUT_MUX_SEL_NO_SIGNAL (0x0000U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1180
/**
1181
* VPRE_clk
1182
*/
1183
#define FS8X_M_FOUT_MUX_SEL_VPRE_CLK (0x0001U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1184
/**
1185
* BOOST_clk
1186
*/
1187
#define FS8X_M_FOUT_MUX_SEL_BOOST_CLK (0x0002U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1188
/**
1189
* BUCK1_clk
1190
*/
1191
#define FS8X_M_FOUT_MUX_SEL_BUCK1_CLK (0x0003U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1192
/**
1193
* BUCK2_clk
1194
*/
1195
#define FS8X_M_FOUT_MUX_SEL_BUCK2_CLK (0x0004U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1196
/**
1197
* BUCK3_clk
1198
*/
1199
#define FS8X_M_FOUT_MUX_SEL_BUCK3_CLK (0x0005U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1200
/**
1201
* CLK1 or CLK2 selected with FOUT_CLK_SEL bit
1202
*/
1203
#define FS8X_M_FOUT_MUX_SEL_FOUT_CLK (0x0006U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1204
/**
1205
* OSC_MAIN/48
1206
*/
1207
#define FS8X_M_FOUT_MUX_SEL_OSC_MAIN_48 (0x0007U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1208
/**
1209
* OSC_FS/48
1210
*/
1211
#define FS8X_M_FOUT_MUX_SEL_OSC_FS_48 (0x0008U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1212
/**
1213
* CLOCK_FIN_DIV
1214
*/
1215
#define FS8X_M_FOUT_MUX_SEL_CLOCK_FIN_DIV (0x0009U << FS8X_M_FOUT_MUX_SEL_SHIFT)
1216
1217
/**
1218
* range +- 5% 23kHz
1219
*/
1220
#define FS8X_M_MOD_CONF_23KHZ (0x0000U << FS8X_M_MOD_CONF_SHIFT)
1221
/**
1222
* range +- 5% 94kHz
1223
*/
1224
#define FS8X_M_MOD_CONF_94KHZ (0x0001U << FS8X_M_MOD_CONF_SHIFT)
1225
1226
/******************************************************************************/
1227
/* M_INT_MASK1 - Type: RW */
1228
/******************************************************************************/
1229
1230
#define FS8X_M_INT_MASK1_ADDR 0x06U
1231
#define FS8X_M_INT_MASK1_DEFAULT 0x0000U
1232
1233
/**
1234
* Inhibit INTERRUPT for LDO2 over temperature shutdown event
1235
*/
1236
#define FS8X_M_LDO2TSD_M_MASK 0x0001U
1237
/**
1238
* Inhibit INTERRUPT for LDO1 over temperature shutdown event
1239
*/
1240
#define FS8X_M_LDO1TSD_M_MASK 0x0002U
1241
/**
1242
* Inhibit INTERRUPT for BUCK3 over temperature shutdown event
1243
*/
1244
#define FS8X_M_BUCK3TSD_M_MASK 0x0004U
1245
/**
1246
* Inhibit INTERRUPT for BUCK2 over temperature shutdown event
1247
*/
1248
#define FS8X_M_BUCK2TSD_M_MASK 0x0008U
1249
/**
1250
* Inhibit INTERRUPT for BUCK1 over temperature shutdown event
1251
*/
1252
#define FS8X_M_BUCK1TSD_M_MASK 0x0010U
1253
/**
1254
* Inhibit INTERRUPT for BOOST over temperature shutdown event
1255
*/
1256
#define FS8X_M_BOOSTTSD_M_MASK 0x0020U
1257
/**
1258
* Inhibit INTERRUPT for Best Of Supply over temperature shutdown event
1259
*/
1260
#define FS8X_M_BOSTSD_M_MASK 0x0040U
1261
/**
1262
* Inhibit INTERRUPT for LDO2 Over current
1263
*/
1264
#define FS8X_M_LDO2OC_M_MASK 0x0100U
1265
/**
1266
* Inhibit INTERRUPT for LDO1 Over current
1267
*/
1268
#define FS8X_M_LDO1OC_M_MASK 0x0200U
1269
/**
1270
* Inhibit INTERRUPT for BUCK3 Over current
1271
*/
1272
#define FS8X_M_BUCK3OC_M_MASK 0x0400U
1273
/**
1274
* Inhibit INTERRUPT for BUCK2 Over current
1275
*/
1276
#define FS8X_M_BUCK2OC_M_MASK 0x0800U
1277
/**
1278
* Inhibit INTERRUPT for BUCK1 Over current
1279
*/
1280
#define FS8X_M_BUCK1OC_M_MASK 0x1000U
1281
/**
1282
* Inhibit INTERRUPT for VBOOST Over current
1283
*/
1284
#define FS8X_M_BOOSTOC_M_MASK 0x2000U
1285
/**
1286
* Inhibit INTERRUPT for VPRE Over current
1287
*/
1288
#define FS8X_M_VPREOC_M_MASK 0x4000U
1289
1290
/**
1291
* Inhibit INTERRUPT for LDO2 over temperature shutdown event
1292
*/
1293
#define FS8X_M_LDO2TSD_M_SHIFT 0x0000U
1294
/**
1295
* Inhibit INTERRUPT for LDO1 over temperature shutdown event
1296
*/
1297
#define FS8X_M_LDO1TSD_M_SHIFT 0x0001U
1298
/**
1299
* Inhibit INTERRUPT for BUCK3 over temperature shutdown event
1300
*/
1301
#define FS8X_M_BUCK3TSD_M_SHIFT 0x0002U
1302
/**
1303
* Inhibit INTERRUPT for BUCK2 over temperature shutdown event
1304
*/
1305
#define FS8X_M_BUCK2TSD_M_SHIFT 0x0003U
1306
/**
1307
* Inhibit INTERRUPT for BUCK1 over temperature shutdown event
1308
*/
1309
#define FS8X_M_BUCK1TSD_M_SHIFT 0x0004U
1310
/**
1311
* Inhibit INTERRUPT for BOOST over temperature shutdown event
1312
*/
1313
#define FS8X_M_BOOSTTSD_M_SHIFT 0x0005U
1314
/**
1315
* Inhibit INTERRUPT for Best Of Supply over temperature shutdown event
1316
*/
1317
#define FS8X_M_BOSTSD_M_SHIFT 0x0006U
1318
/**
1319
* Inhibit INTERRUPT for LDO2 Over current
1320
*/
1321
#define FS8X_M_LDO2OC_M_SHIFT 0x0008U
1322
/**
1323
* Inhibit INTERRUPT for LDO1 Over current
1324
*/
1325
#define FS8X_M_LDO1OC_M_SHIFT 0x0009U
1326
/**
1327
* Inhibit INTERRUPT for BUCK3 Over current
1328
*/
1329
#define FS8X_M_BUCK3OC_M_SHIFT 0x000AU
1330
/**
1331
* Inhibit INTERRUPT for BUCK2 Over current
1332
*/
1333
#define FS8X_M_BUCK2OC_M_SHIFT 0x000BU
1334
/**
1335
* Inhibit INTERRUPT for BUCK1 Over current
1336
*/
1337
#define FS8X_M_BUCK1OC_M_SHIFT 0x000CU
1338
/**
1339
* Inhibit INTERRUPT for VBOOST Over current
1340
*/
1341
#define FS8X_M_BOOSTOC_M_SHIFT 0x000DU
1342
/**
1343
* Inhibit INTERRUPT for VPRE Over current
1344
*/
1345
#define FS8X_M_VPREOC_M_SHIFT 0x000EU
1346
1347
/**
1348
* INT not masked
1349
*/
1350
#define FS8X_M_LDO2TSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_LDO2TSD_M_SHIFT)
1351
/**
1352
* INT masked
1353
*/
1354
#define FS8X_M_LDO2TSD_M_INT_MASKED (0x0001U << FS8X_M_LDO2TSD_M_SHIFT)
1355
1356
/**
1357
* INT not masked
1358
*/
1359
#define FS8X_M_LDO1TSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_LDO1TSD_M_SHIFT)
1360
/**
1361
* INT masked
1362
*/
1363
#define FS8X_M_LDO1TSD_M_INT_MASKED (0x0001U << FS8X_M_LDO1TSD_M_SHIFT)
1364
1365
/**
1366
* INT not masked
1367
*/
1368
#define FS8X_M_BUCK3TSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_BUCK3TSD_M_SHIFT)
1369
/**
1370
* INT masked
1371
*/
1372
#define FS8X_M_BUCK3TSD_M_INT_MASKED (0x0001U << FS8X_M_BUCK3TSD_M_SHIFT)
1373
1374
/**
1375
* INT not masked
1376
*/
1377
#define FS8X_M_BUCK2TSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_BUCK2TSD_M_SHIFT)
1378
/**
1379
* INT masked
1380
*/
1381
#define FS8X_M_BUCK2TSD_M_INT_MASKED (0x0001U << FS8X_M_BUCK2TSD_M_SHIFT)
1382
1383
/**
1384
* INT not masked
1385
*/
1386
#define FS8X_M_BUCK1TSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_BUCK1TSD_M_SHIFT)
1387
/**
1388
* INT masked
1389
*/
1390
#define FS8X_M_BUCK1TSD_M_INT_MASKED (0x0001U << FS8X_M_BUCK1TSD_M_SHIFT)
1391
1392
/**
1393
* INT not masked
1394
*/
1395
#define FS8X_M_BOOSTTSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_BOOSTTSD_M_SHIFT)
1396
/**
1397
* INT masked
1398
*/
1399
#define FS8X_M_BOOSTTSD_M_INT_MASKED (0x0001U << FS8X_M_BOOSTTSD_M_SHIFT)
1400
1401
/**
1402
* INT not masked
1403
*/
1404
#define FS8X_M_BOSTSD_M_INT_NOT_MASKED (0x0000U << FS8X_M_BOSTSD_M_SHIFT)
1405
/**
1406
* INT masked
1407
*/
1408
#define FS8X_M_BOSTSD_M_INT_MASKED (0x0001U << FS8X_M_BOSTSD_M_SHIFT)
1409
1410
/**
1411
* INT not masked
1412
*/
1413
#define FS8X_M_LDO2OC_M_INT_NOT_MASKED (0x0000U << FS8X_M_LDO2OC_M_SHIFT)
1414
/**
1415
* INT masked
1416
*/
1417
#define FS8X_M_LDO2OC_M_INT_MASKED (0x0001U << FS8X_M_LDO2OC_M_SHIFT)
1418
1419
/**
1420
* INT not masked
1421
*/
1422
#define FS8X_M_LDO1OC_M_INT_NOT_MASKED (0x0000U << FS8X_M_LDO1OC_M_SHIFT)
1423
/**
1424
* INT masked
1425
*/
1426
#define FS8X_M_LDO1OC_M_INT_MASKED (0x0001U << FS8X_M_LDO1OC_M_SHIFT)
1427
1428
/**
1429
* INT not masked
1430
*/
1431
#define FS8X_M_BUCK3OC_M_INT_NOT_MASKED (0x0000U << FS8X_M_BUCK3OC_M_SHIFT)
1432
/**
1433
* INT masked
1434
*/
1435
#define FS8X_M_BUCK3OC_M_INT_MASKED (0x0001U << FS8X_M_BUCK3OC_M_SHIFT)
1436
1437
/**
1438
* INT not masked
1439
*/
1440
#define FS8X_M_BUCK2OC_M_INT_NOT_MASKED (0x0000U << FS8X_M_BUCK2OC_M_SHIFT)
1441
/**
1442
* INT masked
1443
*/
1444
#define FS8X_M_BUCK2OC_M_INT_MASKED (0x0001U << FS8X_M_BUCK2OC_M_SHIFT)
1445
1446
/**
1447
* INT not masked
1448
*/
1449
#define FS8X_M_BUCK1OC_M_INT_NOT_MASKED (0x0000U << FS8X_M_BUCK1OC_M_SHIFT)
1450
/**
1451
* INT masked
1452
*/
1453
#define FS8X_M_BUCK1OC_M_INT_MASKED (0x0001U << FS8X_M_BUCK1OC_M_SHIFT)
1454
1455
/**
1456
* INT not masked
1457
*/
1458
#define FS8X_M_BOOSTOC_M_INT_NOT_MASKED (0x0000U << FS8X_M_BOOSTOC_M_SHIFT)
1459
/**
1460
* INT masked
1461
*/
1462
#define FS8X_M_BOOSTOC_M_INT_MASKED (0x0001U << FS8X_M_BOOSTOC_M_SHIFT)
1463
1464
/**
1465
* INT not masked
1466
*/
1467
#define FS8X_M_VPREOC_M_INT_NOT_MASKED (0x0000U << FS8X_M_VPREOC_M_SHIFT)
1468
/**
1469
* INT masked
1470
*/
1471
#define FS8X_M_VPREOC_M_INT_MASKED (0x0001U << FS8X_M_VPREOC_M_SHIFT)
1472
1473
/******************************************************************************/
1474
/* M_INT_MASK2 - Type: RW */
1475
/******************************************************************************/
1476
1477
#define FS8X_M_INT_MASK2_ADDR 0x07U
1478
#define FS8X_M_INT_MASK2_DEFAULT 0x0000U
1479
1480
/**
1481
* Inhibit INTERRUPT for WAKE2 any transition
1482
*/
1483
#define FS8X_M_WAKE2_M_MASK 0x0001U
1484
/**
1485
* Inhibit INTERRUPT for WAKE1 any transition
1486
*/
1487
#define FS8X_M_WAKE1_M_MASK 0x0002U
1488
/**
1489
* Inhibit INTERRUPT for VSUP_UVH
1490
*/
1491
#define FS8X_M_VSUPUVH_M_MASK 0x0004U
1492
/**
1493
* Inhibit INTERRUPT for VSUP_UVL
1494
*/
1495
#define FS8X_M_VSUPUVL_M_MASK 0x0008U
1496
/**
1497
* Inhibit INTERRUPT for VPRE_UVH
1498
*/
1499
#define FS8X_M_VPREUVH_M_MASK 0x0010U
1500
/**
1501
* Inhibit INTERRUPT for VPRE_UVL
1502
*/
1503
#define FS8X_M_VPREUVL_M_MASK 0x0020U
1504
/**
1505
* Inhibit INTERRUPT for VSUP_UV7
1506
*/
1507
#define FS8X_M_VSUPUV7_M_MASK 0x0040U
1508
/**
1509
* Inhibit INTERRUPT for VBOOST_UVH
1510
*/
1511
#define FS8X_M_VBOOST_UVH_M_MASK 0x0080U
1512
/**
1513
* Inhibit INTERRUPT for VPRE_FB_OV
1514
*/
1515
#define FS8X_M_VPRE_FB_OV_M_MASK 0x0100U
1516
/**
1517
* Inhibit INTERRUPT for COM any transition
1518
*/
1519
#define FS8X_M_COM_M_MASK 0x0200U
1520
/**
1521
* Inhibit INTERRUPT for VBOS_UVH any transition
1522
*/
1523
#define FS8X_M_VBOSUVH_M_MASK 0x0400U
1524
/**
1525
* Inhibit INTERRUPT for VBOOST_OV any transition
1526
*/
1527
#define FS8X_M_VBOOSTOV_M_MASK 0x0800U
1528
1529
/**
1530
* Inhibit INTERRUPT for WAKE2 any transition
1531
*/
1532
#define FS8X_M_WAKE2_M_SHIFT 0x0000U
1533
/**
1534
* Inhibit INTERRUPT for WAKE1 any transition
1535
*/
1536
#define FS8X_M_WAKE1_M_SHIFT 0x0001U
1537
/**
1538
* Inhibit INTERRUPT for VSUP_UVH
1539
*/
1540
#define FS8X_M_VSUPUVH_M_SHIFT 0x0002U
1541
/**
1542
* Inhibit INTERRUPT for VSUP_UVL
1543
*/
1544
#define FS8X_M_VSUPUVL_M_SHIFT 0x0003U
1545
/**
1546
* Inhibit INTERRUPT for VPRE_UVH
1547
*/
1548
#define FS8X_M_VPREUVH_M_SHIFT 0x0004U
1549
/**
1550
* Inhibit INTERRUPT for VPRE_UVL
1551
*/
1552
#define FS8X_M_VPREUVL_M_SHIFT 0x0005U
1553
/**
1554
* Inhibit INTERRUPT for VSUP_UV7
1555
*/
1556
#define FS8X_M_VSUPUV7_M_SHIFT 0x0006U
1557
/**
1558
* Inhibit INTERRUPT for VBOOST_UVH
1559
*/
1560
#define FS8X_M_VBOOST_UVH_M_SHIFT 0x0007U
1561
/**
1562
* Inhibit INTERRUPT for VPRE_FB_OV
1563
*/
1564
#define FS8X_M_VPRE_FB_OV_M_SHIFT 0x0008U
1565
/**
1566
* Inhibit INTERRUPT for COM any transition
1567
*/
1568
#define FS8X_M_COM_M_SHIFT 0x0009U
1569
/**
1570
* Inhibit INTERRUPT for VBOS_UVH any transition
1571
*/
1572
#define FS8X_M_VBOSUVH_M_SHIFT 0x000AU
1573
/**
1574
* Inhibit INTERRUPT for VBOOST_OV any transition
1575
*/
1576
#define FS8X_M_VBOOSTOV_M_SHIFT 0x000BU
1577
1578
/**
1579
* INT not masked
1580
*/
1581
#define FS8X_M_WAKE2_M_INT_NOT_MASKED (0x0000U << FS8X_M_WAKE2_M_SHIFT)
1582
/**
1583
* INT masked
1584
*/
1585
#define FS8X_M_WAKE2_M_INT_MASKED (0x0001U << FS8X_M_WAKE2_M_SHIFT)
1586
1587
/**
1588
* INT not masked
1589
*/
1590
#define FS8X_M_WAKE1_M_INT_NOT_MASKED (0x0000U << FS8X_M_WAKE1_M_SHIFT)
1591
/**
1592
* INT masked
1593
*/
1594
#define FS8X_M_WAKE1_M_INT_MASKED (0x0001U << FS8X_M_WAKE1_M_SHIFT)
1595
1596
/**
1597
* INT not masked
1598
*/
1599
#define FS8X_M_VSUPUVH_M_INT_NOT_MASKED (0x0000U << FS8X_M_VSUPUVH_M_SHIFT)
1600
/**
1601
* INT masked
1602
*/
1603
#define FS8X_M_VSUPUVH_M_INT_MASKED (0x0001U << FS8X_M_VSUPUVH_M_SHIFT)
1604
1605
/**
1606
* INT not masked
1607
*/
1608
#define FS8X_M_VSUPUVL_M_INT_NOT_MASKED (0x0000U << FS8X_M_VSUPUVL_M_SHIFT)
1609
/**
1610
* INT masked
1611
*/
1612
#define FS8X_M_VSUPUVL_M_INT_MASKED (0x0001U << FS8X_M_VSUPUVL_M_SHIFT)
1613
1614
/**
1615
* INT not masked
1616
*/
1617
#define FS8X_M_VPREUVH_M_INT_NOT_MASKED (0x0000U << FS8X_M_VPREUVH_M_SHIFT)
1618
/**
1619
* INT masked
1620
*/
1621
#define FS8X_M_VPREUVH_M_INT_MASKED (0x0001U << FS8X_M_VPREUVH_M_SHIFT)
1622
1623
/**
1624
* INT not masked
1625
*/
1626
#define FS8X_M_VPREUVL_M_INT_NOT_MASKED (0x0000U << FS8X_M_VPREUVL_M_SHIFT)
1627
/**
1628
* INT masked
1629
*/
1630
#define FS8X_M_VPREUVL_M_INT_MASKED (0x0001U << FS8X_M_VPREUVL_M_SHIFT)
1631
1632
/**
1633
* INT not masked
1634
*/
1635
#define FS8X_M_VSUPUV7_M_INT_NOT_MASKED (0x0000U << FS8X_M_VSUPUV7_M_SHIFT)
1636
/**
1637
* INT masked
1638
*/
1639
#define FS8X_M_VSUPUV7_M_INT_MASKED (0x0001U << FS8X_M_VSUPUV7_M_SHIFT)
1640
1641
/**
1642
* INT not masked
1643
*/
1644
#define FS8X_M_VBOOST_UVH_M_INT_NOT_MASKED (0x0000U << FS8X_M_VBOOST_UVH_M_SHIFT)
1645
/**
1646
* INT masked
1647
*/
1648
#define FS8X_M_VBOOST_UVH_M_INT_MASKED (0x0001U << FS8X_M_VBOOST_UVH_M_SHIFT)
1649
1650
/**
1651
* INT not masked
1652
*/
1653
#define FS8X_M_VPRE_FB_OV_M_INT_NOT_MASKED (0x0000U << FS8X_M_VPRE_FB_OV_M_SHIFT)
1654
/**
1655
* INT masked
1656
*/
1657
#define FS8X_M_VPRE_FB_OV_M_INT_MASKED (0x0001U << FS8X_M_VPRE_FB_OV_M_SHIFT)
1658
1659
/**
1660
* INT not masked
1661
*/
1662
#define FS8X_M_COM_M_INT_NOT_MASKED (0x0000U << FS8X_M_COM_M_SHIFT)
1663
/**
1664
* INT masked
1665
*/
1666
#define FS8X_M_COM_M_INT_MASKED (0x0001U << FS8X_M_COM_M_SHIFT)
1667
1668
/**
1669
* INT not masked
1670
*/
1671
#define FS8X_M_VBOSUVH_M_INT_NOT_MASKED (0x0000U << FS8X_M_VBOSUVH_M_SHIFT)
1672
/**
1673
* INT masked
1674
*/
1675
#define FS8X_M_VBOSUVH_M_INT_MASKED (0x0001U << FS8X_M_VBOSUVH_M_SHIFT)
1676
1677
/**
1678
* INT not masked
1679
*/
1680
#define FS8X_M_VBOOSTOV_M_INT_NOT_MASKED (0x0000U << FS8X_M_VBOOSTOV_M_SHIFT)
1681
/**
1682
* INT masked
1683
*/
1684
#define FS8X_M_VBOOSTOV_M_INT_MASKED (0x0001U << FS8X_M_VBOOSTOV_M_SHIFT)
1685
1686
/******************************************************************************/
1687
/* M_FLAG1 - Type: RW */
1688
/******************************************************************************/
1689
1690
#define FS8X_M_FLAG1_ADDR 0x08U
1691
#define FS8X_M_FLAG1_DEFAULT 0x0000U
1692
1693
/**
1694
* LDO2 over temperature shutdown event
1695
*/
1696
#define FS8X_M_LDO2OT_MASK 0x0001U
1697
/**
1698
* LDO1 over temperature shutdown event
1699
*/
1700
#define FS8X_M_LDO1OT_MASK 0x0002U
1701
/**
1702
* BUCK3 over temperature shutdown event
1703
*/
1704
#define FS8X_M_BUCK3OT_MASK 0x0004U
1705
/**
1706
* BUCK2 over temperature shutdown event
1707
*/
1708
#define FS8X_M_BUCK2OT_MASK 0x0008U
1709
/**
1710
* BUCK1 over temperature shutdown event
1711
*/
1712
#define FS8X_M_BUCK1OT_MASK 0x0010U
1713
/**
1714
* VBOOST over temperature shutdown event
1715
*/
1716
#define FS8X_M_VBOOSTOT_MASK 0x0020U
1717
/**
1718
* VBOOST Over voltage protection event
1719
*/
1720
#define FS8X_M_VBOOSTOV_MASK 0x0040U
1721
/**
1722
* CLK_FIN_DIV monitoring
1723
*/
1724
#define FS8X_M_CLK_FIN_DIV_OK_MASK 0x0080U
1725
/**
1726
* LDO2 Over current event
1727
*/
1728
#define FS8X_M_LDO2OC_MASK 0x0100U
1729
/**
1730
* LDO1 Over current event
1731
*/
1732
#define FS8X_M_LDO1OC_MASK 0x0200U
1733
/**
1734
* BUCK3 Over current
1735
*/
1736
#define FS8X_M_BUCK3OC_MASK 0x0400U
1737
/**
1738
* BUCK2 Over current
1739
*/
1740
#define FS8X_M_BUCK2OC_MASK 0x0800U
1741
/**
1742
* BUCK1 Over current
1743
*/
1744
#define FS8X_M_BUCK1OC_MASK 0x1000U
1745
/**
1746
* VPRE Over current event
1747
*/
1748
#define FS8X_M_VPREOC_MASK 0x2000U
1749
/**
1750
* VBOOST Under voltage high event (falling)
1751
*/
1752
#define FS8X_M_VBOOSTUVH_MASK 0x4000U
1753
/**
1754
* VBOS Under voltage high event (falling)
1755
*/
1756
#define FS8X_M_VBOSUVH_MASK 0x8000U
1757
1758
/**
1759
* LDO2 over temperature shutdown event
1760
*/
1761
#define FS8X_M_LDO2OT_SHIFT 0x0000U
1762
/**
1763
* LDO1 over temperature shutdown event
1764
*/
1765
#define FS8X_M_LDO1OT_SHIFT 0x0001U
1766
/**
1767
* BUCK3 over temperature shutdown event
1768
*/
1769
#define FS8X_M_BUCK3OT_SHIFT 0x0002U
1770
/**
1771
* BUCK2 over temperature shutdown event
1772
*/
1773
#define FS8X_M_BUCK2OT_SHIFT 0x0003U
1774
/**
1775
* BUCK1 over temperature shutdown event
1776
*/
1777
#define FS8X_M_BUCK1OT_SHIFT 0x0004U
1778
/**
1779
* VBOOST over temperature shutdown event
1780
*/
1781
#define FS8X_M_VBOOSTOT_SHIFT 0x0005U
1782
/**
1783
* VBOOST Over voltage protection event
1784
*/
1785
#define FS8X_M_VBOOSTOV_SHIFT 0x0006U
1786
/**
1787
* CLK_FIN_DIV monitoring
1788
*/
1789
#define FS8X_M_CLK_FIN_DIV_OK_SHIFT 0x0007U
1790
/**
1791
* LDO2 Over current event
1792
*/
1793
#define FS8X_M_LDO2OC_SHIFT 0x0008U
1794
/**
1795
* LDO1 Over current event
1796
*/
1797
#define FS8X_M_LDO1OC_SHIFT 0x0009U
1798
/**
1799
* BUCK3 Over current
1800
*/
1801
#define FS8X_M_BUCK3OC_SHIFT 0x000AU
1802
/**
1803
* BUCK2 Over current
1804
*/
1805
#define FS8X_M_BUCK2OC_SHIFT 0x000BU
1806
/**
1807
* BUCK1 Over current
1808
*/
1809
#define FS8X_M_BUCK1OC_SHIFT 0x000CU
1810
/**
1811
* VPRE Over current event
1812
*/
1813
#define FS8X_M_VPREOC_SHIFT 0x000DU
1814
/**
1815
* VBOOST Under voltage high event (falling)
1816
*/
1817
#define FS8X_M_VBOOSTUVH_SHIFT 0x000EU
1818
/**
1819
* VBOS Under voltage high event (falling)
1820
*/
1821
#define FS8X_M_VBOSUVH_SHIFT 0x000FU
1822
1823
/**
1824
* No event
1825
*/
1826
#define FS8X_M_LDO2OT_NO_EVENT (0x0000U << FS8X_M_LDO2OT_SHIFT)
1827
/**
1828
* Event occurred
1829
*/
1830
#define FS8X_M_LDO2OT_EVENT_OCCURRED (0x0001U << FS8X_M_LDO2OT_SHIFT)
1831
1832
/**
1833
* No event
1834
*/
1835
#define FS8X_M_LDO1OT_NO_EVENT (0x0000U << FS8X_M_LDO1OT_SHIFT)
1836
/**
1837
* Event occurred
1838
*/
1839
#define FS8X_M_LDO1OT_EVENT_OCCURRED (0x0001U << FS8X_M_LDO1OT_SHIFT)
1840
1841
/**
1842
* No event
1843
*/
1844
#define FS8X_M_BUCK3OT_NO_EVENT (0x0000U << FS8X_M_BUCK3OT_SHIFT)
1845
/**
1846
* Event occurred
1847
*/
1848
#define FS8X_M_BUCK3OT_EVENT_OCCURRED (0x0001U << FS8X_M_BUCK3OT_SHIFT)
1849
1850
/**
1851
* No event
1852
*/
1853
#define FS8X_M_BUCK2OT_NO_EVENT (0x0000U << FS8X_M_BUCK2OT_SHIFT)
1854
/**
1855
* Event occurred
1856
*/
1857
#define FS8X_M_BUCK2OT_EVENT_OCCURRED (0x0001U << FS8X_M_BUCK2OT_SHIFT)
1858
1859
/**
1860
* No event
1861
*/
1862
#define FS8X_M_BUCK1OT_NO_EVENT (0x0000U << FS8X_M_BUCK1OT_SHIFT)
1863
/**
1864
* Event occurred
1865
*/
1866
#define FS8X_M_BUCK1OT_EVENT_OCCURRED (0x0001U << FS8X_M_BUCK1OT_SHIFT)
1867
1868
/**
1869
* No event
1870
*/
1871
#define FS8X_M_VBOOSTOT_NO_EVENT (0x0000U << FS8X_M_VBOOSTOT_SHIFT)
1872
/**
1873
* Event occurred
1874
*/
1875
#define FS8X_M_VBOOSTOT_EVENT_OCCURRED (0x0001U << FS8X_M_VBOOSTOT_SHIFT)
1876
1877
/**
1878
* No event
1879
*/
1880
#define FS8X_M_VBOOSTOV_NO_EVENT (0x0000U << FS8X_M_VBOOSTOV_SHIFT)
1881
/**
1882
* Event occurred
1883
*/
1884
#define FS8X_M_VBOOSTOV_EVENT_OCCURRED (0x0001U << FS8X_M_VBOOSTOV_SHIFT)
1885
1886
/**
1887
* Not OK : FINERR_LONG < CLK_FIN_DIV deviation < FINERR_SHORT
1888
*/
1889
#define FS8X_M_CLK_FIN_DIV_OK_NOT_OK (0x0000U << FS8X_M_CLK_FIN_DIV_OK_SHIFT)
1890
/**
1891
* OK : FINERR_SHORT < CLK_FIN_DIV deviation < FINERR_LONG
1892
*/
1893
#define FS8X_M_CLK_FIN_DIV_OK_OK (0x0001U << FS8X_M_CLK_FIN_DIV_OK_SHIFT)
1894
1895
/**
1896
* No event
1897
*/
1898
#define FS8X_M_LDO2OC_NO_EVENT (0x0000U << FS8X_M_LDO2OC_SHIFT)
1899
/**
1900
* Event occurred
1901
*/
1902
#define FS8X_M_LDO2OC_EVENT_OCCURRED (0x0001U << FS8X_M_LDO2OC_SHIFT)
1903
1904
/**
1905
* No event
1906
*/
1907
#define FS8X_M_LDO1OC_NO_EVENT (0x0000U << FS8X_M_LDO1OC_SHIFT)
1908
/**
1909
* Event occurred
1910
*/
1911
#define FS8X_M_LDO1OC_EVENT_OCCURRED (0x0001U << FS8X_M_LDO1OC_SHIFT)
1912
1913
/**
1914
* No event
1915
*/
1916
#define FS8X_M_BUCK3OC_NO_EVENT (0x0000U << FS8X_M_BUCK3OC_SHIFT)
1917
/**
1918
* Event occurred
1919
*/
1920
#define FS8X_M_BUCK3OC_EVENT_OCCURRED (0x0001U << FS8X_M_BUCK3OC_SHIFT)
1921
1922
/**
1923
* No event
1924
*/
1925
#define FS8X_M_BUCK2OC_NO_EVENT (0x0000U << FS8X_M_BUCK2OC_SHIFT)
1926
/**
1927
* Event occurred
1928
*/
1929
#define FS8X_M_BUCK2OC_EVENT_OCCURRED (0x0001U << FS8X_M_BUCK2OC_SHIFT)
1930
1931
/**
1932
* No event
1933
*/
1934
#define FS8X_M_BUCK1OC_NO_EVENT (0x0000U << FS8X_M_BUCK1OC_SHIFT)
1935
/**
1936
* Event occurred
1937
*/
1938
#define FS8X_M_BUCK1OC_EVENT_OCCURRED (0x0001U << FS8X_M_BUCK1OC_SHIFT)
1939
1940
/**
1941
* No event
1942
*/
1943
#define FS8X_M_VPREOC_NO_EVENT (0x0000U << FS8X_M_VPREOC_SHIFT)
1944
/**
1945
* Event occured
1946
*/
1947
#define FS8X_M_VPREOC_EVENT_OCCURRED (0x0001U << FS8X_M_VPREOC_SHIFT)
1948
1949
/**
1950
* No event
1951
*/
1952
#define FS8X_M_VBOOSTUVH_NO_EVENT (0x0000U << FS8X_M_VBOOSTUVH_SHIFT)
1953
/**
1954
* Event occured
1955
*/
1956
#define FS8X_M_VBOOSTUVH_EVENT_OCCURRED (0x0001U << FS8X_M_VBOOSTUVH_SHIFT)
1957
1958
/**
1959
* No event
1960
*/
1961
#define FS8X_M_VBOSUVH_NO_EVENT (0x0000U << FS8X_M_VBOSUVH_SHIFT)
1962
/**
1963
* Event occured
1964
*/
1965
#define FS8X_M_VBOSUVH_EVENT_OCCURRED (0x0001U << FS8X_M_VBOSUVH_SHIFT)
1966
1967
/******************************************************************************/
1968
/* M_FLAG2 - Type: RW */
1969
/******************************************************************************/
1970
1971
#define FS8X_M_FLAG2_ADDR 0x09U
1972
#define FS8X_M_FLAG2_DEFAULT 0x0000U
1973
1974
/**
1975
* WAKE1 wake up souce flag
1976
*/
1977
#define FS8X_M_WK1FLG_MASK 0x0001U
1978
/**
1979
* WAKE2 wake up souce flag
1980
*/
1981
#define FS8X_M_WK2FLG_MASK 0x0002U
1982
/**
1983
* Report event: WAKE1 real time state
1984
*/
1985
#define FS8X_M_WK1RT_MASK 0x0004U
1986
/**
1987
* Report event: WAKE2 real time state
1988
*/
1989
#define FS8X_M_WK2RT_MASK 0x0008U
1990
/**
1991
* VSUP_UVHH event
1992
*/
1993
#define FS8X_M_VSUPUVH_MASK 0x0010U
1994
/**
1995
* VSUP_UVHL event
1996
*/
1997
#define FS8X_M_VSUPUVL_MASK 0x0020U
1998
/**
1999
* VPRE_UVH event
2000
*/
2001
#define FS8X_M_VPREUVH_MASK 0x0040U
2002
/**
2003
* VPRE_UVL event
2004
*/
2005
#define FS8X_M_VPREUVL_MASK 0x0080U
2006
/**
2007
* LDO2 state
2008
*/
2009
#define FS8X_M_LDO2_ST_MASK 0x0100U
2010
/**
2011
* LDO1 state
2012
*/
2013
#define FS8X_M_LDO1_ST_MASK 0x0200U
2014
/**
2015
* BUCK3 state
2016
*/
2017
#define FS8X_M_BUCK3_ST_MASK 0x0400U
2018
/**
2019
* BUCK2 state
2020
*/
2021
#define FS8X_M_BUCK2_ST_MASK 0x0800U
2022
/**
2023
* BUCK1 state
2024
*/
2025
#define FS8X_M_BUCK1_ST_MASK 0x1000U
2026
/**
2027
* BOOST state
2028
*/
2029
#define FS8X_M_BOOST_ST_MASK 0x2000U
2030
/**
2031
* VSUP_UV7 event
2032
*/
2033
#define FS8X_M_VSUPUV7_MASK 0x4000U
2034
/**
2035
* VPRE_FB_OV event
2036
*/
2037
#define FS8X_M_VPRE_FB_OV_MASK 0x8000U
2038
2039
/**
2040
* WAKE1 wake up souce flag
2041
*/
2042
#define FS8X_M_WK1FLG_SHIFT 0x0000U
2043
/**
2044
* WAKE2 wake up souce flag
2045
*/
2046
#define FS8X_M_WK2FLG_SHIFT 0x0001U
2047
/**
2048
* Report event: WAKE1 real time state
2049
*/
2050
#define FS8X_M_WK1RT_SHIFT 0x0002U
2051
/**
2052
* Report event: WAKE2 real time state
2053
*/
2054
#define FS8X_M_WK2RT_SHIFT 0x0003U
2055
/**
2056
* VSUP_UVHH event
2057
*/
2058
#define FS8X_M_VSUPUVH_SHIFT 0x0004U
2059
/**
2060
* VSUP_UVHL event
2061
*/
2062
#define FS8X_M_VSUPUVL_SHIFT 0x0005U
2063
/**
2064
* VPRE_UVH event
2065
*/
2066
#define FS8X_M_VPREUVH_SHIFT 0x0006U
2067
/**
2068
* VPRE_UVL event
2069
*/
2070
#define FS8X_M_VPREUVL_SHIFT 0x0007U
2071
/**
2072
* LDO2 state
2073
*/
2074
#define FS8X_M_LDO2_ST_SHIFT 0x0008U
2075
/**
2076
* LDO1 state
2077
*/
2078
#define FS8X_M_LDO1_ST_SHIFT 0x0009U
2079
/**
2080
* BUCK3 state
2081
*/
2082
#define FS8X_M_BUCK3_ST_SHIFT 0x000AU
2083
/**
2084
* BUCK2 state
2085
*/
2086
#define FS8X_M_BUCK2_ST_SHIFT 0x000BU
2087
/**
2088
* BUCK1 state
2089
*/
2090
#define FS8X_M_BUCK1_ST_SHIFT 0x000CU
2091
/**
2092
* BOOST state
2093
*/
2094
#define FS8X_M_BOOST_ST_SHIFT 0x000DU
2095
/**
2096
* VSUP_UV7 event
2097
*/
2098
#define FS8X_M_VSUPUV7_SHIFT 0x000EU
2099
/**
2100
* VPRE_FB_OV event
2101
*/
2102
#define FS8X_M_VPRE_FB_OV_SHIFT 0x000FU
2103
2104
/**
2105
* No event
2106
*/
2107
#define FS8X_M_WK1FLG_NO_EVENT (0x0000U << FS8X_M_WK1FLG_SHIFT)
2108
/**
2109
* Event occurred
2110
*/
2111
#define FS8X_M_WK1FLG_EVENT_OCCURRED (0x0001U << FS8X_M_WK1FLG_SHIFT)
2112
2113
/**
2114
* No event
2115
*/
2116
#define FS8X_M_WK2FLG_NO_EVENT (0x0000U << FS8X_M_WK2FLG_SHIFT)
2117
/**
2118
* Event occurred
2119
*/
2120
#define FS8X_M_WK2FLG_EVENT_OCCURRED (0x0001U << FS8X_M_WK2FLG_SHIFT)
2121
2122
/**
2123
* WAKE1 is low level
2124
*/
2125
#define FS8X_M_WK1RT_WAKE1_LOW (0x0000U << FS8X_M_WK1RT_SHIFT)
2126
/**
2127
* WAKE1 is high
2128
*/
2129
#define FS8X_M_WK1RT_WAKE1_HIGH (0x0001U << FS8X_M_WK1RT_SHIFT)
2130
2131
/**
2132
* WAKE2 is low level
2133
*/
2134
#define FS8X_M_WK2RT_WAKE2_LOW (0x0000U << FS8X_M_WK2RT_SHIFT)
2135
/**
2136
* WAKE2 is high
2137
*/
2138
#define FS8X_M_WK2RT_WAKE2_HIGH (0x0001U << FS8X_M_WK2RT_SHIFT)
2139
2140
/**
2141
* No event
2142
*/
2143
#define FS8X_M_VSUPUVH_NO_EVENT (0x0000U << FS8X_M_VSUPUVH_SHIFT)
2144
/**
2145
* Event occurred
2146
*/
2147
#define FS8X_M_VSUPUVH_EVENT_OCCURRED (0x0001U << FS8X_M_VSUPUVH_SHIFT)
2148
2149
/**
2150
* No event
2151
*/
2152
#define FS8X_M_VSUPUVL_NO_EVENT (0x0000U << FS8X_M_VSUPUVL_SHIFT)
2153
/**
2154
* Event occurred
2155
*/
2156
#define FS8X_M_VSUPUVL_EVENT_OCCURRED (0x0001U << FS8X_M_VSUPUVL_SHIFT)
2157
2158
/**
2159
* No event
2160
*/
2161
#define FS8X_M_VPREUVH_NO_EVENT (0x0000U << FS8X_M_VPREUVH_SHIFT)
2162
/**
2163
* Event occurred
2164
*/
2165
#define FS8X_M_VPREUVH_EVENT_OCCURRED (0x0001U << FS8X_M_VPREUVH_SHIFT)
2166
2167
/**
2168
* No event
2169
*/
2170
#define FS8X_M_VPREUVL_NO_EVENT (0x0000U << FS8X_M_VPREUVL_SHIFT)
2171
/**
2172
* Event occurred
2173
*/
2174
#define FS8X_M_VPREUVL_EVENT_OCCURRED (0x0001U << FS8X_M_VPREUVL_SHIFT)
2175
2176
/**
2177
* regulator OFF
2178
*/
2179
#define FS8X_M_LDO2_ST_REGULATOR_OFF (0x0000U << FS8X_M_LDO2_ST_SHIFT)
2180
/**
2181
* regulator ON
2182
*/
2183
#define FS8X_M_LDO2_ST_REGULATOR_ON (0x0001U << FS8X_M_LDO2_ST_SHIFT)
2184
2185
/**
2186
* regulator OFF
2187
*/
2188
#define FS8X_M_LDO1_ST_REGULATOR_OFF (0x0000U << FS8X_M_LDO1_ST_SHIFT)
2189
/**
2190
* regulator ON
2191
*/
2192
#define FS8X_M_LDO1_ST_REGULATOR_ON (0x0001U << FS8X_M_LDO1_ST_SHIFT)
2193
2194
/**
2195
* regulator OFF
2196
*/
2197
#define FS8X_M_BUCK3_ST_REGULATOR_OFF (0x0000U << FS8X_M_BUCK3_ST_SHIFT)
2198
/**
2199
* regulator ON
2200
*/
2201
#define FS8X_M_BUCK3_ST_REGULATOR_ON (0x0001U << FS8X_M_BUCK3_ST_SHIFT)
2202
2203
/**
2204
* regulator OFF
2205
*/
2206
#define FS8X_M_BUCK2_ST_REGULATOR_OFF (0x0000U << FS8X_M_BUCK2_ST_SHIFT)
2207
/**
2208
* regulator ON
2209
*/
2210
#define FS8X_M_BUCK2_ST_REGULATOR_ON (0x0001U << FS8X_M_BUCK2_ST_SHIFT)
2211
2212
/**
2213
* regulator OFF
2214
*/
2215
#define FS8X_M_BUCK1_ST_REGULATOR_OFF (0x0000U << FS8X_M_BUCK1_ST_SHIFT)
2216
/**
2217
* regulator ON
2218
*/
2219
#define FS8X_M_BUCK1_ST_REGULATOR_ON (0x0001U << FS8X_M_BUCK1_ST_SHIFT)
2220
2221
/**
2222
* regulator OFF
2223
*/
2224
#define FS8X_M_BOOST_ST_REGULATOR_OFF (0x0000U << FS8X_M_BOOST_ST_SHIFT)
2225
/**
2226
* regulator ON
2227
*/
2228
#define FS8X_M_BOOST_ST_REGULATOR_ON (0x0001U << FS8X_M_BOOST_ST_SHIFT)
2229
2230
/**
2231
* No event
2232
*/
2233
#define FS8X_M_VSUPUV7_NO_EVENT (0x0000U << FS8X_M_VSUPUV7_SHIFT)
2234
/**
2235
* Event occured
2236
*/
2237
#define FS8X_M_VSUPUV7_EVENT_OCCURRED (0x0001U << FS8X_M_VSUPUV7_SHIFT)
2238
2239
/**
2240
* No event
2241
*/
2242
#define FS8X_M_VPRE_FB_OV_NO_EVENT (0x0000U << FS8X_M_VPRE_FB_OV_SHIFT)
2243
/**
2244
* Event occured
2245
*/
2246
#define FS8X_M_VPRE_FB_OV_EVENT_OCCURRED (0x0001U << FS8X_M_VPRE_FB_OV_SHIFT)
2247
2248
/******************************************************************************/
2249
/* M_VMON_REGX - Type: RW */
2250
/******************************************************************************/
2251
2252
#define FS8X_M_VMON_REGX_ADDR 0x0AU
2253
#define FS8X_M_VMON_REGX_DEFAULT 0x0000U
2254
2255
/**
2256
* Regulator Assignment to VMON1
2257
*/
2258
#define FS8X_M_VMON1_REG_MASK 0x0007U
2259
/**
2260
* Regulator Assignment to VMON2
2261
*/
2262
#define FS8X_M_VMON2_REG_MASK 0x0038U
2263
/**
2264
* Regulator Assignment to VMON3
2265
*/
2266
#define FS8X_M_VMON3_REG_MASK 0x01C0U
2267
/**
2268
* Regulator Assignment to VMON4
2269
*/
2270
#define FS8X_M_VMON4_REG_MASK 0x0E00U
2271
2272
/**
2273
* Regulator Assignment to VMON1
2274
*/
2275
#define FS8X_M_VMON1_REG_SHIFT 0x0000U
2276
/**
2277
* Regulator Assignment to VMON2
2278
*/
2279
#define FS8X_M_VMON2_REG_SHIFT 0x0003U
2280
/**
2281
* Regulator Assignment to VMON3
2282
*/
2283
#define FS8X_M_VMON3_REG_SHIFT 0x0006U
2284
/**
2285
* Regulator Assignment to VMON4
2286
*/
2287
#define FS8X_M_VMON4_REG_SHIFT 0x0009U
2288
2289
/**
2290
* External Regulator
2291
*/
2292
#define FS8X_M_VMON1_REG_EXTERNAL_REGULATOR (0x0000U << FS8X_M_VMON1_REG_SHIFT)
2293
/**
2294
* VPRE
2295
*/
2296
#define FS8X_M_VMON1_REG_VPRE (0x0001U << FS8X_M_VMON1_REG_SHIFT)
2297
/**
2298
* LDO1
2299
*/
2300
#define FS8X_M_VMON1_REG_LDO1 (0x0002U << FS8X_M_VMON1_REG_SHIFT)
2301
/**
2302
* LDO2
2303
*/
2304
#define FS8X_M_VMON1_REG_LDO2 (0x0003U << FS8X_M_VMON1_REG_SHIFT)
2305
/**
2306
* BUCK2
2307
*/
2308
#define FS8X_M_VMON1_REG_BUCK2 (0x0004U << FS8X_M_VMON1_REG_SHIFT)
2309
/**
2310
* BUCK3
2311
*/
2312
#define FS8X_M_VMON1_REG_BUCK3 (0x0005U << FS8X_M_VMON1_REG_SHIFT)
2313
2314
/**
2315
* External Regulator
2316
*/
2317
#define FS8X_M_VMON2_REG_EXTERNAL_REGULATOR (0x0000U << FS8X_M_VMON2_REG_SHIFT)
2318
/**
2319
* VPRE
2320
*/
2321
#define FS8X_M_VMON2_REG_VPRE (0x0001U << FS8X_M_VMON2_REG_SHIFT)
2322
/**
2323
* LDO1
2324
*/
2325
#define FS8X_M_VMON2_REG_LDO1 (0x0002U << FS8X_M_VMON2_REG_SHIFT)
2326
/**
2327
* LDO2
2328
*/
2329
#define FS8X_M_VMON2_REG_LDO2 (0x0003U << FS8X_M_VMON2_REG_SHIFT)
2330
/**
2331
* BUCK2
2332
*/
2333
#define FS8X_M_VMON2_REG_BUCK2 (0x0004U << FS8X_M_VMON2_REG_SHIFT)
2334
/**
2335
* BUCK3
2336
*/
2337
#define FS8X_M_VMON2_REG_BUCK3 (0x0005U << FS8X_M_VMON2_REG_SHIFT)
2338
2339
/**
2340
* External Regulator
2341
*/
2342
#define FS8X_M_VMON3_REG_EXTERNAL_REGULATOR (0x0000U << FS8X_M_VMON3_REG_SHIFT)
2343
/**
2344
* VPRE
2345
*/
2346
#define FS8X_M_VMON3_REG_VPRE (0x0001U << FS8X_M_VMON3_REG_SHIFT)
2347
/**
2348
* LDO1
2349
*/
2350
#define FS8X_M_VMON3_REG_LDO1 (0x0002U << FS8X_M_VMON3_REG_SHIFT)
2351
/**
2352
* LDO2
2353
*/
2354
#define FS8X_M_VMON3_REG_LDO2 (0x0003U << FS8X_M_VMON3_REG_SHIFT)
2355
/**
2356
* BUCK2
2357
*/
2358
#define FS8X_M_VMON3_REG_BUCK2 (0x0004U << FS8X_M_VMON3_REG_SHIFT)
2359
/**
2360
* BUCK3
2361
*/
2362
#define FS8X_M_VMON3_REG_BUCK3 (0x0005U << FS8X_M_VMON3_REG_SHIFT)
2363
2364
/**
2365
* External Regulator
2366
*/
2367
#define FS8X_M_VMON4_REG_EXTERNAL_REGULATOR (0x0000U << FS8X_M_VMON4_REG_SHIFT)
2368
/**
2369
* VPRE
2370
*/
2371
#define FS8X_M_VMON4_REG_VPRE (0x0001U << FS8X_M_VMON4_REG_SHIFT)
2372
/**
2373
* LDO1
2374
*/
2375
#define FS8X_M_VMON4_REG_LDO1 (0x0002U << FS8X_M_VMON4_REG_SHIFT)
2376
/**
2377
* LDO2
2378
*/
2379
#define FS8X_M_VMON4_REG_LDO2 (0x0003U << FS8X_M_VMON4_REG_SHIFT)
2380
/**
2381
* BUCK2
2382
*/
2383
#define FS8X_M_VMON4_REG_BUCK2 (0x0004U << FS8X_M_VMON4_REG_SHIFT)
2384
/**
2385
* BUCK3
2386
*/
2387
#define FS8X_M_VMON4_REG_BUCK3 (0x0005U << FS8X_M_VMON4_REG_SHIFT)
2388
2389
/******************************************************************************/
2390
/* M_LVB1_SVS - Type: R */
2391
/******************************************************************************/
2392
2393
#define FS8X_M_LVB1_SVS_ADDR 0x0BU
2394
#define FS8X_M_LVB1_SVS_DEFAULT 0x0000U
2395
2396
/**
2397
* Static Voltage Scaling negative offset
2398
*/
2399
#define FS8X_M_LVB1_SVS_MASK 0x001FU
2400
2401
/**
2402
* Static Voltage Scaling negative offset
2403
*/
2404
#define FS8X_M_LVB1_SVS_SHIFT 0x0000U
2405
2406
/**
2407
* 0mV
2408
*/
2409
#define FS8X_M_LVB1_SVS_0MV (0x0000U << FS8X_M_LVB1_SVS_SHIFT)
2410
/**
2411
* -6.25mV
2412
*/
2413
#define FS8X_M_LVB1_SVS_M6_25MV (0x0001U << FS8X_M_LVB1_SVS_SHIFT)
2414
/**
2415
* -12.50mV
2416
*/
2417
#define FS8X_M_LVB1_SVS_M12_50MV (0x0002U << FS8X_M_LVB1_SVS_SHIFT)
2418
/**
2419
* -18.75mV
2420
*/
2421
#define FS8X_M_LVB1_SVS_M18_75MV (0x0003U << FS8X_M_LVB1_SVS_SHIFT)
2422
/**
2423
* -25mV
2424
*/
2425
#define FS8X_M_LVB1_SVS_M25MV (0x0004U << FS8X_M_LVB1_SVS_SHIFT)
2426
/**
2427
* -31.25mV
2428
*/
2429
#define FS8X_M_LVB1_SVS_M31_25MV (0x0005U << FS8X_M_LVB1_SVS_SHIFT)
2430
/**
2431
* -37.5mV
2432
*/
2433
#define FS8X_M_LVB1_SVS_M37_5MV (0x0006U << FS8X_M_LVB1_SVS_SHIFT)
2434
/**
2435
* -43.75mV
2436
*/
2437
#define FS8X_M_LVB1_SVS_M43_75MV (0x0007U << FS8X_M_LVB1_SVS_SHIFT)
2438
/**
2439
* -50mV
2440
*/
2441
#define FS8X_M_LVB1_SVS_M50MV (0x0008U << FS8X_M_LVB1_SVS_SHIFT)
2442
/**
2443
* -56.25mV
2444
*/
2445
#define FS8X_M_LVB1_SVS_M56_25MV (0x0009U << FS8X_M_LVB1_SVS_SHIFT)
2446
/**
2447
* -62.5mV
2448
*/
2449
#define FS8X_M_LVB1_SVS_M62_5MV (0x000AU << FS8X_M_LVB1_SVS_SHIFT)
2450
/**
2451
* -68.75mV
2452
*/
2453
#define FS8X_M_LVB1_SVS_M68_75MV (0x000BU << FS8X_M_LVB1_SVS_SHIFT)
2454
/**
2455
* -75mV
2456
*/
2457
#define FS8X_M_LVB1_SVS_M75MV (0x000CU << FS8X_M_LVB1_SVS_SHIFT)
2458
/**
2459
* -81.25mV
2460
*/
2461
#define FS8X_M_LVB1_SVS_M81_25MV (0x000DU << FS8X_M_LVB1_SVS_SHIFT)
2462
/**
2463
* -87.5mV
2464
*/
2465
#define FS8X_M_LVB1_SVS_M87_5MV (0x000EU << FS8X_M_LVB1_SVS_SHIFT)
2466
/**
2467
* -93.75mV
2468
*/
2469
#define FS8X_M_LVB1_SVS_M93_75MV (0x000FU << FS8X_M_LVB1_SVS_SHIFT)
2470
/**
2471
* -100mV
2472
*/
2473
#define FS8X_M_LVB1_SVS_M100MV (0x0010U << FS8X_M_LVB1_SVS_SHIFT)
2474
2475
/******************************************************************************/
2476
/* M_MEMORY0 - Type: RW */
2477
/******************************************************************************/
2478
2479
#define FS8X_M_MEMORY0_ADDR 0x23U
2480
#define FS8X_M_MEMORY0_DEFAULT 0x0000U
2481
2482
/**
2483
* Free field for data storage
2484
*/
2485
#define FS8X_M_M_MEMORY0_MASK 0xFFFFU
2486
2487
/**
2488
* Free field for data storage
2489
*/
2490
#define FS8X_M_M_MEMORY0_SHIFT 0x0000U
2491
2492
/******************************************************************************/
2493
/* M_MEMORY1 - Type: RW */
2494
/******************************************************************************/
2495
2496
#define FS8X_M_MEMORY1_ADDR 0x24U
2497
#define FS8X_M_MEMORY1_DEFAULT 0x0000U
2498
2499
/**
2500
* Free field for data storage
2501
*/
2502
#define FS8X_M_M_MEMORY1_MASK 0xFFFFU
2503
2504
/**
2505
* Free field for data storage
2506
*/
2507
#define FS8X_M_M_MEMORY1_SHIFT 0x0000U
2508
2509
/******************************************************************************/
2510
/* M_DEVICEID - Type: R */
2511
/******************************************************************************/
2512
2513
#define FS8X_M_DEVICEID_ADDR 0x25U
2514
#define FS8X_M_DEVICEID_DEFAULT 0x0000U
2515
2516
/**
2517
* Device ID
2518
*/
2519
#define FS8X_M_M_DEVICE_MASK 0x00FFU
2520
2521
/**
2522
* Device ID
2523
*/
2524
#define FS8X_M_M_DEVICE_SHIFT 0x0000U
2525
2526
/******************************************************************************/
2527
/* FS_I_OVUV_SAFE_REACTION1 - Type: RW */
2528
/******************************************************************************/
2529
2530
#define FS8X_FS_I_OVUV_SAFE_REACTION1_ADDR 0x01U
2531
#define FS8X_FS_I_OVUV_SAFE_REACTION1_DEFAULT 0xD00DU
2532
2533
/**
2534
* VDDIO UV impact on RSTB/FS0B
2535
*/
2536
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_MASK 0x0003U
2537
/**
2538
* VDDIO OV impact on RSTB/FS0B
2539
*/
2540
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_MASK 0x000CU
2541
/**
2542
* VMON4 ABIST2 configuration
2543
*/
2544
#define FS8X_FS_I_VMON4_ABIST2_MASK 0x0020U
2545
/**
2546
* VMON3 ABIST2 configuration
2547
*/
2548
#define FS8X_FS_I_VMON3_ABIST2_MASK 0x0040U
2549
/**
2550
* VMON2 ABIST2 configuration
2551
*/
2552
#define FS8X_FS_I_VMON2_ABIST2_MASK 0x0080U
2553
/**
2554
* VMON1 ABIST2 configuration
2555
*/
2556
#define FS8X_FS_I_VMON1_ABIST2_MASK 0x0100U
2557
/**
2558
* VDDIO ABIST2 configuration
2559
*/
2560
#define FS8X_FS_I_VDDIO_ABIST2_MASK 0x0200U
2561
/**
2562
* VCOREMON ABIST2 configuration
2563
*/
2564
#define FS8X_FS_I_VCOREMON_ABIST2_MASK 0x0400U
2565
/**
2566
* VCOREMON UV impact on RSTB/FS0B
2567
*/
2568
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_MASK 0x3000U
2569
/**
2570
* VCOREMON OV impact on RSTB/FS0B
2571
*/
2572
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_MASK 0xC000U
2573
2574
/**
2575
* VDDIO UV impact on RSTB/FS0B
2576
*/
2577
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_SHIFT 0x0000U
2578
/**
2579
* VDDIO OV impact on RSTB/FS0B
2580
*/
2581
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_SHIFT 0x0002U
2582
/**
2583
* VMON4 ABIST2 configuration
2584
*/
2585
#define FS8X_FS_I_VMON4_ABIST2_SHIFT 0x0005U
2586
/**
2587
* VMON3 ABIST2 configuration
2588
*/
2589
#define FS8X_FS_I_VMON3_ABIST2_SHIFT 0x0006U
2590
/**
2591
* VMON2 ABIST2 configuration
2592
*/
2593
#define FS8X_FS_I_VMON2_ABIST2_SHIFT 0x0007U
2594
/**
2595
* VMON1 ABIST2 configuration
2596
*/
2597
#define FS8X_FS_I_VMON1_ABIST2_SHIFT 0x0008U
2598
/**
2599
* VDDIO ABIST2 configuration
2600
*/
2601
#define FS8X_FS_I_VDDIO_ABIST2_SHIFT 0x0009U
2602
/**
2603
* VCOREMON ABIST2 configuration
2604
*/
2605
#define FS8X_FS_I_VCOREMON_ABIST2_SHIFT 0x000AU
2606
/**
2607
* VCOREMON UV impact on RSTB/FS0B
2608
*/
2609
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_SHIFT 0x000CU
2610
/**
2611
* VCOREMON OV impact on RSTB/FS0B
2612
*/
2613
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_SHIFT 0x000EU
2614
2615
/**
2616
* No effect on RSTB and FS0B
2617
*/
2618
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VDDIO_UV_FS_IMPACT_SHIFT)
2619
/**
2620
* FS0B only is asserted
2621
*/
2622
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VDDIO_UV_FS_IMPACT_SHIFT)
2623
/**
2624
* FS0B and RSTB are asserted
2625
*/
2626
#define FS8X_FS_I_VDDIO_UV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VDDIO_UV_FS_IMPACT_SHIFT)
2627
2628
/**
2629
* No effect on RSTB and FS0B
2630
*/
2631
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VDDIO_OV_FS_IMPACT_SHIFT)
2632
/**
2633
* FS0B only is asserted
2634
*/
2635
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VDDIO_OV_FS_IMPACT_SHIFT)
2636
/**
2637
* FS0B and RSTB are asserted
2638
*/
2639
#define FS8X_FS_I_VDDIO_OV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VDDIO_OV_FS_IMPACT_SHIFT)
2640
2641
/**
2642
* No ABIST
2643
*/
2644
#define FS8X_FS_I_VMON4_ABIST2_NO_ABIST (0x0000U << FS8X_FS_I_VMON4_ABIST2_SHIFT)
2645
/**
2646
* VMON4 BIST executed during ABIST2
2647
*/
2648
#define FS8X_FS_I_VMON4_ABIST2_VMON4_BIST (0x0001U << FS8X_FS_I_VMON4_ABIST2_SHIFT)
2649
2650
/**
2651
* No ABIST
2652
*/
2653
#define FS8X_FS_I_VMON3_ABIST2_NO_ABIST (0x0000U << FS8X_FS_I_VMON3_ABIST2_SHIFT)
2654
/**
2655
* VMON3 BIST executed during ABIST2
2656
*/
2657
#define FS8X_FS_I_VMON3_ABIST2_VMON3_BIST (0x0001U << FS8X_FS_I_VMON3_ABIST2_SHIFT)
2658
2659
/**
2660
* No ABIST
2661
*/
2662
#define FS8X_FS_I_VMON2_ABIST2_NO_ABIST (0x0000U << FS8X_FS_I_VMON2_ABIST2_SHIFT)
2663
/**
2664
* VMON2 BIST executed during ABIST2
2665
*/
2666
#define FS8X_FS_I_VMON2_ABIST2_VMON2_BIST (0x0001U << FS8X_FS_I_VMON2_ABIST2_SHIFT)
2667
2668
/**
2669
* No ABIST
2670
*/
2671
#define FS8X_FS_I_VMON1_ABIST2_NO_ABIST (0x0000U << FS8X_FS_I_VMON1_ABIST2_SHIFT)
2672
/**
2673
* VMON1 BIST executed during ABIST2
2674
*/
2675
#define FS8X_FS_I_VMON1_ABIST2_VMON1_BIST (0x0001U << FS8X_FS_I_VMON1_ABIST2_SHIFT)
2676
2677
/**
2678
* No ABIST
2679
*/
2680
#define FS8X_FS_I_VDDIO_ABIST2_NO_ABIST (0x0000U << FS8X_FS_I_VDDIO_ABIST2_SHIFT)
2681
/**
2682
* VDDIO BIST executed during ABIST2
2683
*/
2684
#define FS8X_FS_I_VDDIO_ABIST2_VDDIO_BIST (0x0001U << FS8X_FS_I_VDDIO_ABIST2_SHIFT)
2685
2686
/**
2687
* No ABIST
2688
*/
2689
#define FS8X_FS_I_VCOREMON_ABIST2_NO_ABIST (0x0000U << FS8X_FS_I_VCOREMON_ABIST2_SHIFT)
2690
/**
2691
* VCOREMON BIST executed during ABIST2
2692
*/
2693
#define FS8X_FS_I_VCOREMON_ABIST2_VCOREMON_BIST (0x0001U << FS8X_FS_I_VCOREMON_ABIST2_SHIFT)
2694
2695
/**
2696
* No effect on RSTB and FS0B
2697
*/
2698
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VCOREMON_UV_FS_IMPACT_SHIFT)
2699
/**
2700
* FS0B only is asserted
2701
*/
2702
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VCOREMON_UV_FS_IMPACT_SHIFT)
2703
/**
2704
* FS0B and RSTB are asserted
2705
*/
2706
#define FS8X_FS_I_VCOREMON_UV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VCOREMON_UV_FS_IMPACT_SHIFT)
2707
2708
/**
2709
* No effect on RSTB and FS0B
2710
*/
2711
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VCOREMON_OV_FS_IMPACT_SHIFT)
2712
/**
2713
* FS0B only is asserted
2714
*/
2715
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VCOREMON_OV_FS_IMPACT_SHIFT)
2716
/**
2717
* FS0B and RSTB are asserted
2718
*/
2719
#define FS8X_FS_I_VCOREMON_OV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VCOREMON_OV_FS_IMPACT_SHIFT)
2720
2721
/******************************************************************************/
2722
/* FS_I_OVUV_SAFE_REACTION2 - Type: RW */
2723
/******************************************************************************/
2724
2725
#define FS8X_FS_I_OVUV_SAFE_REACTION2_ADDR 0x03U
2726
#define FS8X_FS_I_OVUV_SAFE_REACTION2_DEFAULT 0xDDDDU
2727
2728
/**
2729
* VMON1 UV impact on RSTB/FS0B
2730
*/
2731
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_MASK 0x0003U
2732
/**
2733
* VMON1 OV impact on RSTB/FS0B
2734
*/
2735
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_MASK 0x000CU
2736
/**
2737
* VMON2 UV impact on RSTB/FS0B
2738
*/
2739
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_MASK 0x0030U
2740
/**
2741
* VMON2 OV impact on RSTB/FS0B
2742
*/
2743
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_MASK 0x00C0U
2744
/**
2745
* VMON3 UV impact on RSTB/FS0B
2746
*/
2747
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_MASK 0x0300U
2748
/**
2749
* VMON3 OV impact on RSTB/FS0B
2750
*/
2751
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_MASK 0x0C00U
2752
/**
2753
* VMON4 UV impact on RSTB/FS0B
2754
*/
2755
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_MASK 0x3000U
2756
/**
2757
* VMON4 OV impact on RSTB/FS0B
2758
*/
2759
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_MASK 0xC000U
2760
2761
/**
2762
* VMON1 UV impact on RSTB/FS0B
2763
*/
2764
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_SHIFT 0x0000U
2765
/**
2766
* VMON1 OV impact on RSTB/FS0B
2767
*/
2768
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_SHIFT 0x0002U
2769
/**
2770
* VMON2 UV impact on RSTB/FS0B
2771
*/
2772
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_SHIFT 0x0004U
2773
/**
2774
* VMON2 OV impact on RSTB/FS0B
2775
*/
2776
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_SHIFT 0x0006U
2777
/**
2778
* VMON3 UV impact on RSTB/FS0B
2779
*/
2780
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_SHIFT 0x0008U
2781
/**
2782
* VMON3 OV impact on RSTB/FS0B
2783
*/
2784
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_SHIFT 0x000AU
2785
/**
2786
* VMON4 UV impact on RSTB/FS0B
2787
*/
2788
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_SHIFT 0x000CU
2789
/**
2790
* VMON4 OV impact on RSTB/FS0B
2791
*/
2792
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_SHIFT 0x000EU
2793
2794
/**
2795
* No effect on RSTB and FS0B
2796
*/
2797
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON1_UV_FS_IMPACT_SHIFT)
2798
/**
2799
* FS0B only is asserted
2800
*/
2801
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON1_UV_FS_IMPACT_SHIFT)
2802
/**
2803
* FS0B and RSTB are asserted
2804
*/
2805
#define FS8X_FS_I_VMON1_UV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON1_UV_FS_IMPACT_SHIFT)
2806
2807
/**
2808
* No effect on RSTB and FS0B
2809
*/
2810
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON1_OV_FS_IMPACT_SHIFT)
2811
/**
2812
* FS0B only is asserted
2813
*/
2814
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON1_OV_FS_IMPACT_SHIFT)
2815
/**
2816
* FS0B and RSTB are asserted
2817
*/
2818
#define FS8X_FS_I_VMON1_OV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON1_OV_FS_IMPACT_SHIFT)
2819
2820
/**
2821
* No effect on RSTB and FS0B
2822
*/
2823
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON2_UV_FS_IMPACT_SHIFT)
2824
/**
2825
* FS0B only is asserted
2826
*/
2827
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON2_UV_FS_IMPACT_SHIFT)
2828
/**
2829
* FS0B and RSTB are asserted
2830
*/
2831
#define FS8X_FS_I_VMON2_UV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON2_UV_FS_IMPACT_SHIFT)
2832
2833
/**
2834
* No effect on RSTB and FS0B
2835
*/
2836
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON2_OV_FS_IMPACT_SHIFT)
2837
/**
2838
* FS0B only is asserted
2839
*/
2840
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON2_OV_FS_IMPACT_SHIFT)
2841
/**
2842
* FS0B and RSTB are asserted
2843
*/
2844
#define FS8X_FS_I_VMON2_OV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON2_OV_FS_IMPACT_SHIFT)
2845
2846
/**
2847
* No effect on RSTB and FS0B
2848
*/
2849
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON3_UV_FS_IMPACT_SHIFT)
2850
/**
2851
* FS0B only is asserted
2852
*/
2853
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON3_UV_FS_IMPACT_SHIFT)
2854
/**
2855
* FS0B and RSTB are asserted
2856
*/
2857
#define FS8X_FS_I_VMON3_UV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON3_UV_FS_IMPACT_SHIFT)
2858
2859
/**
2860
* No effect on RSTB and FS0B
2861
*/
2862
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON3_OV_FS_IMPACT_SHIFT)
2863
/**
2864
* FS0B only is asserted
2865
*/
2866
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON3_OV_FS_IMPACT_SHIFT)
2867
/**
2868
* FS0B and RSTB are asserted
2869
*/
2870
#define FS8X_FS_I_VMON3_OV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON3_OV_FS_IMPACT_SHIFT)
2871
2872
/**
2873
* No effect on RSTB and FS0B
2874
*/
2875
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON4_UV_FS_IMPACT_SHIFT)
2876
/**
2877
* FS0B only is asserted
2878
*/
2879
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON4_UV_FS_IMPACT_SHIFT)
2880
/**
2881
* FS0B and RSTB are asserted
2882
*/
2883
#define FS8X_FS_I_VMON4_UV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON4_UV_FS_IMPACT_SHIFT)
2884
2885
/**
2886
* No effect on RSTB and FS0B
2887
*/
2888
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_VMON4_OV_FS_IMPACT_SHIFT)
2889
/**
2890
* FS0B only is asserted
2891
*/
2892
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_VMON4_OV_FS_IMPACT_SHIFT)
2893
/**
2894
* FS0B and RSTB are asserted
2895
*/
2896
#define FS8X_FS_I_VMON4_OV_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_VMON4_OV_FS_IMPACT_SHIFT)
2897
2898
/******************************************************************************/
2899
/* FS_I_WD_CFG - Type: RW */
2900
/******************************************************************************/
2901
2902
#define FS8X_FS_I_WD_CFG_ADDR 0x05U
2903
#define FS8X_FS_I_WD_CFG_DEFAULT 0x4200U
2904
2905
/**
2906
* Reflect the value of the Watchdog Error Counter.
2907
*/
2908
#define FS8X_FS_I_WD_ERR_CNT_MASK 0x000FU
2909
/**
2910
* Reflect the value of the Watchdog Refresh Counter
2911
*/
2912
#define FS8X_FS_I_WD_RFR_CNT_MASK 0x0070U
2913
/**
2914
* Watchdog Error Impact on RSTB/FS0B
2915
*/
2916
#define FS8X_FS_I_WD_FS_IMPACT_MASK 0x0300U
2917
/**
2918
* Watchdog Refresh Counter value
2919
*/
2920
#define FS8X_FS_I_WD_RFR_LIMIT_MASK 0x1800U
2921
/**
2922
* Watchdog Error Counter value
2923
*/
2924
#define FS8X_FS_I_WD_ERR_LIMIT_MASK 0xC000U
2925
2926
/**
2927
* Reflect the value of the Watchdog Error Counter.
2928
*/
2929
#define FS8X_FS_I_WD_ERR_CNT_SHIFT 0x0000U
2930
/**
2931
* Reflect the value of the Watchdog Refresh Counter
2932
*/
2933
#define FS8X_FS_I_WD_RFR_CNT_SHIFT 0x0004U
2934
/**
2935
* Watchdog Error Impact on RSTB/FS0B
2936
*/
2937
#define FS8X_FS_I_WD_FS_IMPACT_SHIFT 0x0008U
2938
/**
2939
* Watchdog Refresh Counter value
2940
*/
2941
#define FS8X_FS_I_WD_RFR_LIMIT_SHIFT 0x000BU
2942
/**
2943
* Watchdog Error Counter value
2944
*/
2945
#define FS8X_FS_I_WD_ERR_LIMIT_SHIFT 0x000EU
2946
2947
/**
2948
* 0
2949
*/
2950
#define FS8X_FS_I_WD_ERR_CNT_0 (0x0000U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2951
/**
2952
* 1
2953
*/
2954
#define FS8X_FS_I_WD_ERR_CNT_1 (0x0001U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2955
/**
2956
* 2
2957
*/
2958
#define FS8X_FS_I_WD_ERR_CNT_2 (0x0002U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2959
/**
2960
* 3
2961
*/
2962
#define FS8X_FS_I_WD_ERR_CNT_3 (0x0003U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2963
/**
2964
* 4
2965
*/
2966
#define FS8X_FS_I_WD_ERR_CNT_4 (0x0004U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2967
/**
2968
* 5
2969
*/
2970
#define FS8X_FS_I_WD_ERR_CNT_5 (0x0005U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2971
/**
2972
* 6
2973
*/
2974
#define FS8X_FS_I_WD_ERR_CNT_6 (0x0006U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2975
/**
2976
* 7
2977
*/
2978
#define FS8X_FS_I_WD_ERR_CNT_7 (0x0007U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2979
/**
2980
* 8
2981
*/
2982
#define FS8X_FS_I_WD_ERR_CNT_8 (0x0008U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2983
/**
2984
* 9
2985
*/
2986
#define FS8X_FS_I_WD_ERR_CNT_9 (0x0009U << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2987
/**
2988
* 10
2989
*/
2990
#define FS8X_FS_I_WD_ERR_CNT_10 (0x000AU << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2991
/**
2992
* 11
2993
*/
2994
#define FS8X_FS_I_WD_ERR_CNT_11 (0x000BU << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2995
/**
2996
* 12
2997
*/
2998
#define FS8X_FS_I_WD_ERR_CNT_12 (0x000CU << FS8X_FS_I_WD_ERR_CNT_SHIFT)
2999
3000
/**
3001
* 0
3002
*/
3003
#define FS8X_FS_I_WD_RFR_CNT_0 (0x0000U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3004
/**
3005
* 1
3006
*/
3007
#define FS8X_FS_I_WD_RFR_CNT_1 (0x0001U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3008
/**
3009
* 2
3010
*/
3011
#define FS8X_FS_I_WD_RFR_CNT_2 (0x0002U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3012
/**
3013
* 3
3014
*/
3015
#define FS8X_FS_I_WD_RFR_CNT_3 (0x0003U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3016
/**
3017
* 4
3018
*/
3019
#define FS8X_FS_I_WD_RFR_CNT_4 (0x0004U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3020
/**
3021
* 5
3022
*/
3023
#define FS8X_FS_I_WD_RFR_CNT_5 (0x0005U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3024
/**
3025
* 6
3026
*/
3027
#define FS8X_FS_I_WD_RFR_CNT_6 (0x0006U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3028
/**
3029
* 7
3030
*/
3031
#define FS8X_FS_I_WD_RFR_CNT_7 (0x0007U << FS8X_FS_I_WD_RFR_CNT_SHIFT)
3032
3033
/**
3034
* No action on RSTB and FS0B
3035
*/
3036
#define FS8X_FS_I_WD_FS_IMPACT_NO_ACTION (0x0000U << FS8X_FS_I_WD_FS_IMPACT_SHIFT)
3037
/**
3038
* FS0B only is asserted if WD error counter = WD_ERR_LIMIT[1:0]
3039
*/
3040
#define FS8X_FS_I_WD_FS_IMPACT_FS0B (0x0001U << FS8X_FS_I_WD_FS_IMPACT_SHIFT)
3041
/**
3042
* FS0B and RSTB are asserted if WD error counter = WD_ERR_LIMIT[1:0]
3043
*/
3044
#define FS8X_FS_I_WD_FS_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_WD_FS_IMPACT_SHIFT)
3045
3046
/**
3047
* 6
3048
*/
3049
#define FS8X_FS_I_WD_RFR_LIMIT_6 (0x0000U << FS8X_FS_I_WD_RFR_LIMIT_SHIFT)
3050
/**
3051
* 4
3052
*/
3053
#define FS8X_FS_I_WD_RFR_LIMIT_4 (0x0001U << FS8X_FS_I_WD_RFR_LIMIT_SHIFT)
3054
/**
3055
* 2
3056
*/
3057
#define FS8X_FS_I_WD_RFR_LIMIT_2 (0x0002U << FS8X_FS_I_WD_RFR_LIMIT_SHIFT)
3058
/**
3059
* 1
3060
*/
3061
#define FS8X_FS_I_WD_RFR_LIMIT_1 (0x0003U << FS8X_FS_I_WD_RFR_LIMIT_SHIFT)
3062
3063
/**
3064
* 8
3065
*/
3066
#define FS8X_FS_I_WD_ERR_LIMIT_8 (0x0000U << FS8X_FS_I_WD_ERR_LIMIT_SHIFT)
3067
/**
3068
* 6
3069
*/
3070
#define FS8X_FS_I_WD_ERR_LIMIT_6 (0x0001U << FS8X_FS_I_WD_ERR_LIMIT_SHIFT)
3071
/**
3072
* 4
3073
*/
3074
#define FS8X_FS_I_WD_ERR_LIMIT_4 (0x0002U << FS8X_FS_I_WD_ERR_LIMIT_SHIFT)
3075
/**
3076
* 2
3077
*/
3078
#define FS8X_FS_I_WD_ERR_LIMIT_2 (0x0003U << FS8X_FS_I_WD_ERR_LIMIT_SHIFT)
3079
3080
/******************************************************************************/
3081
/* FS_I_SAFE_INPUTS - Type: RW */
3082
/******************************************************************************/
3083
3084
#define FS8X_FS_I_SAFE_INPUTS_ADDR 0x07U
3085
#define FS8X_FS_I_SAFE_INPUTS_DEFAULT 0x41C6U
3086
3087
/**
3088
* ERRMON impact on RSTB/FS0B
3089
*/
3090
#define FS8X_FS_I_ERRMON_FS_IMPACT_MASK 0x0002U
3091
/**
3092
* ERRMON acknowledgement timing
3093
*/
3094
#define FS8X_FS_I_ERRMON_ACK_TIME_MASK 0x000CU
3095
/**
3096
* ERRMON polarity
3097
*/
3098
#define FS8X_FS_I_ERRMON_FLT_POLARITY_MASK 0x0010U
3099
/**
3100
* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU2
3101
*/
3102
#define FS8X_FS_I_FCCU2_FS_REACT_MASK 0x0040U
3103
/**
3104
* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU1
3105
*/
3106
#define FS8X_FS_I_FCCU1_FS_REACT_MASK 0x0080U
3107
/**
3108
* FCCU12 impact on RSTB/FS0B
3109
*/
3110
#define FS8X_FS_I_FCCU12_FS_IMPACT_MASK 0x0100U
3111
/**
3112
* FCCU2 polarity
3113
*/
3114
#define FS8X_FS_I_FCCU2_FLT_POL_MASK 0x0400U
3115
/**
3116
* FCCU1 polarity
3117
*/
3118
#define FS8X_FS_I_FCCU1_FLT_POL_MASK 0x0800U
3119
/**
3120
* FCCU12 polarity
3121
*/
3122
#define FS8X_FS_I_FCCU12_FLT_POL_MASK 0x1000U
3123
/**
3124
* FCCU pins configuration
3125
*/
3126
#define FS8X_FS_I_FCCU_CFG_MASK 0xC000U
3127
3128
/**
3129
* ERRMON impact on RSTB/FS0B
3130
*/
3131
#define FS8X_FS_I_ERRMON_FS_IMPACT_SHIFT 0x0001U
3132
/**
3133
* ERRMON acknowledgement timing
3134
*/
3135
#define FS8X_FS_I_ERRMON_ACK_TIME_SHIFT 0x0002U
3136
/**
3137
* ERRMON polarity
3138
*/
3139
#define FS8X_FS_I_ERRMON_FLT_POLARITY_SHIFT 0x0004U
3140
/**
3141
* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU2
3142
*/
3143
#define FS8X_FS_I_FCCU2_FS_REACT_SHIFT 0x0006U
3144
/**
3145
* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU1
3146
*/
3147
#define FS8X_FS_I_FCCU1_FS_REACT_SHIFT 0x0007U
3148
/**
3149
* FCCU12 impact on RSTB/FS0B
3150
*/
3151
#define FS8X_FS_I_FCCU12_FS_IMPACT_SHIFT 0x0008U
3152
/**
3153
* FCCU2 polarity
3154
*/
3155
#define FS8X_FS_I_FCCU2_FLT_POL_SHIFT 0x000AU
3156
/**
3157
* FCCU1 polarity
3158
*/
3159
#define FS8X_FS_I_FCCU1_FLT_POL_SHIFT 0x000BU
3160
/**
3161
* FCCU12 polarity
3162
*/
3163
#define FS8X_FS_I_FCCU12_FLT_POL_SHIFT 0x000CU
3164
/**
3165
* FCCU pins configuration
3166
*/
3167
#define FS8X_FS_I_FCCU_CFG_SHIFT 0x000EU
3168
3169
/**
3170
* FS0B only is asserted when ERRMON fault is detected
3171
*/
3172
#define FS8X_FS_I_ERRMON_FS_IMPACT_FS0B (0x0000U << FS8X_FS_I_ERRMON_FS_IMPACT_SHIFT)
3173
/**
3174
* FS0B and RSTB are asserted when ERRMON fault is detected
3175
*/
3176
#define FS8X_FS_I_ERRMON_FS_IMPACT_FS0B_RSTB (0x0001U << FS8X_FS_I_ERRMON_FS_IMPACT_SHIFT)
3177
3178
/**
3179
* 1ms
3180
*/
3181
#define FS8X_FS_I_ERRMON_ACK_TIME_1MS (0x0000U << FS8X_FS_I_ERRMON_ACK_TIME_SHIFT)
3182
/**
3183
* 8ms
3184
*/
3185
#define FS8X_FS_I_ERRMON_ACK_TIME_8MS (0x0001U << FS8X_FS_I_ERRMON_ACK_TIME_SHIFT)
3186
/**
3187
* 16ms
3188
*/
3189
#define FS8X_FS_I_ERRMON_ACK_TIME_16MS (0x0002U << FS8X_FS_I_ERRMON_ACK_TIME_SHIFT)
3190
/**
3191
* 32ms
3192
*/
3193
#define FS8X_FS_I_ERRMON_ACK_TIME_32MS (0x0003U << FS8X_FS_I_ERRMON_ACK_TIME_SHIFT)
3194
3195
/**
3196
* LOW LEVEL IS A FAULT after a negative edge transition
3197
*/
3198
#define FS8X_FS_I_ERRMON_FLT_POLARITY_NEGATIVE_EDGE (0x0000U << FS8X_FS_I_ERRMON_FLT_POLARITY_SHIFT)
3199
/**
3200
* HIGH LEVEL IS A FAULT after a positive edge transition
3201
*/
3202
#define FS8X_FS_I_ERRMON_FLT_POLARITY_POSITIVE_EDGE (0x0001U << FS8X_FS_I_ERRMON_FLT_POLARITY_SHIFT)
3203
3204
/**
3205
* FS0B only is asserted
3206
*/
3207
#define FS8X_FS_I_FCCU2_FS_REACT_FS0B (0x0000U << FS8X_FS_I_FCCU2_FS_REACT_SHIFT)
3208
/**
3209
* FS0B and RSTB are asserted
3210
*/
3211
#define FS8X_FS_I_FCCU2_FS_REACT_FS0B_RSTB (0x0001U << FS8X_FS_I_FCCU2_FS_REACT_SHIFT)
3212
3213
/**
3214
* FS0B only is asserted
3215
*/
3216
#define FS8X_FS_I_FCCU1_FS_REACT_FS0B (0x0000U << FS8X_FS_I_FCCU1_FS_REACT_SHIFT)
3217
/**
3218
* FS0B and RSTB are asserted
3219
*/
3220
#define FS8X_FS_I_FCCU1_FS_REACT_FS0B_RSTB (0x0001U << FS8X_FS_I_FCCU1_FS_REACT_SHIFT)
3221
3222
/**
3223
* FS0B only is asserted
3224
*/
3225
#define FS8X_FS_I_FCCU12_FS_IMPACT_FS0B (0x0000U << FS8X_FS_I_FCCU12_FS_IMPACT_SHIFT)
3226
/**
3227
* FS0B and RSTB are asserted
3228
*/
3229
#define FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB (0x0001U << FS8X_FS_I_FCCU12_FS_IMPACT_SHIFT)
3230
3231
/**
3232
* FCCU2 low level is a fault
3233
*/
3234
#define FS8X_FS_I_FCCU2_FLT_POL_FCCU2_L (0x0000U << FS8X_FS_I_FCCU2_FLT_POL_SHIFT)
3235
/**
3236
* FCCU2 hign level is a fault
3237
*/
3238
#define FS8X_FS_I_FCCU2_FLT_POL_FCCU2_H (0x0001U << FS8X_FS_I_FCCU2_FLT_POL_SHIFT)
3239
3240
/**
3241
* FCCU1 low level is a fault
3242
*/
3243
#define FS8X_FS_I_FCCU1_FLT_POL_FCCU1_L (0x0000U << FS8X_FS_I_FCCU1_FLT_POL_SHIFT)
3244
/**
3245
* FCCU1 high level is a fault
3246
*/
3247
#define FS8X_FS_I_FCCU1_FLT_POL_FCCU1_H (0x0001U << FS8X_FS_I_FCCU1_FLT_POL_SHIFT)
3248
3249
/**
3250
* FCCU1=0 or FCCU2=1 level is a fault
3251
*/
3252
#define FS8X_FS_I_FCCU12_FLT_POL_FCCU1_L_FCCU2_H (0x0000U << FS8X_FS_I_FCCU12_FLT_POL_SHIFT)
3253
/**
3254
* FCCU1=1 or FCCU2=0 level is a fault
3255
*/
3256
#define FS8X_FS_I_FCCU12_FLT_POL_FCCU1_H_FCCU2_L (0x0001U << FS8X_FS_I_FCCU12_FLT_POL_SHIFT)
3257
3258
/**
3259
* No monitoring
3260
*/
3261
#define FS8X_FS_I_FCCU_CFG_NO_MONITORING (0x0000U << FS8X_FS_I_FCCU_CFG_SHIFT)
3262
/**
3263
* FCCU1 and FCCU2 monitoring by pair (bi-stable protocol)
3264
*/
3265
#define FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_PAIR (0x0001U << FS8X_FS_I_FCCU_CFG_SHIFT)
3266
/**
3267
* FCCU1 or FCCU2 input monitoring
3268
*/
3269
#define FS8X_FS_I_FCCU_CFG_FCCU1_FCCU2_INPUT (0x0002U << FS8X_FS_I_FCCU_CFG_SHIFT)
3270
/**
3271
* FCCU1 input monitoring only
3272
*/
3273
#define FS8X_FS_I_FCCU_CFG_FCCU1_INPUT (0x0003U << FS8X_FS_I_FCCU_CFG_SHIFT)
3274
3275
/******************************************************************************/
3276
/* FS_I_FSSM - Type: RW */
3277
/******************************************************************************/
3278
3279
#define FS8X_FS_I_FSSM_ADDR 0x09U
3280
#define FS8X_FS_I_FSSM_DEFAULT 0x5180U
3281
3282
/**
3283
* Reflect the value of the Fault Error Counter
3284
*/
3285
#define FS8X_FS_I_FLT_ERR_CNT_MASK 0x000FU
3286
/**
3287
* Disable 8S timer
3288
*/
3289
#define FS8X_FS_I_DIS_8S_MASK 0x0010U
3290
/**
3291
* Disable Clock Monitoring
3292
*/
3293
#define FS8X_FS_I_CLK_MON_DIS_MASK 0x0020U
3294
/**
3295
* Assert RSTB in case of a short to high detected on FS0B
3296
*/
3297
#define FS8X_FS_I_FS0B_SC_HIGH_CFG_MASK 0x0080U
3298
/**
3299
* RSTB pulse duration configuration
3300
*/
3301
#define FS8X_FS_I_RSTB_DUR_MASK 0x0200U
3302
/**
3303
* Fault Error Counter intermediate value impact on RSTB/FS0B
3304
*/
3305
#define FS8X_FS_I_FLT_ERR_IMPACT_MASK 0x1800U
3306
/**
3307
* Fault Error Counter max value configuration
3308
*/
3309
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_MASK 0xC000U
3310
3311
/**
3312
* Reflect the value of the Fault Error Counter
3313
*/
3314
#define FS8X_FS_I_FLT_ERR_CNT_SHIFT 0x0000U
3315
/**
3316
* Disable 8S timer
3317
*/
3318
#define FS8X_FS_I_DIS_8S_SHIFT 0x0004U
3319
/**
3320
* Disable Clock Monitoring
3321
*/
3322
#define FS8X_FS_I_CLK_MON_DIS_SHIFT 0x0005U
3323
/**
3324
* Assert RSTB in case of a short to high detected on FS0B
3325
*/
3326
#define FS8X_FS_I_FS0B_SC_HIGH_CFG_SHIFT 0x0007U
3327
/**
3328
* RSTB pulse duration configuration
3329
*/
3330
#define FS8X_FS_I_RSTB_DUR_SHIFT 0x0009U
3331
/**
3332
* Fault Error Counter intermediate value impact on RSTB/FS0B
3333
*/
3334
#define FS8X_FS_I_FLT_ERR_IMPACT_SHIFT 0x000BU
3335
/**
3336
* Fault Error Counter max value configuration
3337
*/
3338
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_SHIFT 0x000EU
3339
3340
/**
3341
* 0
3342
*/
3343
#define FS8X_FS_I_FLT_ERR_CNT_0 (0x0000U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3344
/**
3345
* 1
3346
*/
3347
#define FS8X_FS_I_FLT_ERR_CNT_1 (0x0001U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3348
/**
3349
* 2
3350
*/
3351
#define FS8X_FS_I_FLT_ERR_CNT_2 (0x0002U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3352
/**
3353
* 3
3354
*/
3355
#define FS8X_FS_I_FLT_ERR_CNT_3 (0x0003U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3356
/**
3357
* 4
3358
*/
3359
#define FS8X_FS_I_FLT_ERR_CNT_4 (0x0004U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3360
/**
3361
* 5
3362
*/
3363
#define FS8X_FS_I_FLT_ERR_CNT_5 (0x0005U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3364
/**
3365
* 6
3366
*/
3367
#define FS8X_FS_I_FLT_ERR_CNT_6 (0x0006U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3368
/**
3369
* 7
3370
*/
3371
#define FS8X_FS_I_FLT_ERR_CNT_7 (0x0007U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3372
/**
3373
* 8
3374
*/
3375
#define FS8X_FS_I_FLT_ERR_CNT_8 (0x0008U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3376
/**
3377
* 9
3378
*/
3379
#define FS8X_FS_I_FLT_ERR_CNT_9 (0x0009U << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3380
/**
3381
* 10
3382
*/
3383
#define FS8X_FS_I_FLT_ERR_CNT_10 (0x000AU << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3384
/**
3385
* 11
3386
*/
3387
#define FS8X_FS_I_FLT_ERR_CNT_11 (0x000BU << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3388
/**
3389
* 12
3390
*/
3391
#define FS8X_FS_I_FLT_ERR_CNT_12 (0x000CU << FS8X_FS_I_FLT_ERR_CNT_SHIFT)
3392
3393
/**
3394
* RSTB LOW 8s Counter enabled
3395
*/
3396
#define FS8X_FS_I_DIS_8S_COUNTER_ENABLED (0x0000U << FS8X_FS_I_DIS_8S_SHIFT)
3397
/**
3398
* RSTB LOW 8s Counter disabled
3399
*/
3400
#define FS8X_FS_I_DIS_8S_COUNTER_DISABLED (0x0001U << FS8X_FS_I_DIS_8S_SHIFT)
3401
3402
/**
3403
* Clock Monitoring active
3404
*/
3405
#define FS8X_FS_I_CLK_MON_DIS_MONITORING_ACTIVE (0x0000U << FS8X_FS_I_CLK_MON_DIS_SHIFT)
3406
/**
3407
* Clock Monitoring disabled
3408
*/
3409
#define FS8X_FS_I_CLK_MON_DIS_MONITORING_DISABLED (0x0001U << FS8X_FS_I_CLK_MON_DIS_SHIFT)
3410
3411
/**
3412
* No assertion of the RESET
3413
*/
3414
#define FS8X_FS_I_FS0B_SC_HIGH_CFG_NO_ASSERTION (0x0000U << FS8X_FS_I_FS0B_SC_HIGH_CFG_SHIFT)
3415
/**
3416
* RESET asserted
3417
*/
3418
#define FS8X_FS_I_FS0B_SC_HIGH_CFG_RESET_ASSERTED (0x0001U << FS8X_FS_I_FS0B_SC_HIGH_CFG_SHIFT)
3419
3420
/**
3421
* 10 ms
3422
*/
3423
#define FS8X_FS_I_RSTB_DUR_10MS (0x0000U << FS8X_FS_I_RSTB_DUR_SHIFT)
3424
/**
3425
* 1 ms
3426
*/
3427
#define FS8X_FS_I_RSTB_DUR_1MS (0x0001U << FS8X_FS_I_RSTB_DUR_SHIFT)
3428
3429
/**
3430
* No effect on RSTB and FS0B
3431
*/
3432
#define FS8X_FS_I_FLT_ERR_IMPACT_NO_EFFECT (0x0000U << FS8X_FS_I_FLT_ERR_IMPACT_SHIFT)
3433
/**
3434
* FS0B only is asserted if FLT_ERR_CNT=intermediate value
3435
*/
3436
#define FS8X_FS_I_FLT_ERR_IMPACT_FS0B (0x0001U << FS8X_FS_I_FLT_ERR_IMPACT_SHIFT)
3437
/**
3438
* FS0B and RSTB are asserted if FLT_ERR_CNT=intermediate value
3439
*/
3440
#define FS8X_FS_I_FLT_ERR_IMPACT_FS0B_RSTB (0x0002U << FS8X_FS_I_FLT_ERR_IMPACT_SHIFT)
3441
3442
/**
3443
* 2
3444
*/
3445
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_2 (0x0000U << FS8X_FS_I_FLT_ERR_CNT_LIMIT_SHIFT)
3446
/**
3447
* 6
3448
*/
3449
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_6 (0x0001U << FS8X_FS_I_FLT_ERR_CNT_LIMIT_SHIFT)
3450
/**
3451
* 8
3452
*/
3453
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_8 (0x0002U << FS8X_FS_I_FLT_ERR_CNT_LIMIT_SHIFT)
3454
/**
3455
* 12
3456
*/
3457
#define FS8X_FS_I_FLT_ERR_CNT_LIMIT_12 (0x0003U << FS8X_FS_I_FLT_ERR_CNT_LIMIT_SHIFT)
3458
3459
/******************************************************************************/
3460
/* FS_I_SVS - Type: RW */
3461
/******************************************************************************/
3462
3463
#define FS8X_FS_I_SVS_ADDR 0x0BU
3464
#define FS8X_FS_I_SVS_DEFAULT 0x0000U
3465
3466
/**
3467
* Static Voltage Scaling negative offset
3468
*/
3469
#define FS8X_FS_I_SVS_OFFSET_MASK 0xF800U
3470
3471
/**
3472
* Static Voltage Scaling negative offset
3473
*/
3474
#define FS8X_FS_I_SVS_OFFSET_SHIFT 0x000BU
3475
3476
/**
3477
* 0mV
3478
*/
3479
#define FS8X_FS_I_SVS_OFFSET_EXTERNAL_REGULATOR (0x0000U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3480
/**
3481
* -6.25mV
3482
*/
3483
#define FS8X_FS_I_SVS_OFFSET_M6_25MV (0x0001U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3484
/**
3485
* -12.50mV
3486
*/
3487
#define FS8X_FS_I_SVS_OFFSET_M12_50MV (0x0002U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3488
/**
3489
* -18.75mV
3490
*/
3491
#define FS8X_FS_I_SVS_OFFSET_M18_75MV (0x0003U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3492
/**
3493
* -25mV
3494
*/
3495
#define FS8X_FS_I_SVS_OFFSET_M25MV (0x0004U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3496
/**
3497
* -31.25mV
3498
*/
3499
#define FS8X_FS_I_SVS_OFFSET_M31_25MV (0x0005U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3500
/**
3501
* -37.5mV
3502
*/
3503
#define FS8X_FS_I_SVS_OFFSET_M37_5MV (0x0006U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3504
/**
3505
* -43.75mV
3506
*/
3507
#define FS8X_FS_I_SVS_OFFSET_M43_75MV (0x0007U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3508
/**
3509
* -50mV
3510
*/
3511
#define FS8X_FS_I_SVS_OFFSET_M50MV (0x0008U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3512
/**
3513
* -56.25mV
3514
*/
3515
#define FS8X_FS_I_SVS_OFFSET_M56_25MV (0x0009U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3516
/**
3517
* -62.5mV
3518
*/
3519
#define FS8X_FS_I_SVS_OFFSET_M62_5MV (0x000AU << FS8X_FS_I_SVS_OFFSET_SHIFT)
3520
/**
3521
* -68.75mV
3522
*/
3523
#define FS8X_FS_I_SVS_OFFSET_M68_75MV (0x000BU << FS8X_FS_I_SVS_OFFSET_SHIFT)
3524
/**
3525
* -75mV
3526
*/
3527
#define FS8X_FS_I_SVS_OFFSET_M75MV (0x000CU << FS8X_FS_I_SVS_OFFSET_SHIFT)
3528
/**
3529
* -81.25mV
3530
*/
3531
#define FS8X_FS_I_SVS_OFFSET_M81_25MV (0x000DU << FS8X_FS_I_SVS_OFFSET_SHIFT)
3532
/**
3533
* -87.5mV
3534
*/
3535
#define FS8X_FS_I_SVS_OFFSET_M87_5MV (0x000EU << FS8X_FS_I_SVS_OFFSET_SHIFT)
3536
/**
3537
* -93.75mV
3538
*/
3539
#define FS8X_FS_I_SVS_OFFSET_M93_75MV (0x000FU << FS8X_FS_I_SVS_OFFSET_SHIFT)
3540
/**
3541
* -100mV
3542
*/
3543
#define FS8X_FS_I_SVS_OFFSET_M100MV (0x0010U << FS8X_FS_I_SVS_OFFSET_SHIFT)
3544
3545
/******************************************************************************/
3546
/* FS_GRL_FLAGS - Type: R */
3547
/******************************************************************************/
3548
3549
#define FS8X_FS_GRL_FLAGS_ADDR 0x00U
3550
#define FS8X_FS_GRL_FLAGS_DEFAULT 0x0000U
3551
3552
/**
3553
* Report an issue in one of the voltage monitoring (OV or UV)
3554
*/
3555
#define FS8X_FS_FS_REG_OVUV_G_MASK 0x1000U
3556
/**
3557
* Report an issue in one of the Fail Safe IOs
3558
*/
3559
#define FS8X_FS_FS_IO_G_MASK 0x2000U
3560
/**
3561
* Report an issue on the Watchdog refresh
3562
*/
3563
#define FS8X_FS_FS_WD_G_MASK 0x4000U
3564
/**
3565
* Report an issue in the communication (SPI or I2C)
3566
*/
3567
#define FS8X_FS_FS_COM_G_MASK 0x8000U
3568
3569
/**
3570
* Report an issue in one of the voltage monitoring (OV or UV)
3571
*/
3572
#define FS8X_FS_FS_REG_OVUV_G_SHIFT 0x000CU
3573
/**
3574
* Report an issue in one of the Fail Safe IOs
3575
*/
3576
#define FS8X_FS_FS_IO_G_SHIFT 0x000DU
3577
/**
3578
* Report an issue on the Watchdog refresh
3579
*/
3580
#define FS8X_FS_FS_WD_G_SHIFT 0x000EU
3581
/**
3582
* Report an issue in the communication (SPI or I2C)
3583
*/
3584
#define FS8X_FS_FS_COM_G_SHIFT 0x000FU
3585
3586
/**
3587
* No Failure
3588
*/
3589
#define FS8X_FS_FS_REG_OVUV_G_NO_FAILURE (0x0000U << FS8X_FS_FS_REG_OVUV_G_SHIFT)
3590
/**
3591
* Failure
3592
*/
3593
#define FS8X_FS_FS_REG_OVUV_G_FAILURE (0x0001U << FS8X_FS_FS_REG_OVUV_G_SHIFT)
3594
3595
/**
3596
* No Failure
3597
*/
3598
#define FS8X_FS_FS_IO_G_NO_FAILURE (0x0000U << FS8X_FS_FS_IO_G_SHIFT)
3599
/**
3600
* Failure
3601
*/
3602
#define FS8X_FS_FS_IO_G_FAILURE (0x0001U << FS8X_FS_FS_IO_G_SHIFT)
3603
3604
/**
3605
* Good WD Refresh
3606
*/
3607
#define FS8X_FS_FS_WD_G_GOOD_WD_REFRESH (0x0000U << FS8X_FS_FS_WD_G_SHIFT)
3608
/**
3609
* Bad WD Refresh
3610
*/
3611
#define FS8X_FS_FS_WD_G_BAD_WD_REFRESH (0x0001U << FS8X_FS_FS_WD_G_SHIFT)
3612
3613
/**
3614
* No Failure
3615
*/
3616
#define FS8X_FS_FS_COM_G_NO_FAILURE (0x0000U << FS8X_FS_FS_COM_G_SHIFT)
3617
/**
3618
* Failure
3619
*/
3620
#define FS8X_FS_FS_COM_G_FAILURE (0x0001U << FS8X_FS_FS_COM_G_SHIFT)
3621
3622
/******************************************************************************/
3623
/* FS_WD_WINDOW - Type: RW */
3624
/******************************************************************************/
3625
3626
#define FS8X_FS_WD_WINDOW_ADDR 0x0DU
3627
#define FS8X_FS_WD_WINDOW_DEFAULT 0x3200U
3628
3629
/**
3630
* Watchdog Window Duration when the device is in Fault Recovery Strategy.
3631
*/
3632
#define FS8X_FS_WDW_RECOVERY_MASK 0x000FU
3633
/**
3634
* CLOSED window
3635
*/
3636
#define FS8X_FS_WDW_DC_MASK 0x0700U
3637
/**
3638
* Watchdog Window Duration
3639
*/
3640
#define FS8X_FS_WD_WINDOW_MASK 0xF000U
3641
3642
/**
3643
* Watchdog Window Duration when the device is in Fault Recovery Strategy.
3644
*/
3645
#define FS8X_FS_WDW_RECOVERY_SHIFT 0x0000U
3646
/**
3647
* CLOSED window
3648
*/
3649
#define FS8X_FS_WDW_DC_SHIFT 0x0008U
3650
/**
3651
* Watchdog Window Duration
3652
*/
3653
#define FS8X_FS_WD_WINDOW_SHIFT 0x000CU
3654
3655
/**
3656
* DISABLE
3657
*/
3658
#define FS8X_FS_WDW_RECOVERY_DISABLE (0x0000U << FS8X_FS_WDW_RECOVERY_SHIFT)
3659
/**
3660
* 1.0ms
3661
*/
3662
#define FS8X_FS_WDW_RECOVERY_1MS (0x0001U << FS8X_FS_WDW_RECOVERY_SHIFT)
3663
/**
3664
* 2.0ms
3665
*/
3666
#define FS8X_FS_WDW_RECOVERY_2MS (0x0002U << FS8X_FS_WDW_RECOVERY_SHIFT)
3667
/**
3668
* 3.0ms
3669
*/
3670
#define FS8X_FS_WDW_RECOVERY_3MS (0x0003U << FS8X_FS_WDW_RECOVERY_SHIFT)
3671
/**
3672
* 4.0ms
3673
*/
3674
#define FS8X_FS_WDW_RECOVERY_4MS (0x0004U << FS8X_FS_WDW_RECOVERY_SHIFT)
3675
/**
3676
* 6.0ms
3677
*/
3678
#define FS8X_FS_WDW_RECOVERY_6MS (0x0005U << FS8X_FS_WDW_RECOVERY_SHIFT)
3679
/**
3680
* 8.0ms
3681
*/
3682
#define FS8X_FS_WDW_RECOVERY_8MS (0x0006U << FS8X_FS_WDW_RECOVERY_SHIFT)
3683
/**
3684
* 12ms
3685
*/
3686
#define FS8X_FS_WDW_RECOVERY_12MS (0x0007U << FS8X_FS_WDW_RECOVERY_SHIFT)
3687
/**
3688
* 16ms
3689
*/
3690
#define FS8X_FS_WDW_RECOVERY_16MS (0x0008U << FS8X_FS_WDW_RECOVERY_SHIFT)
3691
/**
3692
* 24ms
3693
*/
3694
#define FS8X_FS_WDW_RECOVERY_24MS (0x0009U << FS8X_FS_WDW_RECOVERY_SHIFT)
3695
/**
3696
* 32ms
3697
*/
3698
#define FS8X_FS_WDW_RECOVERY_32MS (0x000AU << FS8X_FS_WDW_RECOVERY_SHIFT)
3699
/**
3700
* 64ms
3701
*/
3702
#define FS8X_FS_WDW_RECOVERY_64MS (0x000BU << FS8X_FS_WDW_RECOVERY_SHIFT)
3703
/**
3704
* 128ms
3705
*/
3706
#define FS8X_FS_WDW_RECOVERY_128MS (0x000CU << FS8X_FS_WDW_RECOVERY_SHIFT)
3707
/**
3708
* 256ms
3709
*/
3710
#define FS8X_FS_WDW_RECOVERY_256MS (0x000DU << FS8X_FS_WDW_RECOVERY_SHIFT)
3711
/**
3712
* 512ms
3713
*/
3714
#define FS8X_FS_WDW_RECOVERY_512MS (0x000EU << FS8X_FS_WDW_RECOVERY_SHIFT)
3715
/**
3716
* 1024ms
3717
*/
3718
#define FS8X_FS_WDW_RECOVERY_1024MS (0x000FU << FS8X_FS_WDW_RECOVERY_SHIFT)
3719
3720
/**
3721
* 31.25%
3722
*/
3723
#define FS8X_FS_WDW_DC_31_25 (0x0000U << FS8X_FS_WDW_DC_SHIFT)
3724
/**
3725
* 37.5%
3726
*/
3727
#define FS8X_FS_WDW_DC_37_5 (0x0001U << FS8X_FS_WDW_DC_SHIFT)
3728
/**
3729
* 50%
3730
*/
3731
#define FS8X_FS_WDW_DC_50 (0x0002U << FS8X_FS_WDW_DC_SHIFT)
3732
/**
3733
* 62.5%
3734
*/
3735
#define FS8X_FS_WDW_DC_62_5 (0x0003U << FS8X_FS_WDW_DC_SHIFT)
3736
/**
3737
* 68.75%
3738
*/
3739
#define FS8X_FS_WDW_DC_68_75 (0x0004U << FS8X_FS_WDW_DC_SHIFT)
3740
3741
/**
3742
* DISABLE (during INIT_FS only)
3743
*/
3744
#define FS8X_FS_WD_WINDOW_DISABLE (0x0000U << FS8X_FS_WD_WINDOW_SHIFT)
3745
/**
3746
* 1.0ms
3747
*/
3748
#define FS8X_FS_WD_WINDOW_1MS (0x0001U << FS8X_FS_WD_WINDOW_SHIFT)
3749
/**
3750
* 2.0ms
3751
*/
3752
#define FS8X_FS_WD_WINDOW_2MS (0x0002U << FS8X_FS_WD_WINDOW_SHIFT)
3753
/**
3754
* 3.0ms
3755
*/
3756
#define FS8X_FS_WD_WINDOW_3MS (0x0003U << FS8X_FS_WD_WINDOW_SHIFT)
3757
/**
3758
* 4.0ms
3759
*/
3760
#define FS8X_FS_WD_WINDOW_4MS (0x0004U << FS8X_FS_WD_WINDOW_SHIFT)
3761
/**
3762
* 6.0ms
3763
*/
3764
#define FS8X_FS_WD_WINDOW_6MS (0x0005U << FS8X_FS_WD_WINDOW_SHIFT)
3765
/**
3766
* 8.0ms
3767
*/
3768
#define FS8X_FS_WD_WINDOW_8MS (0x0006U << FS8X_FS_WD_WINDOW_SHIFT)
3769
/**
3770
* 12ms
3771
*/
3772
#define FS8X_FS_WD_WINDOW_12MS (0x0007U << FS8X_FS_WD_WINDOW_SHIFT)
3773
/**
3774
* 16ms
3775
*/
3776
#define FS8X_FS_WD_WINDOW_16MS (0x0008U << FS8X_FS_WD_WINDOW_SHIFT)
3777
/**
3778
* 24ms
3779
*/
3780
#define FS8X_FS_WD_WINDOW_24MS (0x0009U << FS8X_FS_WD_WINDOW_SHIFT)
3781
/**
3782
* 32ms
3783
*/
3784
#define FS8X_FS_WD_WINDOW_32MS (0x000AU << FS8X_FS_WD_WINDOW_SHIFT)
3785
/**
3786
* 64ms
3787
*/
3788
#define FS8X_FS_WD_WINDOW_64MS (0x000BU << FS8X_FS_WD_WINDOW_SHIFT)
3789
/**
3790
* 128ms
3791
*/
3792
#define FS8X_FS_WD_WINDOW_128MS (0x000CU << FS8X_FS_WD_WINDOW_SHIFT)
3793
/**
3794
* 256ms
3795
*/
3796
#define FS8X_FS_WD_WINDOW_256MS (0x000DU << FS8X_FS_WD_WINDOW_SHIFT)
3797
/**
3798
* 512ms
3799
*/
3800
#define FS8X_FS_WD_WINDOW_512MS (0x000EU << FS8X_FS_WD_WINDOW_SHIFT)
3801
/**
3802
* 1024ms
3803
*/
3804
#define FS8X_FS_WD_WINDOW_1024MS (0x000FU << FS8X_FS_WD_WINDOW_SHIFT)
3805
3806
/******************************************************************************/
3807
/* FS_WD_SEED - Type: RW */
3808
/******************************************************************************/
3809
3810
#define FS8X_FS_WD_SEED_ADDR 0x0FU
3811
#define FS8X_FS_WD_SEED_DEFAULT 0x5AB2U
3812
3813
/**
3814
* Seed for the LFSR
3815
*/
3816
#define FS8X_FS_WD_SEED_MASK 0xFFFFU
3817
3818
/**
3819
* Seed for the LFSR
3820
*/
3821
#define FS8X_FS_WD_SEED_SHIFT 0x0000U
3822
3823
/******************************************************************************/
3824
/* FS_WD_ANSWER - Type: RW */
3825
/******************************************************************************/
3826
3827
#define FS8X_FS_WD_ANSWER_ADDR 0x10U
3828
#define FS8X_FS_WD_ANSWER_DEFAULT 0x0000U
3829
3830
/**
3831
* WATCHDOG LFSR VALUE
3832
*/
3833
#define FS8X_FS_WD_ANSWER_MASK 0xFFFFU
3834
3835
/**
3836
* WATCHDOG LFSR VALUE
3837
*/
3838
#define FS8X_FS_WD_ANSWER_SHIFT 0x0000U
3839
3840
/******************************************************************************/
3841
/* FS_OVUVREG_STATUS - Type: RW */
3842
/******************************************************************************/
3843
3844
#define FS8X_FS_OVUVREG_STATUS_ADDR 0x11U
3845
#define FS8X_FS_OVUVREG_STATUS_DEFAULT 0x5550U
3846
3847
/**
3848
* Drift of the Fail Safe OSC
3849
*/
3850
#define FS8X_FS_FS_OSC_DRIFT_MASK 0x0002U
3851
/**
3852
* Overvoltage of the Internal Digital Fail Safe reference voltage
3853
*/
3854
#define FS8X_FS_FS_DIG_REF_OV_MASK 0x0004U
3855
/**
3856
* Undervoltage Monitoring on VMON1
3857
*/
3858
#define FS8X_FS_VMON1_UV_MASK 0x0010U
3859
/**
3860
* Overvoltage Monitoring on VMON1
3861
*/
3862
#define FS8X_FS_VMON1_OV_MASK 0x0020U
3863
/**
3864
* Undervoltage Monitoring on VMON2
3865
*/
3866
#define FS8X_FS_VMON2_UV_MASK 0x0040U
3867
/**
3868
* Overvoltage Monitoring on VMON2
3869
*/
3870
#define FS8X_FS_VMON2_OV_MASK 0x0080U
3871
/**
3872
* Undervoltage Monitoring on VMON3
3873
*/
3874
#define FS8X_FS_VMON3_UV_MASK 0x0100U
3875
/**
3876
* Overvoltage Monitoring on VMON3
3877
*/
3878
#define FS8X_FS_VMON3_OV_MASK 0x0200U
3879
/**
3880
* Undervoltage Monitoring on VMON4
3881
*/
3882
#define FS8X_FS_VMON4_UV_MASK 0x0400U
3883
/**
3884
* Overvoltage Monitoring on VMON4
3885
*/
3886
#define FS8X_FS_VMON4_OV_MASK 0x0800U
3887
/**
3888
* Undervoltage Monitoring on VDDIO
3889
*/
3890
#define FS8X_FS_VDDIO_UV_MASK 0x1000U
3891
/**
3892
* Overvoltage Monitoring on VDDIO
3893
*/
3894
#define FS8X_FS_VDDIO_OV_MASK 0x2000U
3895
/**
3896
* Undervoltage Monitoring on VCOREMON
3897
*/
3898
#define FS8X_FS_VCOREMON_UV_MASK 0x4000U
3899
/**
3900
* Overvoltage Monitoring on VCOREMON
3901
*/
3902
#define FS8X_FS_VCOREMON_OV_MASK 0x8000U
3903
3904
/**
3905
* Drift of the Fail Safe OSC
3906
*/
3907
#define FS8X_FS_FS_OSC_DRIFT_SHIFT 0x0001U
3908
/**
3909
* Overvoltage of the Internal Digital Fail Safe reference voltage
3910
*/
3911
#define FS8X_FS_FS_DIG_REF_OV_SHIFT 0x0002U
3912
/**
3913
* Undervoltage Monitoring on VMON1
3914
*/
3915
#define FS8X_FS_VMON1_UV_SHIFT 0x0004U
3916
/**
3917
* Overvoltage Monitoring on VMON1
3918
*/
3919
#define FS8X_FS_VMON1_OV_SHIFT 0x0005U
3920
/**
3921
* Undervoltage Monitoring on VMON2
3922
*/
3923
#define FS8X_FS_VMON2_UV_SHIFT 0x0006U
3924
/**
3925
* Overvoltage Monitoring on VMON2
3926
*/
3927
#define FS8X_FS_VMON2_OV_SHIFT 0x0007U
3928
/**
3929
* Undervoltage Monitoring on VMON3
3930
*/
3931
#define FS8X_FS_VMON3_UV_SHIFT 0x0008U
3932
/**
3933
* Overvoltage Monitoring on VMON3
3934
*/
3935
#define FS8X_FS_VMON3_OV_SHIFT 0x0009U
3936
/**
3937
* Undervoltage Monitoring on VMON4
3938
*/
3939
#define FS8X_FS_VMON4_UV_SHIFT 0x000AU
3940
/**
3941
* Overvoltage Monitoring on VMON4
3942
*/
3943
#define FS8X_FS_VMON4_OV_SHIFT 0x000BU
3944
/**
3945
* Undervoltage Monitoring on VDDIO
3946
*/
3947
#define FS8X_FS_VDDIO_UV_SHIFT 0x000CU
3948
/**
3949
* Overvoltage Monitoring on VDDIO
3950
*/
3951
#define FS8X_FS_VDDIO_OV_SHIFT 0x000DU
3952
/**
3953
* Undervoltage Monitoring on VCOREMON
3954
*/
3955
#define FS8X_FS_VCOREMON_UV_SHIFT 0x000EU
3956
/**
3957
* Overvoltage Monitoring on VCOREMON
3958
*/
3959
#define FS8X_FS_VCOREMON_OV_SHIFT 0x000FU
3960
3961
/**
3962
* No Drift
3963
*/
3964
#define FS8X_FS_FS_OSC_DRIFT_NO_DRIFT (0x0000U << FS8X_FS_FS_OSC_DRIFT_SHIFT)
3965
/**
3966
* Oscillator Drift
3967
*/
3968
#define FS8X_FS_FS_OSC_DRIFT_OSCILLATOR_DRIFT (0x0001U << FS8X_FS_FS_OSC_DRIFT_SHIFT)
3969
3970
/**
3971
* No Overvoltage
3972
*/
3973
#define FS8X_FS_FS_DIG_REF_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_FS_DIG_REF_OV_SHIFT)
3974
/**
3975
* Overvoltage reported of the internal digital fail safe reference voltage
3976
*/
3977
#define FS8X_FS_FS_DIG_REF_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_FS_DIG_REF_OV_SHIFT)
3978
3979
/**
3980
* No Undervoltage
3981
*/
3982
#define FS8X_FS_VMON1_UV_NO_UNDERVOLTAGE (0x0000U << FS8X_FS_VMON1_UV_SHIFT)
3983
/**
3984
* Undervoltage Reported on VMON1
3985
*/
3986
#define FS8X_FS_VMON1_UV_UNDERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON1_UV_SHIFT)
3987
3988
/**
3989
* No Overvoltage
3990
*/
3991
#define FS8X_FS_VMON1_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_VMON1_OV_SHIFT)
3992
/**
3993
* Overvoltage Reported on VMON1
3994
*/
3995
#define FS8X_FS_VMON1_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON1_OV_SHIFT)
3996
3997
/**
3998
* No Undervoltage
3999
*/
4000
#define FS8X_FS_VMON2_UV_NO_UNDERVOLTAGE (0x0000U << FS8X_FS_VMON2_UV_SHIFT)
4001
/**
4002
* Undervoltage Reported on VMON2
4003
*/
4004
#define FS8X_FS_VMON2_UV_UNDERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON2_UV_SHIFT)
4005
4006
/**
4007
* No Overvoltage
4008
*/
4009
#define FS8X_FS_VMON2_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_VMON2_OV_SHIFT)
4010
/**
4011
* Overvoltage Reported on VMON2
4012
*/
4013
#define FS8X_FS_VMON2_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON2_OV_SHIFT)
4014
4015
/**
4016
* No Undervoltage
4017
*/
4018
#define FS8X_FS_VMON3_UV_NO_UNDERVOLTAGE (0x0000U << FS8X_FS_VMON3_UV_SHIFT)
4019
/**
4020
* Undervoltage Reported on VMON3
4021
*/
4022
#define FS8X_FS_VMON3_UV_UNDERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON3_UV_SHIFT)
4023
4024
/**
4025
* No Overvoltage
4026
*/
4027
#define FS8X_FS_VMON3_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_VMON3_OV_SHIFT)
4028
/**
4029
* Overvoltage Reported on VMON3
4030
*/
4031
#define FS8X_FS_VMON3_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON3_OV_SHIFT)
4032
4033
/**
4034
* No Undervoltage
4035
*/
4036
#define FS8X_FS_VMON4_UV_NO_UNDERVOLTAGE (0x0000U << FS8X_FS_VMON4_UV_SHIFT)
4037
/**
4038
* Undervoltage Reported on VMON4
4039
*/
4040
#define FS8X_FS_VMON4_UV_UNDERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON4_UV_SHIFT)
4041
4042
/**
4043
* No Overvoltage
4044
*/
4045
#define FS8X_FS_VMON4_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_VMON4_OV_SHIFT)
4046
/**
4047
* Overvoltage Reported on VMON4
4048
*/
4049
#define FS8X_FS_VMON4_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VMON4_OV_SHIFT)
4050
4051
/**
4052
* No Undervoltage
4053
*/
4054
#define FS8X_FS_VDDIO_UV_NO_UNDERVOLTAGE (0x0000U << FS8X_FS_VDDIO_UV_SHIFT)
4055
/**
4056
* Undervoltage Reported on VDDIO
4057
*/
4058
#define FS8X_FS_VDDIO_UV_UNDERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VDDIO_UV_SHIFT)
4059
4060
/**
4061
* No Overvoltage
4062
*/
4063
#define FS8X_FS_VDDIO_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_VDDIO_OV_SHIFT)
4064
/**
4065
* Overvoltage Reported on VDDIO
4066
*/
4067
#define FS8X_FS_VDDIO_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VDDIO_OV_SHIFT)
4068
4069
/**
4070
* No Undervoltage
4071
*/
4072
#define FS8X_FS_VCOREMON_UV_NO_UNDERVOLTAGE (0x0000U << FS8X_FS_VCOREMON_UV_SHIFT)
4073
/**
4074
* Undervoltage Reported on VCOREMON
4075
*/
4076
#define FS8X_FS_VCOREMON_UV_UNDERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VCOREMON_UV_SHIFT)
4077
4078
/**
4079
* No Overvoltage
4080
*/
4081
#define FS8X_FS_VCOREMON_OV_NO_OVERVOLTAGE (0x0000U << FS8X_FS_VCOREMON_OV_SHIFT)
4082
/**
4083
* Overvoltage Reported on VCOREMON
4084
*/
4085
#define FS8X_FS_VCOREMON_OV_OVERVOLTAGE_REPORTED (0x0001U << FS8X_FS_VCOREMON_OV_SHIFT)
4086
4087
/******************************************************************************/
4088
/* FS_RELEASE_FS0B - Type: RW */
4089
/******************************************************************************/
4090
4091
#define FS8X_FS_RELEASE_FS0B_ADDR 0x12U
4092
#define FS8X_FS_RELEASE_FS0B_DEFAULT 0x0000U
4093
4094
/**
4095
* Secure 16bits word to release FS0B
4096
*/
4097
#define FS8X_FS_RELEASE_FS0B_MASK 0xFFFFU
4098
4099
/**
4100
* Secure 16bits word to release FS0B
4101
*/
4102
#define FS8X_FS_RELEASE_FS0B_SHIFT 0x0000U
4103
4104
/******************************************************************************/
4105
/* FS_SAFE_IOS - Type: RW */
4106
/******************************************************************************/
4107
4108
#define FS8X_FS_SAFE_IOS_ADDR 0x13U
4109
#define FS8X_FS_SAFE_IOS_DEFAULT 0x0000U
4110
4111
/**
4112
* Report FCCU1 pin real time state
4113
*/
4114
#define FS8X_FS_FCCU1_RT_MASK 0x0001U
4115
/**
4116
* Report FCCU2 pin real time state
4117
*/
4118
#define FS8X_FS_FCCU2_RT_MASK 0x0002U
4119
/**
4120
* Go back to INIT Fail Safe request
4121
*/
4122
#define FS8X_FS_GO_TO_INITFS_MASK 0x0004U
4123
/**
4124
* Request assertion of FS0B
4125
*/
4126
#define FS8X_FS_FS0B_REQ_MASK 0x0008U
4127
/**
4128
* Report a Failure on FS0B
4129
*/
4130
#define FS8X_FS_FS0B_DIAG_MASK 0x0010U
4131
/**
4132
* Sense of FS0B pad
4133
*/
4134
#define FS8X_FS_FS0B_SNS_MASK 0x0020U
4135
/**
4136
* FS0B driver _ digital command
4137
*/
4138
#define FS8X_FS_FS0B_DRV_MASK 0x0040U
4139
/**
4140
* Request assertion of RSTB (Pulse)
4141
*/
4142
#define FS8X_FS_RSTB_REQ_MASK 0x0080U
4143
/**
4144
* Report a RSTB Short to High
4145
*/
4146
#define FS8X_FS_RSTB_DIAG_MASK 0x0100U
4147
/**
4148
* Report a RSTB event
4149
*/
4150
#define FS8X_FS_RSTB_EVENT_MASK 0x0200U
4151
/**
4152
* Sense of RSTB pad
4153
*/
4154
#define FS8X_FS_RSTB_SNS_MASK 0x0400U
4155
/**
4156
* RSTB driver _ digital command
4157
*/
4158
#define FS8X_FS_RSTB_DRV_MASK 0x0800U
4159
/**
4160
* Report an External RESET
4161
*/
4162
#define FS8X_FS_EXT_RSTB_MASK 0x1000U
4163
/**
4164
* Sense of PGOOD pad
4165
*/
4166
#define FS8X_FS_PGOOD_SNS_MASK 0x2000U
4167
/**
4168
* Report a Power GOOD event
4169
*/
4170
#define FS8X_FS_PGOOD_EVENT_MASK 0x4000U
4171
/**
4172
* Report a PGOOD Short to High
4173
*/
4174
#define FS8X_FS_PGOOD_DIAG_MASK 0x8000U
4175
4176
/**
4177
* Report FCCU1 pin real time state
4178
*/
4179
#define FS8X_FS_FCCU1_RT_SHIFT 0x0000U
4180
/**
4181
* Report FCCU2 pin real time state
4182
*/
4183
#define FS8X_FS_FCCU2_RT_SHIFT 0x0001U
4184
/**
4185
* Go back to INIT Fail Safe request
4186
*/
4187
#define FS8X_FS_GO_TO_INITFS_SHIFT 0x0002U
4188
/**
4189
* Request assertion of FS0B
4190
*/
4191
#define FS8X_FS_FS0B_REQ_SHIFT 0x0003U
4192
/**
4193
* Report a Failure on FS0B
4194
*/
4195
#define FS8X_FS_FS0B_DIAG_SHIFT 0x0004U
4196
/**
4197
* Sense of FS0B pad
4198
*/
4199
#define FS8X_FS_FS0B_SNS_SHIFT 0x0005U
4200
/**
4201
* FS0B driver _ digital command
4202
*/
4203
#define FS8X_FS_FS0B_DRV_SHIFT 0x0006U
4204
/**
4205
* Request assertion of RSTB (Pulse)
4206
*/
4207
#define FS8X_FS_RSTB_REQ_SHIFT 0x0007U
4208
/**
4209
* Report a RSTB Short to High
4210
*/
4211
#define FS8X_FS_RSTB_DIAG_SHIFT 0x0008U
4212
/**
4213
* Report a RSTB event
4214
*/
4215
#define FS8X_FS_RSTB_EVENT_SHIFT 0x0009U
4216
/**
4217
* Sense of RSTB pad
4218
*/
4219
#define FS8X_FS_RSTB_SNS_SHIFT 0x000AU
4220
/**
4221
* RSTB driver _ digital command
4222
*/
4223
#define FS8X_FS_RSTB_DRV_SHIFT 0x000BU
4224
/**
4225
* Report an External RESET
4226
*/
4227
#define FS8X_FS_EXT_RSTB_SHIFT 0x000CU
4228
/**
4229
* Sense of PGOOD pad
4230
*/
4231
#define FS8X_FS_PGOOD_SNS_SHIFT 0x000DU
4232
/**
4233
* Report a Power GOOD event
4234
*/
4235
#define FS8X_FS_PGOOD_EVENT_SHIFT 0x000EU
4236
/**
4237
* Report a PGOOD Short to High
4238
*/
4239
#define FS8X_FS_PGOOD_DIAG_SHIFT 0x000FU
4240
4241
/**
4242
* Low level
4243
*/
4244
#define FS8X_FS_FCCU1_RT_LOW_LEVEL (0x0000U << FS8X_FS_FCCU1_RT_SHIFT)
4245
/**
4246
* High level
4247
*/
4248
#define FS8X_FS_FCCU1_RT_HIGH_LEVEL (0x0001U << FS8X_FS_FCCU1_RT_SHIFT)
4249
4250
/**
4251
* Low level
4252
*/
4253
#define FS8X_FS_FCCU2_RT_LOW_LEVEL (0x0000U << FS8X_FS_FCCU2_RT_SHIFT)
4254
/**
4255
* High level
4256
*/
4257
#define FS8X_FS_FCCU2_RT_HIGH_LEVEL (0x0001U << FS8X_FS_FCCU2_RT_SHIFT)
4258
4259
/**
4260
* No action
4261
*/
4262
#define FS8X_FS_GO_TO_INITFS_NO_ACTION (0x0000U << FS8X_FS_GO_TO_INITFS_SHIFT)
4263
/**
4264
* Go back to INIT_FS
4265
*/
4266
#define FS8X_FS_GO_TO_INITFS_GO_BACK_TO_INIT_FS (0x0001U << FS8X_FS_GO_TO_INITFS_SHIFT)
4267
4268
/**
4269
* No Assertion
4270
*/
4271
#define FS8X_FS_FS0B_REQ_NO_ASSERTION (0x0000U << FS8X_FS_FS0B_REQ_SHIFT)
4272
/**
4273
* FS0B Assertion
4274
*/
4275
#define FS8X_FS_FS0B_REQ_FS0B_ASSERTION (0x0001U << FS8X_FS_FS0B_REQ_SHIFT)
4276
4277
/**
4278
* No Failure
4279
*/
4280
#define FS8X_FS_FS0B_DIAG_NO_FAILURE (0x0000U << FS8X_FS_FS0B_DIAG_SHIFT)
4281
/**
4282
* Short Circuit High
4283
*/
4284
#define FS8X_FS_FS0B_DIAG_SHORT_CIRCUIT_HIGH (0x0001U << FS8X_FS_FS0B_DIAG_SHIFT)
4285
4286
/**
4287
* FS0B pad sensed low
4288
*/
4289
#define FS8X_FS_FS0B_SNS_PAD_SENSED_LOW (0x0000U << FS8X_FS_FS0B_SNS_SHIFT)
4290
/**
4291
* FS0B pad sensed high
4292
*/
4293
#define FS8X_FS_FS0B_SNS_PAD_SENSED_HIGH (0x0001U << FS8X_FS_FS0B_SNS_SHIFT)
4294
4295
/**
4296
* FS0B driver command sensed low
4297
*/
4298
#define FS8X_FS_FS0B_DRV_COMMAND_SENSED_LOW (0x0000U << FS8X_FS_FS0B_DRV_SHIFT)
4299
/**
4300
* FS0B driver command sensed high
4301
*/
4302
#define FS8X_FS_FS0B_DRV_COMMAND_SENSED_HIGH (0x0001U << FS8X_FS_FS0B_DRV_SHIFT)
4303
4304
/**
4305
* No Assertion
4306
*/
4307
#define FS8X_FS_RSTB_REQ_NO_ASSERTION (0x0000U << FS8X_FS_RSTB_REQ_SHIFT)
4308
/**
4309
* RSTB Assertion (Pulse)
4310
*/
4311
#define FS8X_FS_RSTB_REQ_RSTB_ASSERTION (0x0001U << FS8X_FS_RSTB_REQ_SHIFT)
4312
4313
/**
4314
* No Failure
4315
*/
4316
#define FS8X_FS_RSTB_DIAG_NO_FAILURE (0x0000U << FS8X_FS_RSTB_DIAG_SHIFT)
4317
/**
4318
* Short Circuit High
4319
*/
4320
#define FS8X_FS_RSTB_DIAG_SHORT_CIRCUIT_HIGH (0x0001U << FS8X_FS_RSTB_DIAG_SHIFT)
4321
4322
/**
4323
* No RESET
4324
*/
4325
#define FS8X_FS_RSTB_EVENT_NO_RESET (0x0000U << FS8X_FS_RSTB_EVENT_SHIFT)
4326
/**
4327
* RESET occurred
4328
*/
4329
#define FS8X_FS_RSTB_EVENT_RESET_OCCURRED (0x0001U << FS8X_FS_RSTB_EVENT_SHIFT)
4330
4331
/**
4332
* RSTB pad sensed low
4333
*/
4334
#define FS8X_FS_RSTB_SNS_PAD_SENSED_LOW (0x0000U << FS8X_FS_RSTB_SNS_SHIFT)
4335
/**
4336
* RSTB pad sensed high
4337
*/
4338
#define FS8X_FS_RSTB_SNS_PAD_SENSED_HIGH (0x0001U << FS8X_FS_RSTB_SNS_SHIFT)
4339
4340
/**
4341
* RSTB driver command sensed low
4342
*/
4343
#define FS8X_FS_RSTB_DRV_COMMAND_SENSED_LOW (0x0000U << FS8X_FS_RSTB_DRV_SHIFT)
4344
/**
4345
* RSTB driver command sensed high
4346
*/
4347
#define FS8X_FS_RSTB_DRV_COMMAND_SENSED_HIGH (0x0001U << FS8X_FS_RSTB_DRV_SHIFT)
4348
4349
/**
4350
* No External RESET
4351
*/
4352
#define FS8X_FS_EXT_RSTB_NO_EXTERNAL_RESET (0x0000U << FS8X_FS_EXT_RSTB_SHIFT)
4353
/**
4354
* External RESET
4355
*/
4356
#define FS8X_FS_EXT_RSTB_EXTERNAL_RESET (0x0001U << FS8X_FS_EXT_RSTB_SHIFT)
4357
4358
/**
4359
* PGOOD pad sensed low
4360
*/
4361
#define FS8X_FS_PGOOD_SNS_PAD_SENSED_LOW (0x0000U << FS8X_FS_PGOOD_SNS_SHIFT)
4362
/**
4363
* PGOOD pad sensed high
4364
*/
4365
#define FS8X_FS_PGOOD_SNS_PAD_SENSED_HIGH (0x0001U << FS8X_FS_PGOOD_SNS_SHIFT)
4366
4367
/**
4368
* No Power GOOD
4369
*/
4370
#define FS8X_FS_PGOOD_EVENT_NO_POWER_GOOD (0x0000U << FS8X_FS_PGOOD_EVENT_SHIFT)
4371
/**
4372
* Power Good event occurred
4373
*/
4374
#define FS8X_FS_PGOOD_EVENT_POWER_GOOD_EVENT_OCCURRED (0x0001U << FS8X_FS_PGOOD_EVENT_SHIFT)
4375
4376
/**
4377
* No Failure
4378
*/
4379
#define FS8X_FS_PGOOD_DIAG_NO_FAILURE (0x0000U << FS8X_FS_PGOOD_DIAG_SHIFT)
4380
/**
4381
* Short-Circuit HIGH
4382
*/
4383
#define FS8X_FS_PGOOD_DIAG_SHORT_CIRCUIT_HIGH (0x0001U << FS8X_FS_PGOOD_DIAG_SHIFT)
4384
4385
/******************************************************************************/
4386
/* FS_DIAG_SAFETY - Type: RW */
4387
/******************************************************************************/
4388
4389
#define FS8X_FS_DIAG_SAFETY_ADDR 0x14U
4390
#define FS8X_FS_DIAG_SAFETY_DEFAULT 0x0000U
4391
4392
/**
4393
* Diagnostic of Logical BIST
4394
*/
4395
#define FS8X_FS_LBIST_OK_MASK 0x0001U
4396
/**
4397
* Invalid Fail Safe I2C access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address)
4398
*/
4399
#define FS8X_FS_I2C_FS_REQ_MASK 0x0002U
4400
/**
4401
* Fail Safe I2C communication CRC issue
4402
*/
4403
#define FS8X_FS_I2C_FS_CRC_MASK 0x0004U
4404
/**
4405
* Fail Safe SPI communication CRC issue
4406
*/
4407
#define FS8X_FS_SPI_FS_CRC_MASK 0x0008U
4408
/**
4409
* Invalid Fail Safe SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address)
4410
*/
4411
#define FS8X_FS_SPI_FS_REQ_MASK 0x0010U
4412
/**
4413
* Fail Safe SPI SCLK error detection
4414
*/
4415
#define FS8X_FS_SPI_FS_CLK_MASK 0x0020U
4416
/**
4417
* Diagnostic of Analog BIST2
4418
*/
4419
#define FS8X_FS_ABIST2_OK_MASK 0x0040U
4420
/**
4421
* Diagnostic of Analog BIST1
4422
*/
4423
#define FS8X_FS_ABIST1_OK_MASK 0x0080U
4424
/**
4425
* WD refresh status - Timing
4426
*/
4427
#define FS8X_FS_BAD_WD_TIMING_MASK 0x0100U
4428
/**
4429
* WD Refresh status - Data
4430
*/
4431
#define FS8X_FS_BAD_WD_DATA_MASK 0x0200U
4432
/**
4433
* Report ERRMON pin level
4434
*/
4435
#define FS8X_FS_ERRMON_STATUS_MASK 0x0400U
4436
/**
4437
* Report an error in the ERRMON input
4438
*/
4439
#define FS8X_FS_ERRMON_MASK 0x0800U
4440
/**
4441
* Acknowledge ERRMON failure detection from MCU
4442
*/
4443
#define FS8X_FS_ERRMON_ACK_MASK 0x1000U
4444
/**
4445
* Report an error in the FCCU2 input
4446
*/
4447
#define FS8X_FS_FCCU2_MASK 0x2000U
4448
/**
4449
* Report an error in the FCCU1 input
4450
*/
4451
#define FS8X_FS_FCCU1_MASK 0x4000U
4452
/**
4453
* Report an error in the FCCU12 input
4454
*/
4455
#define FS8X_FS_FCCU12_MASK 0x8000U
4456
4457
/**
4458
* Diagnostic of Logical BIST
4459
*/
4460
#define FS8X_FS_LBIST_OK_SHIFT 0x0000U
4461
/**
4462
* Invalid Fail Safe I2C access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address)
4463
*/
4464
#define FS8X_FS_I2C_FS_REQ_SHIFT 0x0001U
4465
/**
4466
* Fail Safe I2C communication CRC issue
4467
*/
4468
#define FS8X_FS_I2C_FS_CRC_SHIFT 0x0002U
4469
/**
4470
* Fail Safe SPI communication CRC issue
4471
*/
4472
#define FS8X_FS_SPI_FS_CRC_SHIFT 0x0003U
4473
/**
4474
* Invalid Fail Safe SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address)
4475
*/
4476
#define FS8X_FS_SPI_FS_REQ_SHIFT 0x0004U
4477
/**
4478
* Fail Safe SPI SCLK error detection
4479
*/
4480
#define FS8X_FS_SPI_FS_CLK_SHIFT 0x0005U
4481
/**
4482
* Diagnostic of Analog BIST2
4483
*/
4484
#define FS8X_FS_ABIST2_OK_SHIFT 0x0006U
4485
/**
4486
* Diagnostic of Analog BIST1
4487
*/
4488
#define FS8X_FS_ABIST1_OK_SHIFT 0x0007U
4489
/**
4490
* WD refresh status - Timing
4491
*/
4492
#define FS8X_FS_BAD_WD_TIMING_SHIFT 0x0008U
4493
/**
4494
* WD Refresh status - Data
4495
*/
4496
#define FS8X_FS_BAD_WD_DATA_SHIFT 0x0009U
4497
/**
4498
* Report ERRMON pin level
4499
*/
4500
#define FS8X_FS_ERRMON_STATUS_SHIFT 0x000AU
4501
/**
4502
* Report an error in the ERRMON input
4503
*/
4504
#define FS8X_FS_ERRMON_SHIFT 0x000BU
4505
/**
4506
* Acknowledge ERRMON failure detection from MCU
4507
*/
4508
#define FS8X_FS_ERRMON_ACK_SHIFT 0x000CU
4509
/**
4510
* Report an error in the FCCU2 input
4511
*/
4512
#define FS8X_FS_FCCU2_SHIFT 0x000DU
4513
/**
4514
* Report an error in the FCCU1 input
4515
*/
4516
#define FS8X_FS_FCCU1_SHIFT 0x000EU
4517
/**
4518
* Report an error in the FCCU12 input
4519
*/
4520
#define FS8X_FS_FCCU12_SHIFT 0x000FU
4521
4522
/**
4523
* LBIST FAIL
4524
*/
4525
#define FS8X_FS_LBIST_OK_FAIL (0x0000U << FS8X_FS_LBIST_OK_SHIFT)
4526
/**
4527
* LBIST PASS
4528
*/
4529
#define FS8X_FS_LBIST_OK_PASS (0x0001U << FS8X_FS_LBIST_OK_SHIFT)
4530
4531
/**
4532
* No error
4533
*/
4534
#define FS8X_FS_I2C_FS_REQ_NO_ERROR (0x0000U << FS8X_FS_I2C_FS_REQ_SHIFT)
4535
/**
4536
* I2c Violation
4537
*/
4538
#define FS8X_FS_I2C_FS_REQ_I2C_VIOLATION (0x0001U << FS8X_FS_I2C_FS_REQ_SHIFT)
4539
4540
/**
4541
* No error
4542
*/
4543
#define FS8X_FS_I2C_FS_CRC_NO_ERROR (0x0000U << FS8X_FS_I2C_FS_CRC_SHIFT)
4544
/**
4545
* Error detected in the CRC
4546
*/
4547
#define FS8X_FS_I2C_FS_CRC_ERROR_DETECTED (0x0001U << FS8X_FS_I2C_FS_CRC_SHIFT)
4548
4549
/**
4550
* No error
4551
*/
4552
#define FS8X_FS_SPI_FS_CRC_NO_ERROR (0x0000U << FS8X_FS_SPI_FS_CRC_SHIFT)
4553
/**
4554
* Error detected in the CRC
4555
*/
4556
#define FS8X_FS_SPI_FS_CRC_ERROR_DETECTED (0x0001U << FS8X_FS_SPI_FS_CRC_SHIFT)
4557
4558
/**
4559
* No error
4560
*/
4561
#define FS8X_FS_SPI_FS_REQ_NO_ERROR (0x0000U << FS8X_FS_SPI_FS_REQ_SHIFT)
4562
/**
4563
* SPI Violation
4564
*/
4565
#define FS8X_FS_SPI_FS_REQ_SPI_VIOLATION (0x0001U << FS8X_FS_SPI_FS_REQ_SHIFT)
4566
4567
/**
4568
* No error
4569
*/
4570
#define FS8X_FS_SPI_FS_CLK_NO_ERROR (0x0000U << FS8X_FS_SPI_FS_CLK_SHIFT)
4571
/**
4572
* Wrong number of clock cycles <32 or >32)
4573
*/
4574
#define FS8X_FS_SPI_FS_CLK_WRONG_NUMBER_OF_CLOCK_CYCLES (0x0001U << FS8X_FS_SPI_FS_CLK_SHIFT)
4575
4576
/**
4577
* ABIST2 FAIL or NOT EXECUTED
4578
*/
4579
#define FS8X_FS_ABIST2_OK_ABIST2_FAIL (0x0000U << FS8X_FS_ABIST2_OK_SHIFT)
4580
/**
4581
* PASS
4582
*/
4583
#define FS8X_FS_ABIST2_OK_PASS (0x0001U << FS8X_FS_ABIST2_OK_SHIFT)
4584
4585
/**
4586
* ABIST1 FAIL or NOT EXECUTED
4587
*/
4588
#define FS8X_FS_ABIST1_OK_ABIST1_FAIL (0x0000U << FS8X_FS_ABIST1_OK_SHIFT)
4589
/**
4590
* PASS
4591
*/
4592
#define FS8X_FS_ABIST1_OK_PASS (0x0001U << FS8X_FS_ABIST1_OK_SHIFT)
4593
4594
/**
4595
* Good WD Refresh
4596
*/
4597
#define FS8X_FS_BAD_WD_TIMING_GOOD_WD_REFRESH (0x0000U << FS8X_FS_BAD_WD_TIMING_SHIFT)
4598
/**
4599
* Bad WD refresh, wrong window or in timeout
4600
*/
4601
#define FS8X_FS_BAD_WD_TIMING_BAD_WD_REFRESH (0x0001U << FS8X_FS_BAD_WD_TIMING_SHIFT)
4602
4603
/**
4604
* Good WD Refresh
4605
*/
4606
#define FS8X_FS_BAD_WD_DATA_GOOD_WD_REFRESH (0x0000U << FS8X_FS_BAD_WD_DATA_SHIFT)
4607
/**
4608
* Bad WD refresh, error in the DATA
4609
*/
4610
#define FS8X_FS_BAD_WD_DATA_BAD_WD_REFRESH (0x0001U << FS8X_FS_BAD_WD_DATA_SHIFT)
4611
4612
/**
4613
* LOW Level
4614
*/
4615
#define FS8X_FS_ERRMON_STATUS_LOW_LEVEL (0x0000U << FS8X_FS_ERRMON_STATUS_SHIFT)
4616
/**
4617
* HIGH Level
4618
*/
4619
#define FS8X_FS_ERRMON_STATUS_HIGH_LEVEL (0x0001U << FS8X_FS_ERRMON_STATUS_SHIFT)
4620
4621
/**
4622
* No error
4623
*/
4624
#define FS8X_FS_ERRMON_NO_ERROR (0x0000U << FS8X_FS_ERRMON_SHIFT)
4625
/**
4626
* Error detected
4627
*/
4628
#define FS8X_FS_ERRMON_ERROR_DETECTED (0x0001U << FS8X_FS_ERRMON_SHIFT)
4629
4630
/**
4631
* No effect
4632
*/
4633
#define FS8X_FS_ERRMON_ACK_NO_EFFECT (0x0000U << FS8X_FS_ERRMON_ACK_SHIFT)
4634
/**
4635
* Acknowledge ERRMON failure detection
4636
*/
4637
#define FS8X_FS_ERRMON_ACK_FAILURE_DETECTION (0x0001U << FS8X_FS_ERRMON_ACK_SHIFT)
4638
4639
/**
4640
* No error
4641
*/
4642
#define FS8X_FS_FCCU2_NO_ERROR (0x0000U << FS8X_FS_FCCU2_SHIFT)
4643
/**
4644
* Error detected
4645
*/
4646
#define FS8X_FS_FCCU2_ERROR_DETECTED (0x0001U << FS8X_FS_FCCU2_SHIFT)
4647
4648
/**
4649
* No error
4650
*/
4651
#define FS8X_FS_FCCU1_NO_ERROR (0x0000U << FS8X_FS_FCCU1_SHIFT)
4652
/**
4653
* Error detected
4654
*/
4655
#define FS8X_FS_FCCU1_ERROR_DETECTED (0x0001U << FS8X_FS_FCCU1_SHIFT)
4656
4657
/**
4658
* No error
4659
*/
4660
#define FS8X_FS_FCCU12_NO_ERROR (0x0000U << FS8X_FS_FCCU12_SHIFT)
4661
/**
4662
* Error detected
4663
*/
4664
#define FS8X_FS_FCCU12_ERROR_DETECTED (0x0001U << FS8X_FS_FCCU12_SHIFT)
4665
4666
/******************************************************************************/
4667
/* FS_INTB_MASK - Type: RW */
4668
/******************************************************************************/
4669
4670
#define FS8X_FS_INTB_MASK_ADDR 0x15U
4671
#define FS8X_FS_INTB_MASK_DEFAULT 0x0000U
4672
4673
/**
4674
* Inhibit INTERRUPT on FCCU1 event
4675
*/
4676
#define FS8X_FS_INT_INH_FCCU1_MASK 0x0001U
4677
/**
4678
* Inhibit INTERRUPT on FCCU2 event
4679
*/
4680
#define FS8X_FS_INT_INH_FCCU2_MASK 0x0002U
4681
/**
4682
* Inhibit INTERRUPT on ERRMON event
4683
*/
4684
#define FS8X_FS_INT_INH_ERRMON_MASK 0x0004U
4685
/**
4686
* Inhibit INTERRUPT on bad WD refresh event
4687
*/
4688
#define FS8X_FS_INT_INH_BAD_WD_REFRESH_MASK 0x0008U
4689
/**
4690
* Inhibit INTERRUPT on VCOREMON OV and UV event
4691
*/
4692
#define FS8X_FS_INT_INH_VCOREMON_OV_UV_MASK 0x0010U
4693
/**
4694
* Inhibit INTERRUPT on VDDIO OV and UV event
4695
*/
4696
#define FS8X_FS_INT_INH_VDDIO_OV_UV_MASK 0x0020U
4697
/**
4698
* Inhibit INTERRUPT on VMON1 OV and UV event
4699
*/
4700
#define FS8X_FS_INT_INH_VMON1_OV_UV_MASK 0x0040U
4701
/**
4702
* Inhibit INTERRUPT on VMON2 OV and UV event
4703
*/
4704
#define FS8X_FS_INT_INH_VMON2_OV_UV_MASK 0x0080U
4705
/**
4706
* Inhibit INTERRUPT on VMON3 OV and UV event
4707
*/
4708
#define FS8X_FS_INT_INH_VMON3_OV_UV_MASK 0x0100U
4709
/**
4710
* Inhibit INTERRUPT on VMON4 OV and UV event
4711
*/
4712
#define FS8X_FS_INT_INH_VMON4_OV_UV_MASK 0x0200U
4713
4714
/**
4715
* Inhibit INTERRUPT on FCCU1 event
4716
*/
4717
#define FS8X_FS_INT_INH_FCCU1_SHIFT 0x0000U
4718
/**
4719
* Inhibit INTERRUPT on FCCU2 event
4720
*/
4721
#define FS8X_FS_INT_INH_FCCU2_SHIFT 0x0001U
4722
/**
4723
* Inhibit INTERRUPT on ERRMON event
4724
*/
4725
#define FS8X_FS_INT_INH_ERRMON_SHIFT 0x0002U
4726
/**
4727
* Inhibit INTERRUPT on bad WD refresh event
4728
*/
4729
#define FS8X_FS_INT_INH_BAD_WD_REFRESH_SHIFT 0x0003U
4730
/**
4731
* Inhibit INTERRUPT on VCOREMON OV and UV event
4732
*/
4733
#define FS8X_FS_INT_INH_VCOREMON_OV_UV_SHIFT 0x0004U
4734
/**
4735
* Inhibit INTERRUPT on VDDIO OV and UV event
4736
*/
4737
#define FS8X_FS_INT_INH_VDDIO_OV_UV_SHIFT 0x0005U
4738
/**
4739
* Inhibit INTERRUPT on VMON1 OV and UV event
4740
*/
4741
#define FS8X_FS_INT_INH_VMON1_OV_UV_SHIFT 0x0006U
4742
/**
4743
* Inhibit INTERRUPT on VMON2 OV and UV event
4744
*/
4745
#define FS8X_FS_INT_INH_VMON2_OV_UV_SHIFT 0x0007U
4746
/**
4747
* Inhibit INTERRUPT on VMON3 OV and UV event
4748
*/
4749
#define FS8X_FS_INT_INH_VMON3_OV_UV_SHIFT 0x0008U
4750
/**
4751
* Inhibit INTERRUPT on VMON4 OV and UV event
4752
*/
4753
#define FS8X_FS_INT_INH_VMON4_OV_UV_SHIFT 0x0009U
4754
4755
/**
4756
* Interruption NOT MASKED
4757
*/
4758
#define FS8X_FS_INT_INH_FCCU1_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_FCCU1_SHIFT)
4759
/**
4760
* Interruption MASKED
4761
*/
4762
#define FS8X_FS_INT_INH_FCCU1_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_FCCU1_SHIFT)
4763
4764
/**
4765
* Interruption NOT MASKED
4766
*/
4767
#define FS8X_FS_INT_INH_FCCU2_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_FCCU2_SHIFT)
4768
/**
4769
* Interruption MASKED
4770
*/
4771
#define FS8X_FS_INT_INH_FCCU2_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_FCCU2_SHIFT)
4772
4773
/**
4774
* Interruption NOT MASKED
4775
*/
4776
#define FS8X_FS_INT_INH_ERRMON_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_ERRMON_SHIFT)
4777
/**
4778
* Interruption MASKED
4779
*/
4780
#define FS8X_FS_INT_INH_ERRMON_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_ERRMON_SHIFT)
4781
4782
/**
4783
* Interruption NOT MASKED
4784
*/
4785
#define FS8X_FS_INT_INH_BAD_WD_REFRESH_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_BAD_WD_REFRESH_SHIFT)
4786
/**
4787
* Interruption MASKED
4788
*/
4789
#define FS8X_FS_INT_INH_BAD_WD_REFRESH_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_BAD_WD_REFRESH_SHIFT)
4790
4791
/**
4792
* Interruption NOT MASKED
4793
*/
4794
#define FS8X_FS_INT_INH_VCOREMON_OV_UV_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_VCOREMON_OV_UV_SHIFT)
4795
/**
4796
* Interruption MASKED
4797
*/
4798
#define FS8X_FS_INT_INH_VCOREMON_OV_UV_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_VCOREMON_OV_UV_SHIFT)
4799
4800
/**
4801
* Interruption NOT MASKED
4802
*/
4803
#define FS8X_FS_INT_INH_VDDIO_OV_UV_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_VDDIO_OV_UV_SHIFT)
4804
/**
4805
* Interruption MASKED
4806
*/
4807
#define FS8X_FS_INT_INH_VDDIO_OV_UV_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_VDDIO_OV_UV_SHIFT)
4808
4809
/**
4810
* Interruption NOT MASKED
4811
*/
4812
#define FS8X_FS_INT_INH_VMON1_OV_UV_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_VMON1_OV_UV_SHIFT)
4813
/**
4814
* Interruption MASKED
4815
*/
4816
#define FS8X_FS_INT_INH_VMON1_OV_UV_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_VMON1_OV_UV_SHIFT)
4817
4818
/**
4819
* Interruption NOT MASKED
4820
*/
4821
#define FS8X_FS_INT_INH_VMON2_OV_UV_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_VMON2_OV_UV_SHIFT)
4822
/**
4823
* Interruption MASKED
4824
*/
4825
#define FS8X_FS_INT_INH_VMON2_OV_UV_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_VMON2_OV_UV_SHIFT)
4826
4827
/**
4828
* Interruption NOT MASKED
4829
*/
4830
#define FS8X_FS_INT_INH_VMON3_OV_UV_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_VMON3_OV_UV_SHIFT)
4831
/**
4832
* Interruption MASKED
4833
*/
4834
#define FS8X_FS_INT_INH_VMON3_OV_UV_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_VMON3_OV_UV_SHIFT)
4835
4836
/**
4837
* Interruption NOT MASKED
4838
*/
4839
#define FS8X_FS_INT_INH_VMON4_OV_UV_INTERRUPTION_NOT_MASKED (0x0000U << FS8X_FS_INT_INH_VMON4_OV_UV_SHIFT)
4840
/**
4841
* Interruption MASKED
4842
*/
4843
#define FS8X_FS_INT_INH_VMON4_OV_UV_INTERRUPTION_MASKED (0x0001U << FS8X_FS_INT_INH_VMON4_OV_UV_SHIFT)
4844
4845
/******************************************************************************/
4846
/* FS_STATES - Type: RW */
4847
/******************************************************************************/
4848
4849
#define FS8X_FS_STATES_ADDR 0x16U
4850
#define FS8X_FS_STATES_DEFAULT 0x0000U
4851
4852
/**
4853
* FS FSM current state (MSB bit 4 = 0 - extended for future uage)
4854
*/
4855
#define FS8X_FS_FSM_STATE_MASK 0x001FU
4856
/**
4857
* INIT register corruption detection
4858
*/
4859
#define FS8X_FS_REG_CORRUPT_MASK 0x0200U
4860
/**
4861
* OTP bits corruption detection (5ms cyclic check)
4862
*/
4863
#define FS8X_FS_OTP_CORRUPT_MASK 0x0800U
4864
/**
4865
* DEBUG mode status
4866
*/
4867
#define FS8X_FS_DBG_MODE_MASK 0x2000U
4868
/**
4869
* Leave DEBUG mode
4870
*/
4871
#define FS8X_FS_DBG_EXIT_MASK 0x4000U
4872
/**
4873
* Test Mode Activation Status
4874
*/
4875
#define FS8X_FS_TM_ACTIVE_MASK 0x8000U
4876
4877
/**
4878
* FS FSM current state (MSB bit 4 = 0 - extended for future uage)
4879
*/
4880
#define FS8X_FS_FSM_STATE_SHIFT 0x0000U
4881
/**
4882
* INIT register corruption detection
4883
*/
4884
#define FS8X_FS_REG_CORRUPT_SHIFT 0x0009U
4885
/**
4886
* OTP bits corruption detection (5ms cyclic check)
4887
*/
4888
#define FS8X_FS_OTP_CORRUPT_SHIFT 0x000BU
4889
/**
4890
* DEBUG mode status
4891
*/
4892
#define FS8X_FS_DBG_MODE_SHIFT 0x000DU
4893
/**
4894
* Leave DEBUG mode
4895
*/
4896
#define FS8X_FS_DBG_EXIT_SHIFT 0x000EU
4897
/**
4898
* Test Mode Activation Status
4899
*/
4900
#define FS8X_FS_TM_ACTIVE_SHIFT 0x000FU
4901
4902
/**
4903
* INIT_FS
4904
*/
4905
#define FS8X_FS_FSM_STATE_INIT_FS (0x0006U << FS8X_FS_FSM_STATE_SHIFT)
4906
/**
4907
* WAIT_ABIST2
4908
*/
4909
#define FS8X_FS_FSM_STATE_WAIT_ABIST2 (0x0007U << FS8X_FS_FSM_STATE_SHIFT)
4910
/**
4911
* ABIST2
4912
*/
4913
#define FS8X_FS_FSM_STATE_ABIST2 (0x0008U << FS8X_FS_FSM_STATE_SHIFT)
4914
/**
4915
* ASSERT_FS0B
4916
*/
4917
#define FS8X_FS_FSM_STATE_ASSERT_FS0B (0x0009U << FS8X_FS_FSM_STATE_SHIFT)
4918
/**
4919
* NORMAL_FS
4920
*/
4921
#define FS8X_FS_FSM_STATE_NORMAL_FS (0x000AU << FS8X_FS_FSM_STATE_SHIFT)
4922
4923
/**
4924
* No corruption detected in init registers (i.e. no mismatch between register/register_NOT) pair
4925
*/
4926
#define FS8X_FS_REG_CORRUPT_NO_ERROR (0x0000U << FS8X_FS_REG_CORRUPT_SHIFT)
4927
/**
4928
* Data content corruption detected in init registers (i.e. mismatch between register/register_NOT) pair
4929
*/
4930
#define FS8X_FS_REG_CORRUPT_ERROR (0x0001U << FS8X_FS_REG_CORRUPT_SHIFT)
4931
4932
/**
4933
* No OTP content CRC error detected
4934
*/
4935
#define FS8X_FS_OTP_CORRUPT_NO_ERROR (0x0000U << FS8X_FS_OTP_CORRUPT_SHIFT)
4936
/**
4937
* OTP content CRC error detected
4938
*/
4939
#define FS8X_FS_OTP_CORRUPT_ERROR (0x0001U << FS8X_FS_OTP_CORRUPT_SHIFT)
4940
4941
/**
4942
* NOT in DEBUG mode
4943
*/
4944
#define FS8X_FS_DBG_MODE_NO_DEBUG (0x0000U << FS8X_FS_DBG_MODE_SHIFT)
4945
/**
4946
* In DEBUG mode
4947
*/
4948
#define FS8X_FS_DBG_MODE_DEBUG (0x0001U << FS8X_FS_DBG_MODE_SHIFT)
4949
4950
/**
4951
* No Action
4952
*/
4953
#define FS8X_FS_DBG_EXIT_NO_ACTION (0x0000U << FS8X_FS_DBG_EXIT_SHIFT)
4954
/**
4955
* Leave DEBUG mode
4956
*/
4957
#define FS8X_FS_DBG_EXIT_LEAVE_DEBUG_MODE (0x0001U << FS8X_FS_DBG_EXIT_SHIFT)
4958
4959
/**
4960
* Test mode is not activated
4961
*/
4962
#define FS8X_FS_TM_ACTIVE_NOT_ACTIVE (0x0000U << FS8X_FS_TM_ACTIVE_SHIFT)
4963
/**
4964
* Test mode is activated
4965
*/
4966
#define FS8X_FS_TM_ACTIVE_ACTIVE (0x0001U << FS8X_FS_TM_ACTIVE_SHIFT)
4967
4968
#endif
/* SBC_FS8X_MAP_H__ */
src
app
driver
sbc
fs8x_driver
sbc_fs8x_map.h
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