foxBMS - Unit Tests  1.2.1
The foxBMS Unit Tests API Documentation
spi.c
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41 
42 /**
43  * @file spi.c
44  * @author foxBMS Team
45  * @date 2019-12-12 (date of creation)
46  * @updated 2021-12-08 (date of last update)
47  * @ingroup DRIVERS
48  * @prefix SPI
49  *
50  * @brief Driver for the SPI module.
51  *
52  */
53 
54 /*========== Includes =======================================================*/
55 #include "spi.h"
56 
57 #include "HL_reg_spi.h"
58 #include "HL_spi.h"
59 #include "HL_sys_common.h"
60 
61 #include "dma.h"
62 #include "fsystem.h"
63 #include "io.h"
64 #include "mcu.h"
65 #include "os.h"
66 
68 
69 /*========== Macros and Definitions =========================================*/
70 /** Bitfield to check for transmission errors in SPI FLAG register */
71 #define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS (0x5Fu)
72 
73 /*========== Static Constant and Variable Definitions =======================*/
74 
75 /*========== Extern Constant and Variable Definitions =======================*/
76 
77 /*========== Static Function Prototypes =====================================*/
78 
79 /*========== Static Function Implementations ================================*/
80 
81 /*========== Extern Function Implementations ================================*/
82 
83 extern STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay) {
84  FAS_ASSERT(pSpiInterface != NULL_PTR);
85  uint16_t txDummy[1] = {0x00};
86  STD_RETURN_TYPE_e retVal = SPI_TransmitData(pSpiInterface, txDummy, 1u);
87  MCU_delay_us(delay);
88  return retVal;
89 }
90 
91 extern STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint32 frameLength) {
92  FAS_ASSERT(pSpiInterface != NULL_PTR);
93  FAS_ASSERT(pTxBuff != NULL_PTR);
94  FAS_ASSERT(frameLength > 0u);
96 
97  /* Lock SPI hardware to prevent concurrent read/write commands */
98  if (STD_OK == SPI_Lock(SPI_GetSpiIndex(pSpiInterface->pNode))) {
99  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
100 
101  /** SW Chip Select */
102  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
103  /** Set SPI Chip Select pins as GIOs */
104  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
105  /** Activate Chip Select */
106  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
107  }
108  /** HW Chip Select */
109  if (pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE) {
110  /**
111  * Activate HW Chip Select according to bitmask register CSNR
112  * by setting pins as SPI functional pins
113  */
114  /** First deactivate all HW Chip Selects */
115  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
116  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
117  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
118  /** Bitmask = 0 --> HW CS active
119  * --> write to PC0 to set pin as SPI pin (and not GIO)
120  */
121  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
122  }
123  }
124  }
125  uint32_t spiRetval = spiTransmitData(pSpiInterface->pNode, pSpiInterface->pConfig, frameLength, pTxBuff);
126  /** SW Chip Select */
127  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
128  /** Deactivate Chip Select */
129  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
130  }
131 
132  /* Unlock SPI hardware */
133  SPI_Unlock(SPI_GetSpiIndex(pSpiInterface->pNode));
134 
135  /* Transmission successful */
136  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
137  retval = STD_OK;
138  }
139  }
140  return retval;
141 }
142 
144  SPI_INTERFACE_CONFIG_s *pSpiInterface,
145  uint16 *pTxBuff,
146  uint16 *pRxBuff,
147  uint32 frameLength) {
148  FAS_ASSERT(pSpiInterface != NULL_PTR);
149  FAS_ASSERT(pTxBuff != NULL_PTR);
150  FAS_ASSERT(pRxBuff != NULL_PTR);
151  FAS_ASSERT(frameLength > 0u);
152  STD_RETURN_TYPE_e retval = STD_NOT_OK;
153 
154  /* Lock SPI hardware to prevent concurrent read/write commands */
155  if (STD_OK == SPI_Lock(SPI_GetSpiIndex(pSpiInterface->pNode))) {
156  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
157 
158  /** SW Chip Select */
159  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
160  /** Set SPI Chip Select pins as GIOs */
161  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
162  /** Activate Chip Select */
163  IO_PinReset(pSpiInterface->pGioPort, pSpiInterface->csPin);
164  }
165  /** HW Chip Select */
166  if (pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE) {
167  /**
168  * Activate HW Chip Select according to bitmask register CSNR
169  * by setting pins as SPI functional pins
170  */
171  /** First deactivate all HW Chip Selects */
172  pSpiInterface->pNode->PC0 &= SPI_PC0_CLEAR_HW_CS_MASK;
173  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
174  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
175  /** Bitmask = 0 --> HW CS active
176  * --> write to PC0 to set pin as SPI pin (and not GIO)
177  */
178  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
179  }
180  }
181  }
182  uint32_t spiRetval =
183  spiTransmitAndReceiveData(pSpiInterface->pNode, pSpiInterface->pConfig, frameLength, pTxBuff, pRxBuff);
184  /** SW Chip Select */
185  if (pSpiInterface->csType == SPI_CHIP_SELECT_SOFTWARE) {
186  /** Deactivate Chip Select */
187  IO_PinSet(pSpiInterface->pGioPort, pSpiInterface->csPin);
188  }
189 
190  /* Unlock SPI hardware */
191  SPI_Unlock(SPI_GetSpiIndex(pSpiInterface->pNode));
192 
193  /* Transmission successful */
194  if ((spiRetval & SPI_FLAG_REGISTER_TRANSMISSION_ERRORS) == 0u) {
195  retval = STD_OK;
196  }
197  }
198  return retval;
199 }
200 
202  SPI_INTERFACE_CONFIG_s *pSpiInterface,
203  uint16 *pTxBuff,
204  uint16 *pRxBuff,
205  uint32 frameLength) {
206  FAS_ASSERT(pSpiInterface != NULL_PTR);
207  FAS_ASSERT(pTxBuff != NULL_PTR);
208  FAS_ASSERT(pRxBuff != NULL_PTR);
209  FAS_ASSERT(frameLength > 0u);
210 
211  (void)spiTransmitAndReceiveData(pSpiInterface->pNode, pSpiInterface->pConfig, frameLength, pTxBuff, pRxBuff);
212 }
213 
215  SPI_INTERFACE_CONFIG_s *pSpiInterface,
216  uint16_t *pTxBuff,
217  uint16_t *pRxBuff,
218  uint32_t frameLength) {
219  FAS_ASSERT(frameLength > 2u);
220  FAS_ASSERT(pSpiInterface != NULL_PTR);
221  FAS_ASSERT(pTxBuff != NULL_PTR);
222  FAS_ASSERT(pRxBuff != NULL_PTR);
223  /** SPI over DMA currently only compatible with HW Chip Select */
224  FAS_ASSERT(pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE);
225  FAS_ASSERT(SPI_GetSpiIndex(pSpiInterface->pNode) < spi_nrBusyFlags);
226 
227  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
228 
230  /* Lock SPI hardware to prevent concurrent read/write commands */
231  if (spi_busyFlags[SPI_GetSpiIndex(pSpiInterface->pNode)] == SPI_IDLE) {
232  spi_busyFlags[SPI_GetSpiIndex(pSpiInterface->pNode)] = SPI_BUSY;
233 
234  /* Check that not SPI transmission over DMA is taking place */
235  if ((pSpiInterface->pNode->INT0 & DMAREQEN_BIT) == 0x0) {
236  /* The upper 16 bits will be written in the SPI DAT1 register where they serve as configuration */
237  uint32 Chip_Select_Hold = 0u;
238  if (pSpiInterface->pConfig->CS_HOLD == TRUE) {
239  Chip_Select_Hold = SPI_CSHOLD_BIT;
240  } else {
241  Chip_Select_Hold = 0U;
242  }
243  uint32 WDelay = 0u;
244  if (pSpiInterface->pConfig->WDEL == TRUE) {
245  WDelay = SPI_WDEL_BIT;
246  } else {
247  WDelay = 0U;
248  }
249  SPIDATAFMT_t DataFormat = pSpiInterface->pConfig->DFSEL;
250  uint8 ChipSelect = pSpiInterface->pConfig->CSNR;
251 
252  /* Go to privilege mode to write DMA config registers */
253  (void)FSYS_RaisePrivilege();
254 
255  spi_txLastWord[SPI_GetSpiIndex(pSpiInterface->pNode)] = pTxBuff[frameLength - 1u];
256  spi_txLastWord[SPI_GetSpiIndex(pSpiInterface->pNode)] |=
257  ((uint32)DataFormat << SPI_DATA_FORMAT_FIELD_POSITION) |
258  ((uint32)ChipSelect << SPI_HARDWARE_CHIP_SELECT_FIELD_POSITION) | (WDelay);
259 
260  /* Set Tx buffer address */
261  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel].ISADDR =
262  (uint32_t)(&pTxBuff[1u]); /* First word sent manually to write configuration in SPIDAT1 register */
263  /**
264  * Set number of Tx words to send
265  * Last word sent in ISR to set CSHOLD = 0
266  */
267  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel].ITCOUNT =
268  ((frameLength - 2u) << 16U) | 1U; /* Last word sent manually to write CSHOLD in SPIDAT1 register */
269 
270  /* Set Rx buffer address */
271  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel].IDADDR =
272  (uint32_t)pRxBuff;
273  /* Set number of Rx words to receive */
274  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel].ITCOUNT =
275  (frameLength << 16U) | 1U;
276 
277  /* Re-enable channels; because auto-init is disabled */
278  /* Disable otherwise transmission is constantly ongoing */
279  dmaSetChEnable(
280  (dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel,
281  (dmaTriggerType_t)DMA_HW);
282  dmaSetChEnable(
283  (dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel,
284  (dmaTriggerType_t)DMA_HW);
285 
286  /* DMA config registers written, leave privilege mode */
288 
289  /* DMA_REQ_Enable */
290  /* Starts DMA requests if SPIEN is also set to 1 */
291  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
292  uint32_t txBuffer = pTxBuff[0u];
293  txBuffer |= ((uint32)DataFormat << 24U) | ((uint32)ChipSelect << 16U) | (WDelay) | (Chip_Select_Hold);
294  /**
295  * Send first word without DMA because when writing config to DAT1
296  * the HW CS pin are asserted immediately, even if SPIEN bit in GCR1 is 0.
297  * The C2TDELAY is then taken into account before the transmission.
298  */
299  pSpiInterface->pNode->DAT1 = txBuffer;
300  uint32_t timeoutIterations = SPI_TX_EMPTY_TIMEOUT_ITERATIONS;
301  while (((pSpiInterface->pNode->FLG & (uint32)((uint32_t)1u << SPI_TX_BUFFER_EMPTY_FLAG_POSITION)) == 0u) &&
302  (timeoutIterations > 0u)) {
303  timeoutIterations--;
304  }
305  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
306 
307  retVal = STD_OK;
308  }
309  }
311 
312  return retVal;
313 }
314 
315 extern STD_RETURN_TYPE_e SPI_Lock(uint8_t spi) {
316  STD_RETURN_TYPE_e retVal = STD_NOT_OK;
317 
319  if ((*(spi_busyFlags + spi) == SPI_IDLE) && (spi < spi_nrBusyFlags)) {
320  *(spi_busyFlags + spi) = SPI_BUSY;
321  retVal = STD_OK;
322  } else {
323  retVal = STD_NOT_OK;
324  }
326 
327  return retVal;
328 }
329 
330 extern void SPI_Unlock(uint8_t spi) {
332  if (spi < spi_nrBusyFlags) {
333  *(spi_busyFlags + spi) = SPI_IDLE;
334  }
336 }
337 
338 extern void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled) {
339  FAS_ASSERT(pNode != NULL_PTR);
340  FAS_ASSERT(bit <= (enum spiPinSelect)LARGEST_PIN_NUMBER);
341 
342  /* retrieve current configuration */
343  spi_config_reg_t configRegisterBuffer = {0};
344  if (pNode == spiREG1) {
345  spi1GetConfigValue(&configRegisterBuffer, CurrentValue);
346  } else if (pNode == spiREG2) {
347  spi2GetConfigValue(&configRegisterBuffer, CurrentValue);
348  } else if (pNode == spiREG3) {
349  spi3GetConfigValue(&configRegisterBuffer, CurrentValue);
350  } else if (pNode == spiREG4) {
351  spi4GetConfigValue(&configRegisterBuffer, CurrentValue);
352  } else if (pNode == spiREG5) {
353  spi5GetConfigValue(&configRegisterBuffer, CurrentValue);
354  } else {
355  /* invalid SPI node */
357  }
358  uint32_t newPc0 = configRegisterBuffer.CONFIG_PC0;
359 
360  if (hardwareControlled == false) {
361  /* bit has to be cleared */
362  newPc0 &= ~(uint32_t)((uint32_t)1u << (uint8_t)(bit));
363  } else {
364  /* bit has to be set */
365  newPc0 |= (uint32_t)((uint32_t)1u << (uint8_t)(bit));
366  }
367 
368  /* set new port value */
369  spiSetFunctional(pNode, newPc0);
370 }
371 
373  SPI_INTERFACE_CONFIG_s *pSpiInterface,
374  uint16_t *pTxBuff,
375  uint16_t *pRxBuff,
376  uint32_t frameLength) {
377  FAS_ASSERT(pSpiInterface != NULL_PTR);
378  FAS_ASSERT(pTxBuff != NULL_PTR);
379  FAS_ASSERT(pRxBuff != NULL_PTR);
380  FAS_ASSERT(frameLength > 0u);
381  /** SPI receive works only with HW Chip Select */
382  FAS_ASSERT(pSpiInterface->csType == SPI_CHIP_SELECT_HARDWARE);
383 
384  STD_RETURN_TYPE_e retVal = STD_OK;
385 
387  /* Go to privilege mode to write DMA config registers */
388  (void)FSYS_RaisePrivilege();
389 
390  /* DMA_REQ Disable */
391  pSpiInterface->pNode->INT0 &= ~DMAREQEN_BIT;
392  pSpiInterface->pNode->GCR1 &= ~SPIEN_BIT;
393 
394  /* Set Tx buffer address */
395  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel].ISADDR =
396  (uint32_t)pTxBuff;
397  /* Set number of Tx bytes to send */
398  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel].ITCOUNT =
399  (frameLength << 16U) | 1U;
400 
401  /* Set Rx buffer address */
402  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel].IDADDR =
403  (uint32_t)pRxBuff;
404  /* Set number of Rx bytes to receive */
405  dmaRAMREG->PCP[(dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel].ITCOUNT =
406  (frameLength << 16U) | 1U;
407 
408  /* Re-enable channels; because auto-init is disabled */
409  /* Disable otherwise transmission is constantly ongoping */
410  dmaSetChEnable(
411  (dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].txChannel, (dmaTriggerType_t)DMA_HW);
412  dmaSetChEnable(
413  (dmaChannel_t)dma_spiDmaChannels[SPI_GetSpiIndex(pSpiInterface->pNode)].rxChannel, (dmaTriggerType_t)DMA_HW);
414 
415  /* DMA config registers written, leave privilege mode */
417 
419 
420  /* Activate chip selects according to bitmask register CSNR */
421  for (uint8_t csNumber = 0u; csNumber < SPI_MAX_NUMBER_HW_CS; csNumber++) {
422  if (((pSpiInterface->pConfig->CSNR >> csNumber) & 0x1u) == 0u) {
423  /* Bitmask = 0 --> HW CS active --> set pin as SPI functional pin */
424  pSpiInterface->pNode->PC0 |= (uint32_t)1u << csNumber;
425  }
426  }
427 
428  /* DMA_REQ Enable */
429  /* Starts DMA requests if SPIEN is also set to 1 */
430  pSpiInterface->pNode->GCR1 |= SPIEN_BIT;
431  pSpiInterface->pNode->INT0 |= DMAREQEN_BIT;
432 
433  return retVal;
434 }
435 
436 extern void SPI_DmaSendLastByte(uint8_t spiIndex) {
438  dma_spiInterfaces[spiIndex]->DAT1 = spi_txLastWord[spiIndex];
439 }
440 
441 /* AXIVION Next Line Style Linker-Multiple_Definition: TI HAL only provides a weak implementation */
442 void UNIT_TEST_WEAK_IMPL spiNotification(spiBASE_t *spi, uint32 flags) {
443 }
444 
446  FAS_ASSERT(pNode != NULL_PTR);
447  const SpiDataStatus_t spiStatus = SpiTxStatus(pNode);
448  STD_RETURN_TYPE_e retval = STD_OK;
449  if (spiStatus == SPI_PENDING) {
450  retval = STD_NOT_OK;
451  }
452  return retval;
453 }
454 
455 extern uint8_t SPI_GetSpiIndex(spiBASE_t *pNode) {
456  FAS_ASSERT(pNode != NULL_PTR);
457  uint8_t spiIndex = 0u;
458 
459  if (pNode == spiREG1) {
460  spiIndex = SPI_SPI1_INDEX;
461  } else if (pNode == spiREG2) {
462  spiIndex = SPI_SPI2_INDEX;
463  } else if (pNode == spiREG3) {
464  spiIndex = SPI_SPI3_INDEX;
465  } else if (pNode == spiREG4) {
466  spiIndex = SPI_SPI4_INDEX;
467  } else if (pNode == spiREG5) {
468  spiIndex = SPI_SPI5_INDEX;
469  } else {
470  /** Invalid SPI node */
472  }
473 
474  return spiIndex;
475 }
476 
477 /*========== Externalized Static Function Implementations (Unit Test) =======*/
Headers for the driver for the DMA module.
spiBASE_t * dma_spiInterfaces[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:86
DMA_CHANNEL_CONFIG_s dma_spiDmaChannels[DMA_NUMBER_SPI_INTERFACES]
Definition: dma_cfg.c:68
#define SPIEN_BIT
Definition: dma_cfg.h:110
#define DMA_NUMBER_SPI_INTERFACES
Definition: dma_cfg.h:106
#define DMAREQEN_BIT
Definition: dma_cfg.h:108
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:235
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:110
@ STD_NOT_OK
Definition: fstd_types.h:82
@ STD_OK
Definition: fstd_types.h:81
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:75
enum STD_RETURN_TYPE STD_RETURN_TYPE_e
Function to switch between user mode and privilege mode.
#define FSYS_SwitchToUserMode()
Switch back to user mode.
Definition: fsystem.h:113
long FSYS_RaisePrivilege(void)
raise privilege
Definition: test_htsensor.c:66
#define LARGEST_PIN_NUMBER
largest pin number that exists in TMS570LC4357
Definition: general.h:73
#define UNIT_TEST_WEAK_IMPL
Definition: general.h:108
void IO_PinSet(volatile uint32_t *pRegisterAddress, uint32_t pin)
Set pin by writing in pin output register.
Definition: io.c:84
void IO_PinReset(volatile uint32_t *pRegisterAddress, uint32_t pin)
Reset pin by writing in pin output register.
Definition: io.c:91
Header for the driver for the IO module.
void MCU_delay_us(uint32_t delay_us)
Wait blocking a certain time in microseconds.
Definition: mcu.c:80
Headers for the driver for the MCU module.
Declaration of the OS wrapper interface.
void OS_ExitTaskCritical(void)
Exit Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os_freertos.c:125
void OS_EnterTaskCritical(void)
Enter Critical interface function for use in FreeRTOS-Tasks and FreeRTOS-ISR.
Definition: os_freertos.c:121
STD_RETURN_TYPE_e SPI_TransmitReceiveDataDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:214
void SPI_SetFunctional(spiBASE_t *pNode, enum spiPinSelect bit, bool hardwareControlled)
Sets the functional of a SPI pin.
Definition: spi.c:338
STD_RETURN_TYPE_e SPI_CheckInterfaceAvailable(spiBASE_t *pNode)
Returns STD_OK if the SPI interface can be used again.
Definition: spi.c:445
void SPI_DmaSendLastByte(uint8_t spiIndex)
Used to send last byte per SPI.
Definition: spi.c:436
STD_RETURN_TYPE_e SPI_TransmitDummyByte(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint32_t delay)
Sends a dummy byte to wake up the SPI interface.
Definition: spi.c:83
void SPI_FramTransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA, wrappe for FRAM.
Definition: spi.c:201
STD_RETURN_TYPE_e SPI_Lock(uint8_t spi)
Locks SPI interfaces.
Definition: spi.c:315
STD_RETURN_TYPE_e SPI_SlaveSetReceiveDataDma(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16_t *pTxBuff, uint16_t *pRxBuff, uint32_t frameLength)
Transmits and receives data on SPI with DMA.
Definition: spi.c:372
void SPI_Unlock(uint8_t spi)
Unlocks SPI interfaces.
Definition: spi.c:330
STD_RETURN_TYPE_e SPI_TransmitData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint32 frameLength)
Transmits data on SPI without DMA.
Definition: spi.c:91
void UNIT_TEST_WEAK_IMPL spiNotification(spiBASE_t *spi, uint32 flags)
Definition: spi.c:442
STD_RETURN_TYPE_e SPI_TransmitReceiveData(SPI_INTERFACE_CONFIG_s *pSpiInterface, uint16 *pTxBuff, uint16 *pRxBuff, uint32 frameLength)
Transmits and receives data on SPI without DMA.
Definition: spi.c:143
uint8_t SPI_GetSpiIndex(spiBASE_t *pNode)
Returns index of SPI node.
Definition: spi.c:455
#define SPI_FLAG_REGISTER_TRANSMISSION_ERRORS
Definition: spi.c:71
static uint32_t spi_txLastWord[DMA_NUMBER_SPI_INTERFACES]
Definition: spi.c:67
Headers for the driver for the SPI module.
SPI_BUSY_STATE_e spi_busyFlags[]
Definition: spi_cfg.c:329
const uint8_t spi_nrBusyFlags
Definition: spi_cfg.c:338
#define SPI_SPI5_INDEX
Definition: spi_cfg.h:73
#define SPI_HARDWARE_CHIP_SELECT_FIELD_POSITION
Definition: spi_cfg.h:83
#define SPI_SPI2_INDEX
Definition: spi_cfg.h:70
#define SPI_DATA_FORMAT_FIELD_POSITION
Definition: spi_cfg.h:86
@ SPI_IDLE
Definition: spi_cfg.h:125
@ SPI_BUSY
Definition: spi_cfg.h:126
#define SPI_WDEL_BIT
Definition: spi_cfg.h:80
#define SPI_TX_EMPTY_TIMEOUT_ITERATIONS
Definition: spi_cfg.h:95
#define SPI_CSHOLD_BIT
Definition: spi_cfg.h:77
@ SPI_CHIP_SELECT_SOFTWARE
Definition: spi_cfg.h:133
@ SPI_CHIP_SELECT_HARDWARE
Definition: spi_cfg.h:132
#define SPI_MAX_NUMBER_HW_CS
Definition: spi_cfg.h:98
#define SPI_SPI4_INDEX
Definition: spi_cfg.h:72
#define SPI_TX_BUFFER_EMPTY_FLAG_POSITION
Definition: spi_cfg.h:89
#define SPI_SPI1_INDEX
Definition: spi_cfg.h:69
#define SPI_PC0_CLEAR_HW_CS_MASK
Definition: spi_cfg.h:92
#define SPI_SPI3_INDEX
Definition: spi_cfg.h:71
dmaChannel_t rxChannel
Definition: dma_cfg.h:127
dmaChannel_t txChannel
Definition: dma_cfg.h:126
spiDAT1_t * pConfig
Definition: spi_cfg.h:140
SPI_CHIP_SELECT_TYPE_e csType
Definition: spi_cfg.h:144
spiBASE_t * pNode
Definition: spi_cfg.h:141
volatile uint32_t * pGioPort
Definition: spi_cfg.h:142