66 #define FS8x_IS_IN_RANGE(val, min, max) (((val) >= (min)) && ((val) <= (max)))
71 #if (FS8x_WD_TYPE == FS8x_WD_CHALLENGER)
78 static uint16_t FS8x_WD_ComputeAnswer(uint16_t token);
94 #if (FS8x_WD_TYPE == FS8x_WD_CHALLENGER)
118 static uint16_t FS8x_WD_ComputeAnswer(uint16_t token)
141 uint8_t registerAddress;
145 #if (FS8x_WD_TYPE == FS8x_WD_SIMPLE)
147 #elif (FS8x_WD_TYPE == FS8x_WD_CHALLENGER)
151 status |=
FS8x_ReadRegister(spiInterface, drvData,
true, registerAddress, &rxData);
166 #if (FS8x_WD_TYPE == FS8x_WD_SIMPLE)
169 #elif (FS8x_WD_TYPE == FS8x_WD_CHALLENGER)
173 status = FS8x_WD_ReadChallengeToken(spiInterface, drvData, &(drvData->
watchdogSeed));
188 uint16_t fs0b_write = 0;
190 uint16_t diagSafetyMask;
191 uint16_t diagSafetyValue;
192 uint8_t errorCounter;
203 if (errorCounter > 0)
215 if ((rxData.
readData & diagSafetyMask) != diagSafetyValue)
226 for (i = 0; i < 16; i++)
228 fs0b_write |= (uint16_t)(((rxData.
readData >> (15 - i)) & 1U) << i);
230 fs0b_write = ~fs0b_write;
241 #pragma diag_suppress 188
256 uint16_t shift = (uint16_t)vreg;
271 uint8_t* faultErrorCounterValue)
#define NULL
NULL definition.
fs8x_status_t FS8x_GetFaultErrorCounterValue(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData, uint8_t *faultErrorCounterValue)
Reads actual Fault Error Counter value.
fs8x_status_t FS8x_WD_Refresh(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData)
Performs the watchdog refresh.
fs8x_status_t FS8x_WriteRegister(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, bool isFailSafe, uint8_t address, uint16_t writeData)
Sends write command to the FS8x.
fs8x_status_t FS8x_WD_ChangeSeed(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData, uint16_t wdSeed)
Changes seed of LFSR used for watchdog.
fs8x_status_t FS8x_FS0B_Release(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData)
FS0B release routine.
fs8x_status_t FS8x_SetRegulatorState(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData, fs8x_reg_output_t vreg, bool enable)
Sets state (enable/disable) of the selected voltage regulator.
fs8x_status_t FS8x_ReadRegister(SPI_INTERFACE_CONFIG_s *pSpiInterface, fs8x_drv_data_t *drvData, bool isFailSafe, uint8_t address, fs8x_rx_frame_t *rxData)
Performs a read from a single FS8x register.
fs8x_status_t FS8x_SwitchAMUXchannel(SPI_INTERFACE_CONFIG_s *spiInterface, fs8x_drv_data_t *drvData, fs8x_amux_selection_t channelSelection)
Switches a desired channel to the AMUX pin.
fs8x_status_t
Status return codes.
fs8x_reg_output_t
Voltage outputs. Can be used with function FS8x_SetRegulatorState().
#define FS8x_IS_IN_RANGE(val, min, max)
Returns true if value VAL is in the range defined by MIN and MAX values (range includes the border va...
Assertion macro definition, for debugging purposes.
#define FS_ASSERT(x)
Assert macro for the SBC.
Driver common structures, enums, macros and configuration values.
#define FS8x_BO_GET_REG_VALUE(value, mask, shift)
Macro for getting value from register.
This file contains functions for SPI/I2C communication.
#define FS8X_FS_ABIST1_OK_PASS
#define FS8X_FS_ABIST2_OK_MASK
#define FS8X_FS_LBIST_OK_MASK
#define FS8X_FS_WD_ANSWER_ADDR
#define FS8X_FS_RELEASE_FS0B_ADDR
#define FS8X_FS_I_FLT_ERR_CNT_SHIFT
#define FS8X_FS_I_FLT_ERR_CNT_MASK
#define FS8X_M_REG_CTRL1_ADDR
#define FS8X_FS_WD_SEED_ADDR
#define FS8X_FS_ABIST2_OK_PASS
#define FS8X_FS_I_FSSM_ADDR
#define FS8X_FS_DIAG_SAFETY_ADDR
#define FS8X_M_AMUX_RESERVED
#define FS8X_FS_ABIST1_OK_MASK
#define FS8X_FS_LBIST_OK_PASS
This data structure is used by the FS8x driver (this is the first parameter of most the FS8x function...
uint16_t watchdogSeed
Actual watchdog seed value. See FS8x_WD_ChangeSeed() for details.
Structure representing received data frame.
uint16_t readData
Content of a read register.