Altium

Design Rule Verification Report

Date: 2023-01-12
Time: 18:03:13
Elapsed Time: 00:00:04
Filename: C:\Users\schwarz\AppData\Local\TempReleases\Snapshot\2\foxbms2-interface-mc33664.PcbDoc
Warnings: 0
Rule Violations: 0
Waived Violations: 1

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=1.3mm) (InNetClass('TPL_2')),(Not InNetClass('TPL_2')) 0
Clearance Constraint (Gap=1.3mm) (InNetClass('ALARM_1')),(Not InNetClass('ALARM_1')) 0
Clearance Constraint (Gap=1.3mm) (InNetClass('ALARM_2')),(Not InNetClass('ALARM_2')) 0
Clearance Constraint (Gap=0.102mm) (All),(All) 0
Clearance Constraint (Gap=1.3mm) (InNetClass('TPL_1')),(Not InNetClass('TPL_1')) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Creepage Distance Constraint =(12.5mm) (InNetClass('TPL_2')),(Not InNetClass('TPL_2')) 0
Creepage Distance Constraint =(12.5mm) (InNetClass('TPL_1')),(Not InNetClass('TPL_1')) 0
Creepage Distance Constraint =(12.5mm) (InNetClass('ALARM_2')),(Not InNetClass('ALARM_2')) 0
Creepage Distance Constraint =(12.5mm) (InNetClass('ALARM_1')),(Not InNetClass('ALARM_1')) 0
Width Constraint (Min=0.102mm) (Max=1.524mm) (Preferred=0.152mm) (All) 0
Routing Via (Templates Used To Check Via: 0.3mm_tented) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.152mm) (Max=0.254mm) (Prefered=0.222mm) and Width Constraints (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) (All) 0
SMD To Corner (Distance=0.102mm) (All) 0
SMD Entry (Side = Allowed) (Corner = Allowed) (Any Angle = Not Allowed) (Ignore First Corner = Allowed) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.102mm) (All) 0
Hole Size Constraint (Min=0.2mm) (Max=5.994mm) (All) 0
Hole To Hole Clearance (Gap=0.152mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.102mm) (IsPad),(All) 0
Silk to Silk (Clearance=0.254mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (All) 0
Room TPL-transceiver-2 (Bounding Region = (66.834mm, 73.343mm, 82.391mm, 101.759mm) (InComponentClass('TPL-transceiver-2')) 0
Room digital-isolator-alarm1 (Bounding Region = (44.133mm, 43.656mm, 60.166mm, 73.184mm) (InComponentClass('digital-isolator-alarm1')) 0
Room digital-isolator-alarm2 (Bounding Region = (77.311mm, 43.656mm, 93.345mm, 73.184mm) (InComponentClass('digital-isolator-alarm2')) 0
Room TPL-transformer-2 (Bounding Region = (60.801mm, 43.656mm, 76.676mm, 73.184mm) (InComponentClass('TPL-transformer-2')) 0
Room TPL-transceiver-1 (Bounding Region = (33.655mm, 73.343mm, 49.212mm, 101.759mm) (InComponentClass('TPL-transceiver-1')) 0
Room TPL-transformer-1 (Bounding Region = (27.622mm, 43.656mm, 43.498mm, 73.184mm) (InComponentClass('TPL-transformer-1')) 0
Component Clearance Constraint ( Horizontal Gap = 0.2mm, Vertical Gap = 0.2mm ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = -1mm, Vertical Gap = -1mm ) (InComponent('MP100')),(All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 0

Waived Violations Count
Silk to Silk (Clearance=0.254mm) (All),(All) 1
Total 1

Rule Violations

Waived Violations

Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.201mm < 0.254mm) Between Text "TP_EN1" (16.232mm,78.051mm) on Top Overlay And Text "TP_SPI1.SIMO0" (14.81mm,78.05mm) on Top Overlay Silk Text to Silk Clearance [0.201mm]
Waived by Sebastian Wacker at 2021-09-16 11:58:20

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