foxBMS  1.4.1
The foxBMS Battery Management System API Documentation
fstartup.c
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41 
42 /**
43  * @file fstartup.c
44  * @author foxBMS Team
45  * @date 2020-07-09 (date of creation)
46  * @updated 2022-10-27 (date of last update)
47  * @version v1.4.1
48  * @ingroup GENERAL
49  * @prefix STU
50  *
51  * @brief Startup code
52  *
53  * @details This file contains startup code mostly identical to TI code.
54  * Function "_c_int00" is extracted from file "HL_sys_startup.c" and
55  * function "STU_GetResetSourceWithoutFlagReset" is taken from file
56  * "HL_system.c". Both files are generated by TI HALCoGen under the
57  * following license:
58  *
59  * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
60  *
61  * Redistribution and use in source and binary forms, with or without
62  * modification, are permitted provided that the following conditions
63  * are met:
64  *
65  * Redistributions of source code must retain the above copyright
66  * notice, this list of conditions and the following disclaimer.
67  *
68  * Redistributions in binary form must reproduce the above copyright
69  * notice, this list of conditions and the following disclaimer in the
70  * documentation and/or other materials provided with the
71  * distribution.
72  *
73  * Neither the name of Texas Instruments Incorporated nor the names of
74  * its contributors may be used to endorse or promote products derived
75  * from this software without specific prior written permission.
76  *
77  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
78  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
79  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
80  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
81  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
82  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
83  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
84  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
85  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
86  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
87  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88  *
89  */
90 
91 /*========== Includes =======================================================*/
92 /* clang-format off */
93 /* keep include order as suggested by TI HALCoGen */
94 #include "HL_sys_common.h"
95 #include "HL_system.h"
96 #include "HL_sys_vim.h"
97 #include "HL_sys_core.h"
98 #include "HL_esm.h"
99 #include "HL_sys_mpu.h"
100 #include "HL_errata_SSWF021_45.h"
101 
102 #include "fassert.h"
103 #include "fstartup.h"
104 #include "main.h"
105 
106 #include <stdlib.h>
107 /* clang-format on */
108 
109 /*========== Macros and Definitions =========================================*/
110 /** number of retries for the PLL to come up */
111 #define STU_PLL_RETRIES (5u)
112 
113 /*========== Static Constant and Variable Definitions =======================*/
114 
115 /*========== Extern Constant and Variable Definitions =======================*/
116 
117 /*========== Static Function Prototypes =====================================*/
118 /**
119  * @brief Handler for a failed PLL lock
120  * @details If the PLL can not be locked the, this function shall be called to
121  * ensure that the application no further starts.
122  * @return This function never returns */
123 static void STU_HandlePllLockFail(void);
124 
125 /**
126  * @brief Get reset flag
127  * @details Get reset source without reseting respective the flag in SYSESR
128  * register
129  * @return returns reset reason
130  */
131 static resetSource_t STU_GetResetSourceWithoutFlagReset(void);
132 
133 /*========== Static Function Implementations ================================*/
134 
137 }
139  register resetSource_t rst_source;
140 
141  if ((SYS_EXCEPTION & (uint32)POWERON_RESET) != 0U) {
142  /* power-on reset condition */
143  rst_source = POWERON_RESET;
144  } else if ((SYS_EXCEPTION & (uint32)EXT_RESET) != 0U) {
145  /*** Check for other causes of EXT_RESET that would take precedence **/
146  if ((SYS_EXCEPTION & (uint32)OSC_FAILURE_RESET) != 0U) {
147  /* Reset caused due to oscillator failure. Add user code here to handle oscillator failure */
148  rst_source = OSC_FAILURE_RESET;
149  } else if ((SYS_EXCEPTION & (uint32)WATCHDOG_RESET) != 0U) {
150  /* Reset caused due watchdog violation */
151  rst_source = WATCHDOG_RESET;
152  } else if ((SYS_EXCEPTION & (uint32)WATCHDOG2_RESET) != 0U) {
153  /* Reset caused due watchdog violation */
154  rst_source = WATCHDOG2_RESET;
155  } else if ((SYS_EXCEPTION & (uint32)SW_RESET) != 0U) {
156  /* Reset caused due to software reset. */
157  rst_source = SW_RESET;
158  } else {
159  /* Reset caused due to External reset. */
160  rst_source = EXT_RESET;
161  }
162  } else if ((SYS_EXCEPTION & (uint32)DEBUG_RESET) != 0U) {
163  /* Reset caused due Debug reset request */
164  rst_source = DEBUG_RESET;
165  } else if ((SYS_EXCEPTION & (uint32)CPU0_RESET) != 0U) {
166  /* Reset caused due to CPU0 reset. CPU reset can be caused by CPU self-test completion, or by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
167  rst_source = CPU0_RESET;
168  } else {
169  /* No_reset occurred. */
170  rst_source = NO_RESET;
171  }
172  return rst_source;
173 }
174 
175 /*========== Extern Function Implementations ================================*/
176 /** system entry point */
177 #pragma CODE_STATE(_c_int00, 32)
178 #pragma INTERRUPT(_c_int00, RESET)
179 /* SourceId : STARTUP_SourceId_001 */
180 /* DesignId : STARTUP_DesignId_001 */
181 /* Requirements : HL_CONQ_STARTUP_SR1 */
182 void _c_int00(void) {
183  register resetSource_t rstSrc;
184 
185  /* Initialize Core Registers to avoid CCM Error */
186  _coreInitRegisters_();
187 
188  /* Initialize Stack Pointers */
189  _coreInitStackPointer_();
190 
191  /* Reset handler: the following instructions read from the system exception status register
192  * to identify the cause of the CPU reset.
193  */
194  /* Changed in comparison to TI _c_int00 implementation. Readout flags but do NOT clear them! */
196  switch (rstSrc) {
197  case POWERON_RESET:
198  /* Initialize L2RAM to avoid ECC errors right after power on */
199  _memInit_();
200 
201  /* Add condition to check whether PLL can be started successfully */
202  if (_errata_SSWF021_45_both_plls(STU_PLL_RETRIES) != 0U) {
203  /* Put system in a safe state */
205  }
206 
207  case DEBUG_RESET:
208  case EXT_RESET:
209 
210  /* Initialize L2RAM to avoid ECC errors right after power on */
211  if (rstSrc != POWERON_RESET) {
212  _memInit_();
213  }
214 
215  /* Enable CPU Event Export */
216  /* This allows the CPU to signal any single-bit or double-bit errors detected
217  * by its ECC logic for accesses to program flash or data RAM.
218  */
219  _coreEnableEventBusExport_();
220 
221  /* Check if there were ESM group3 errors during power-up.
222  * These could occur during eFuse auto-load or during reads from flash OTP
223  * during power-up. Device operation is not reliable and not recommended
224  * in this case. */
225  if ((esmREG->SR1[2]) != 0U) {
226  esmGroup3Notification(esmREG, esmREG->SR1[2]);
227  }
228 
229  /* Initialize System - Clock, Flash settings with Efuse self check */
230  systemInit();
231 
232  /* Enable IRQ offset via Vic controller */
233  _coreEnableIrqVicOffset_();
234 
235  /* Initialize VIM table */
236  vimInit();
237 
238  /* Configure system response to error conditions signaled to the ESM group1 */
239  /* This function can be configured from the ESM tab of HALCoGen */
240  esmInit();
241  break;
242 
243  case OSC_FAILURE_RESET:
244  break;
245 
246  case WATCHDOG_RESET:
247  case WATCHDOG2_RESET:
248 
249  break;
250 
251  case CPU0_RESET:
252  /* Enable CPU Event Export */
253  /* This allows the CPU to signal any single-bit or double-bit errors detected
254  * by its ECC logic for accesses to program flash or data RAM.
255  */
256  _coreEnableEventBusExport_();
257  break;
258 
259  case SW_RESET:
260  break;
261 
262  default:
263  break;
264  }
265 
266  _mpuInit_();
267 
268  /* initialize global variable and constructors */
269  __TI_auto_init();
270 
271  /* call the application */
272  main();
273 
274  /* AXIVION Next Codeline Style MisraC2012-21.8: exit is called as in generated code by TI */
275  exit(0);
276 }
277 
278 /*========== Externalized Static Function Implementations (Unit Test) =======*/
Assert macro implementation.
#define FAS_ASSERT(x)
Assertion macro that asserts that x is true.
Definition: fassert.h:252
#define FAS_TRAP
Define that evaluates to essential boolean false thus tripping an assert.
Definition: fassert.h:126
void _c_int00(void)
Startup Routine.
Definition: fstartup.c:182
#define STU_PLL_RETRIES
Definition: fstartup.c:111
static void STU_HandlePllLockFail(void)
Handler for a failed PLL lock.
Definition: fstartup.c:135
static resetSource_t STU_GetResetSourceWithoutFlagReset(void)
Get reset flag.
Definition: fstartup.c:138
Startup code.
void __TI_auto_init(void)
initialize global variable and constructors
Main function header.
int main(void)
main function of foxBMS
Definition: main.c:90