foxBMS - Unit Tests  1.4.1
The foxBMS Unit Tests API Documentation
test_ltc_afe_dma.c
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41 
42 /**
43  * @file test_ltc_afe_dma.c
44  * @author foxBMS Team
45  * @date 2020-06-10 (date of creation)
46  * @updated 2022-10-27 (date of last update)
47  * @version v1.4.1
48  * @ingroup UNIT_TEST_IMPLEMENTATION
49  * @prefix TEST
50  *
51  * @brief Test of the ltc_afe_dma.c module in ltc
52  *
53  */
54 
55 /*========== Includes =======================================================*/
56 #include "unity.h"
57 #include "MockHL_sys_dma.h"
58 #include "Mockfassert.h"
59 #include "Mockio.h"
60 #include "Mockltc.h"
61 #include "Mockspi.h"
62 
63 #include "ltc_cfg.h"
64 #include "spi_cfg.h"
65 
66 #include "ltc_afe_dma.h"
67 
68 /*========== Definitions and Implementations for Unit Test ==================*/
71 
72 #define DMA_REQ_LINE_SPI1_TX (DMA_REQ1)
73 #define DMA_REQ_LINE_SPI1_RX (DMA_REQ0)
74 #define DMA_REQ_LINE_SPI2_TX (DMA_REQ3)
75 #define DMA_REQ_LINE_SPI2_RX (DMA_REQ2)
76 #define DMA_REQ_LINE_SPI3_TX (DMA_REQ15)
77 #define DMA_REQ_LINE_SPI3_RX (DMA_REQ14)
78 
79 #define BIG_ENDIAN (3u)
80 #define ELEMENT_COUNT (1u)
81 #define DMAREQEN_BIT (0x10000u)
82 #define SPIEN_BIT (0x1000000u)
83 
84 #define DMA_REQ_LINE_TX (DMA_REQ_LINE_SPI1_TX)
85 #define DMA_REQ_LINE_RX (DMA_REQ_LINE_SPI1_RX)
86 
88  .timer = 0,
89  .statereq = LTC_STATE_NO_REQUEST,
91  .substate = 0,
92  .laststate = LTC_STATEMACH_UNINITIALIZED,
93  .lastsubstate = 0,
94  .adcModereq = LTC_ADCMODE_FAST_DCP0,
95  .adcMode = LTC_ADCMODE_FAST_DCP0,
96  .adcMeasChreq = LTC_ADCMEAS_UNDEFINED,
97  .adcMeasCh = LTC_ADCMEAS_UNDEFINED,
98  .numberOfMeasuredMux = 32,
99  .triggerentry = 0,
100  .ErrRetryCounter = 0,
101  .ErrRequestCounter = 0,
102  .VoltageSampleTime = 0,
103  .muxSampleTime = 0,
104  .commandDataTransferTime = 3,
105  .commandTransferTime = 3,
106  .gpioClocksTransferTime = 3,
107  .muxmeas_seqptr = NULL_PTR,
108  .muxmeas_seqendptr = NULL_PTR,
109  .muxmeas_nr_end = 0,
110  .first_measurement_made = false,
111  .ltc_muxcycle_finished = STD_NOT_OK,
112  .check_spi_flag = STD_NOT_OK,
113  .balance_control_done = STD_NOT_OK,
114  .transmit_ongoing = false,
115  .dummyByte_ongoing = STD_NOT_OK,
116 };
117 
118 /* - configuring dma control packets */
120  .SADD = 0u, /* source address */
121  .DADD = 0u, /* destination address */
122  .CHCTRL = 0U, /* channel control */
123  .FRCNT = LTC_N_BYTES_FOR_DATA_TRANSMISSION, /* frame count */
124  .ELCNT = ELEMENT_COUNT, /* element count */
125  .ELDOFFSET = 0U, /* element destination offset */
126  .ELSOFFSET = 0U, /* element destination offset */
127  .FRDOFFSET = 0U, /* frame destination offset */
128  .FRSOFFSET = 0U, /* frame destination offset */
129  .PORTASGN = PORTA_READ_PORTB_WRITE, /* port assignment */
130  .RDSIZE = ACCESS_8_BIT, /* read size */
131  .WRSIZE = ACCESS_8_BIT, /* write size */
132  .TTYPE = FRAME_TRANSFER, /* transfer type */
133  .ADDMODERD = ADDR_INC1, /* address mode read */
134  .ADDMODEWR = ADDR_FIXED, /* address mode write */
135  .AUTOINIT = AUTOINIT_OFF, /* autoinit */
136 };
137 
139  .SADD = 0u, /* source address */
140  .DADD = 0u, /* destination address */
141  .CHCTRL = 0U, /* channel control */
142  .FRCNT = LTC_N_BYTES_FOR_DATA_TRANSMISSION, /* frame count */
143  .ELCNT = ELEMENT_COUNT, /* element count */
144  .ELDOFFSET = 0U, /* element destination offset */
145  .ELSOFFSET = 0U, /* element destination offset */
146  .FRDOFFSET = 0U, /* frame destination offset */
147  .FRSOFFSET = 0U, /* frame destination offset */
148  .PORTASGN = PORTB_READ_PORTA_WRITE, /* port assignment */
149  .RDSIZE = ACCESS_8_BIT, /* read size */
150  .WRSIZE = ACCESS_8_BIT, /* write size */
151  .TTYPE = FRAME_TRANSFER, /* transfer type */
152  .ADDMODERD = ADDR_FIXED, /* address mode read */
153  .ADDMODEWR = ADDR_INC1, /* address mode write */
154  .AUTOINIT = AUTOINIT_OFF, /* autoinit */
155 };
156 
157 /*========== Setup and Teardown =============================================*/
158 void setUp(void) {
159 }
160 
161 void tearDown(void) {
162 }
163 
164 /*========== Test Cases =====================================================*/
165 
166 void testDummy(void) {
167 }
@ STD_NOT_OK
Definition: fstd_types.h:83
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:76
Headers for the driver for the DMA module for the LTC.
Headers for the configuration for the LTC monitoring chip.
#define LTC_N_BYTES_FOR_DATA_TRANSMISSION
Definition: ltc_cfg.h:78
@ LTC_STATE_NO_REQUEST
Definition: ltc_defs.h:391
@ LTC_STATEMACH_UNINITIALIZED
Definition: ltc_defs.h:120
@ LTC_ADCMEAS_UNDEFINED
Definition: ltc_defs.h:105
@ LTC_ADCMODE_FAST_DCP0
Definition: ltc_defs.h:95
Headers for the configuration for the SPI module.
uint16_t timer
Definition: ltc_defs.h:520
uint8_t ltc_RXPECbuffer[LTC_N_BYTES_FOR_DATA_TRANSMISSION]
uint8_t ltc_TXPECbuffer[LTC_N_BYTES_FOR_DATA_TRANSMISSION]
g_dmaCTRL afe_ltcDmaControlPacketTx
void testDummy(void)
void setUp(void)
void tearDown(void)
LTC_STATE_s ltc_stateBase
#define ELEMENT_COUNT
g_dmaCTRL afe_ltcDmaControlPacketRx