test_ltc_afe_dma.c

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/**
 * @file    test_ltc_afe_dma.c
 * @author  foxBMS Team
 * @date    2020-06-10 (date of creation)
 * @updated 2023-10-12 (date of last update)
 * @version v1.6.0
 * @ingroup UNIT_TEST_IMPLEMENTATION
 * @prefix  TEST
 *
 * @brief   Test of the ltc_afe_dma.c module in ltc
 *
 */
 
/*========== Includes =======================================================*/
#include "unity.h"
#include "MockHL_sys_dma.h"
#include "Mockfassert.h"
#include "Mockio.h"
#include "Mockltc.h"
#include "Mockspi.h"
 
#include "ltc_cfg.h"
#include "spi_cfg.h"
 
#include "ltc_afe_dma.h"
 
#include <stdbool.h>
#include <stdint.h>
 
/*========== Unit Testing Framework Directives ==============================*/
TEST_SOURCE_FILE("ltc_afe_dma.c")
 
TEST_INCLUDE_PATH("../../src/app/driver/afe/api")
TEST_INCLUDE_PATH("../../src/app/driver/afe/ltc/common")
TEST_INCLUDE_PATH("../../src/app/driver/afe/ltc/common/config")
TEST_INCLUDE_PATH("../../src/app/driver/config")
TEST_INCLUDE_PATH("../../src/app/driver/io")
TEST_INCLUDE_PATH("../../src/app/driver/spi")
 
/*========== Definitions and Implementations for Unit Test ==================*/
uint8_t ltc_RXPECbuffer[LTC_N_BYTES_FOR_DATA_TRANSMISSION] = {0};
uint8_t ltc_TXPECbuffer[LTC_N_BYTES_FOR_DATA_TRANSMISSION] = {0};
 
#define DMA_REQ_LINE_SPI1_TX (DMA_REQ1)
#define DMA_REQ_LINE_SPI1_RX (DMA_REQ0)
#define DMA_REQ_LINE_SPI2_TX (DMA_REQ3)
#define DMA_REQ_LINE_SPI2_RX (DMA_REQ2)
#define DMA_REQ_LINE_SPI3_TX (DMA_REQ15)
#define DMA_REQ_LINE_SPI3_RX (DMA_REQ14)
 
#define BIG_ENDIAN    (3u)
#define ELEMENT_COUNT (1u)
#define DMAREQEN_BIT  (0x10000u)
#define SPIEN_BIT     (0x1000000u)
 
#define DMA_REQ_LINE_TX (DMA_REQ_LINE_SPI1_TX)
#define DMA_REQ_LINE_RX (DMA_REQ_LINE_SPI1_RX)
 
LTC_STATE_s ltc_stateBase = {
    .timer                   = 0,
    .statereq                = LTC_STATE_NO_REQUEST,
    .state                   = LTC_STATEMACH_UNINITIALIZED,
    .substate                = 0,
    .laststate               = LTC_STATEMACH_UNINITIALIZED,
    .lastsubstate            = 0,
    .adcModereq              = LTC_ADCMODE_FAST_DCP0,
    .adcMode                 = LTC_ADCMODE_FAST_DCP0,
    .adcMeasChreq            = LTC_ADCMEAS_UNDEFINED,
    .adcMeasCh               = LTC_ADCMEAS_UNDEFINED,
    .numberOfMeasuredMux     = 32,
    .triggerentry            = 0,
    .ErrRetryCounter         = 0,
    .ErrRequestCounter       = 0,
    .VoltageSampleTime       = 0,
    .muxSampleTime           = 0,
    .commandDataTransferTime = 3,
    .commandTransferTime     = 3,
    .gpioClocksTransferTime  = 3,
    .muxmeas_seqptr          = NULL_PTR,
    .muxmeas_seqendptr       = NULL_PTR,
    .muxmeas_nr_end          = 0,
    .first_measurement_made  = false,
    .ltc_muxcycle_finished   = STD_NOT_OK,
    .check_spi_flag          = STD_NOT_OK,
    .balance_control_done    = STD_NOT_OK,
    .transmit_ongoing        = false,
    .dummyByte_ongoing       = STD_NOT_OK,
};
 
/* - configuring dma control packets   */
g_dmaCTRL afe_ltcDmaControlPacketTx = {
    .SADD      = 0u,                                /* source address             */
    .DADD      = 0u,                                /* destination  address       */
    .CHCTRL    = 0U,                                /* channel control            */
    .FRCNT     = LTC_N_BYTES_FOR_DATA_TRANSMISSION, /* frame count                */
    .ELCNT     = ELEMENT_COUNT,                     /* element count              */
    .ELDOFFSET = 0U,                                /* element destination offset */
    .ELSOFFSET = 0U,                                /* element destination offset */
    .FRDOFFSET = 0U,                                /* frame destination offset   */
    .FRSOFFSET = 0U,                                /* frame destination offset   */
    .PORTASGN  = PORTA_READ_PORTB_WRITE,            /* port assignment            */
    .RDSIZE    = ACCESS_8_BIT,                      /* read size                  */
    .WRSIZE    = ACCESS_8_BIT,                      /* write size                 */
    .TTYPE     = FRAME_TRANSFER,                    /* transfer type              */
    .ADDMODERD = ADDR_INC1,                         /* address mode read          */
    .ADDMODEWR = ADDR_FIXED,                        /* address mode write         */
    .AUTOINIT  = AUTOINIT_OFF,                      /* autoinit                   */
};
 
g_dmaCTRL afe_ltcDmaControlPacketRx = {
    .SADD      = 0u,                                /* source address             */
    .DADD      = 0u,                                /* destination  address       */
    .CHCTRL    = 0U,                                /* channel control            */
    .FRCNT     = LTC_N_BYTES_FOR_DATA_TRANSMISSION, /* frame count                */
    .ELCNT     = ELEMENT_COUNT,                     /* element count              */
    .ELDOFFSET = 0U,                                /* element destination offset */
    .ELSOFFSET = 0U,                                /* element destination offset */
    .FRDOFFSET = 0U,                                /* frame destination offset   */
    .FRSOFFSET = 0U,                                /* frame destination offset   */
    .PORTASGN  = PORTB_READ_PORTA_WRITE,            /* port assignment            */
    .RDSIZE    = ACCESS_8_BIT,                      /* read size                  */
    .WRSIZE    = ACCESS_8_BIT,                      /* write size                 */
    .TTYPE     = FRAME_TRANSFER,                    /* transfer type              */
    .ADDMODERD = ADDR_FIXED,                        /* address mode read          */
    .ADDMODEWR = ADDR_INC1,                         /* address mode write         */
    .AUTOINIT  = AUTOINIT_OFF,                      /* autoinit                   */
};
 
/*========== Setup and Teardown =============================================*/
void setUp(void) {
}
 
void tearDown(void) {
}
 
/*========== Test Cases =====================================================*/
 
void testDummy(void) {
}