foxBMS - Unit Tests  1.4.1
The foxBMS Unit Tests API Documentation
mxm_register_map.h
Go to the documentation of this file.
1 /**
2  *
3  * @copyright © 2010 - 2022, Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright notice, this
12  * list of conditions and the following disclaimer.
13  *
14  * 2. Redistributions in binary form must reproduce the above copyright notice,
15  * this list of conditions and the following disclaimer in the documentation
16  * and/or other materials provided with the distribution.
17  *
18  * 3. Neither the name of the copyright holder nor the names of its
19  * contributors may be used to endorse or promote products derived from
20  * this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * We kindly request you to use one or more of the following phrases to refer to
34  * foxBMS in your hardware, software, documentation or advertising materials:
35  *
36  * - ″This product uses parts of foxBMS®″
37  * - ″This product includes parts of foxBMS®″
38  * - ″This product is derived from foxBMS®″
39  *
40  */
41 
42 /**
43  * @file mxm_register_map.h
44  * @author foxBMS Team
45  * @date 2019-03-05 (date of creation)
46  * @updated 2022-10-27 (date of last update)
47  * @version v1.4.1
48  * @ingroup DRIVERS
49  * @prefix MXM
50  *
51  * @brief Register map of the MAX1785x monitoring IC
52  *
53  * @details Register map with named registers of the monitoring ICs
54  * MAX17852 and MAX17853 by Maxim Integrated
55  *
56  */
57 
58 #ifndef FOXBMS__MXM_REGISTER_MAP_H_
59 #define FOXBMS__MXM_REGISTER_MAP_H_
60 
61 /*========== Includes =======================================================*/
62 #include "general.h"
63 
64 /*========== Macros and Definitions =========================================*/
65 /**
66  * @brief MAX1785x register names
67  * @details Register names and addresses of the monitoring ICs MAX17852 and
68  * MAX17853. Please note that the MAX17853 only supports a subset
69  * of these register values.
70  */
71 typedef enum {
72  MXM_REG_VERSION = 0x00u, /*!< VERSION is a read only
73  * accessible register which returns information on the device */
74  MXM_REG_ADDRESS = 0x01u, /*!< ADDRESS is a read and write
75  * accessible register which sets the first, last, and device address
76  * used by a device in a UART chain (UARTSEL=1). This register has no
77  * effect on a device operating in SPI mode (UARTSEL=0). */
78  MXM_REG_STATUS1 = 0x02u, /*!< STATUS1 is a read and write
79  * accessible register which relates the current status of the device.
80  * STATUS1 also contains summary information on STATUS2, STATUS3, and
81  * FMEA registers, and other selected registers indicating if additional
82  * read back checks are required. */
83  MXM_REG_STATUS2 = 0x03u, /*!< STATUS2 is a read and write
84  * accessible register which contains summary information on alerts
85  * related to interface and communication faults. */
86  MXM_REG_STATUS3 = 0x04u, /*!< STATUS3 is a read and write
87  * accessible register which contains summary information on alerts
88  * related to automated cell balancing operations. */
89  MXM_REG_FMEA1 = 0x05u, /*!< FMEA1 is a read and write
90  * accessible register which relates current information on possible
91  * fault conditions. */
92  MXM_REG_FMEA2 = 0x06u, /*!< FMEA2 is a read and write
93  * accessible register which relates current information on possible
94  * fault conditions. */
95  MXM_REG_ALRTSUM = 0x07u, /*!< ALRTSUM is a read accessible
96  * register which relates added, detailed information on the current
97  * states of the device, breaking out several summary bits in STATUS1. */
98  MXM_REG_ALRTOVCELL = 0x08u, /*!< ALRTOVCELL is a read
99  * accessible register which relates current information on cell over
100  * voltage fault alerts based on ADC measurements. */
101  MXM_REG_ALRTUVCELL = 0x09u, /*!< ALRTUVCELL is a read
102  * accessible register which relates current information on cell under
103  * voltage fault alerts based on ADC measurements. */
104  MXM_REG_MINMAXCELL = 0x0Au, /*!< MINMAX is a read accessible
105  * register which relates the cell locations with the highest and lowest
106  * values measured. */
107  MXM_REG_ALRTAUXPRTCT = 0x0Bu, /*!< ALRTAUXPRTCT is a read
108  * accessible register which relates current information on auxiliary
109  * input protection fault alerts. */
110  MXM_REG_ALRTAUXOV = 0x0Cu, /*!< ALRTAUXOV is a read
111  * accessible register which relates current information on auxiliary
112  * over voltage (cold) fault alerts. */
113  MXM_REG_ALRTAUXUV = 0x0Du, /*!< ALRTAUXUV is a read accessible
114  * register which relates current information on auxiliary under voltage
115  * fault (hot) alerts. */
116  MXM_REG_ALRTCOMPOV = 0x0Eu, /*!< ALRTCOMPOV is a read accessible
117  * register which relates current information on cell over voltage fault
118  * alerts based on the redundant comparator. */
119  MXM_REG_ALRTCOMPUV = 0x0Fu, /*!< ALRTCOMPUV is a read accessible
120  * register which relates current information on cell under voltage fault
121  * alerts based on the redundant comparator. */
122  MXM_REG_ALRTCOMPAUXOV = 0x10u, /*!< ALRTCOMPAUXOV is a read
123  * accessible register which relates current information on auxiliary over
124  * voltage fault (cold) alerts based on the redundant comparator. */
125  MXM_REG_ALRTCOMPAUXUV = 0x11u, /*!< ALRTCOMPAUXUV is a read
126  * accessible register which relates current information on auxiliary under
127  * voltage fault (hot) alerts based on the redundant comparator. */
128  MXM_REG_ALRTBALSW = 0x12u, /*!< ALRTBALSW is a read accessible
129  * register which relates current summary information on balancing switch
130  * fault alerts. */
131  MXM_REG_SWACTION = 0x13u, /*!< SWACTION is a read and write
132  * accessible register which contains bits allowing software exit and
133  * reset requests. These requests are not recommended for general use,
134  * but may be of use in case of error. */
135  MXM_REG_DEVCFG1 = 0x14u, /*!< DEVCFG1 is a read and write
136  * accessible register which governs the configuration of the device
137  * interface operation. */
138  MXM_REG_DEVCFG2 = 0x15u, /*!< DEVCFG2 is a read and write
139  * accessible register which governs the configuration of the device
140  * filtering, several top level diagnostic modes, and timeout monitors. */
141  MXM_REG_AUXGPIOCFG = 0x16u, /*!< AUXGPIOCFG is a read and write
142  * accessible register which governs the configuration of the AUX/GPIO
143  * multifunction pins. */
144  MXM_REG_GPIOCFG = 0x17u, /*!< GPIOCFG is a read and write
145  * accessible register which governs the output state of GPIO outputs and
146  * reads back the input state of GPIO inputs. */
147  MXM_REG_PACKCFG = 0x18u, /*!< PACKCFG is a read and write
148  * accessible register which configures the part such that the top most
149  * cell and block used in the application is known. Details of Flex Pack
150  * applications are also configured within this register. */
151  MXM_REG_ALRTIRQEN = 0x19u, /*!< ALRTIRQEN is a read and write
152  * accessible register which selects which STATS1 alerts trigger interrupts
153  * via the ALERT interface port(s), and are included in the DCByte and
154  * Alert Packet (UART) or ALERT bit (SPI) notifications. Note the information
155  * in the STATUS1 register itself (or any component terms rolled up into
156  * STATUS1) is not masked/disabled by these settings, allowing the
157  * underlying data to always be available via STATUS1 readback. */
158  MXM_REG_ALRTOVEN = 0x1Au, /*!< ALRTOVEN is a read and write
159  * accessible register which enables over voltage fault checks on selected
160  * input channels during scans using either the ADC or Comparator. */
161  MXM_REG_ALRTUVEN = 0x1Bu, /*!< ALRTUVEN is a read and write
162  * accessible register which enables under voltage fault checks on selected
163  * input channels during scans using either the ADC or Comparator. */
164  MXM_REG_ALRTAUXOVEN = 0x1Cu, /*!< ALRTAUXOVEN is a read and write
165  * accessible register which enables auxiliary over voltage (cold) fault
166  * checks on selected Auxiliary channels during scans using either the
167  * ADC or Comparator. */
168  MXM_REG_ALRTAUXUVEN = 0x1Du, /*!< ALRTAUXUVEN is a read and write
169  * accessible register which enables auxiliary under voltage (hot) fault
170  * checks on selected Auxiliary channels using either the
171  * ADC or Comparator. */
172  MXM_REG_ALRTCALTST = 0x1Eu, /*!< ALRTCALTST is a read and write
173  * accessible register which allows the user to force Calibration alerts
174  * to test readback and interrupt logic. The forced alert(s) will remain
175  * forced until this register is written back to zeros (assuming the
176  * existing calibration data is within range) */
177  MXM_REG_OVTHCLR = 0x1Fu, /*!< OVTHCLR is a read and write
178  * accessible register which selects the cell over voltage alert
179  * clear threshold used with unipolar ADC measurements. */
180  MXM_REG_OVTHSET = 0x20u, /*!< OVTHSET is a read and write
181  * accessible register which selects the cell over voltage alert set
182  * threshold used with unipolar ADC measurements. */
183  MXM_REG_UVTHCLR = 0x21u, /*!< UVTHCLR is a read and write
184  * accessible register which selects the cell under voltage alert clear
185  * threshold used with unipolar ADC measurements. */
186  MXM_REG_UVTHSET = 0x22u, /*!< UVTHSET is a read and write
187  * accessible register which selects the cell under voltage alert set
188  * threshold used with unipolar ADC measurements. */
189  MXM_REG_MSMTCH = 0x23u, /*!< MSMTCH is a read and write
190  * accessible register which selects the cell voltage mismatch alert
191  * threshold used with ADC cell scan measurements. */
192  MXM_REG_BIPOVTHCLR = 0x24u, /*!< BIPOVTHCLR is a read and write
193  * accessible register which selects the cell over voltage alert clear
194  * threshold used with bipolar ADC measurements. */
195  MXM_REG_BIPOVTHSET = 0x25u, /*!< BIPOVTHSET is a read and write
196  * accessible register which selects the cell over voltage alert set
197  * threshold used with bipolar ADC measurements. */
198  MXM_REG_BIPUVTHCLR = 0x26u, /*!< BIPUVTHCLR is a read and write
199  * accessible register which selects the cell under voltage alert clear
200  * threshold used with bipolar ADC measurements. */
201  MXM_REG_BIPUVTHSET = 0x27u, /*!< BIPUVTHSET is a read and write
202  * accessible register which selects the cell under voltage alert set
203  * threshold used with bipolar ADC measurements. */
204  MXM_REG_BLKOVTHCLR = 0x28u, /*!< BLKOVTHCLR is a read and write
205  * accessible register which selects the block over voltage alert clear
206  * threshold used with ADC measurements. */
207  MXM_REG_BLKOVTHSET = 0x29u, /*!< BLKOVTHSET is a read and write
208  * accessible register which selects the block over voltage alert set
209  * threshold used with ADC measurements. */
210  MXM_REG_BLKUVTHCLR = 0x2Au, /*!< BLKUVTHCLR is a read and write
211  * accessible register which selects the block under voltage alert clear
212  * threshold used with ADC measurements. */
213  MXM_REG_BLKUVTHSET = 0x2Bu, /*!< BLKUVTHSET is a read and write
214  * accessible register which selects the block under voltage alert set
215  * threshold used with ADC measurements. */
216  MXM_REG_CSAOVTHCLR = 0x2Cu, /*!< MAX17852 only: CSAOVTHCLR is a
217  * read and write accessible register which selects the CSA over voltage
218  * alert clear threshold used with ADC measurements. */
219  MXM_REG_CSAOVTHSET = 0x2Du, /*!< MAX17852 only: CSAOVTHSET is a
220  * read and write accessible register which selects the CSA over voltage
221  * alert set threshold used with ADC measurements. */
222  MXM_REG_CSAUVTHCLR = 0x2Eu, /*!< MAX17852 only: CSAUVTHCLR is a
223  * read and write accessible register which selects the CSA under voltage
224  * alert clear threshold used with ADC measurements. */
225  MXM_REG_CSAUVTHSET = 0x2Fu, /*!< MAX17852 only: CSAUVTHSET is a
226  * read and write accessible register which selects the CSA under voltage
227  * alert set threshold used with ADC measurements. */
228  MXM_REG_AUXROVTHCLR = 0x30u, /*!< AUXROVTHCLR is a read and write
229  * accessible register which selects the over voltage (cold) alert
230  * clear threshold used with Ratiometric Auxiliary ADC measurements. */
231  MXM_REG_AUXROVTHSET = 0x31u, /*!< AUXROVTHSET is a read and write
232  * accessible register which selects the over voltage (cold) alert set
233  * threshold used with Ratiometric Auxiliary ADC measurements. */
234  MXM_REG_AUXRUVTHCLR = 0x32u, /*!< AUXRUVTHCLR is a read and write
235  * accessible register which selects the under voltage (hot) alert clear
236  * threshold used with Ratiometric Auxiliary ADC measurements. */
237  MXM_REG_AUXRUVTHSET = 0x33u, /*!< AUXRUVTHSET is a read and write
238  * accessible register which selects the under voltage (hot) alert set
239  * threshold used with Ratiometric Auxiliary ADC measurements. */
240  MXM_REG_AUXOVTHCLR = 0x34u, /*!< AUXOVTHCLR is a read and write
241  * accessible register which selects the over voltage alert clear
242  * threshold used with Absolute Auxiliary ADC measurements. */
243  MXM_REG_AUXAOVTHSET = 0x35u, /*!< AUXAOVTHSET is a read and write
244  * accessible register which selects the over voltage alert set
245  * threshold used with Absolute Auxiliary ADC measurements. */
246  MXM_REG_AUXAUVTHCLR = 0x36u, /*!< AUXAUVTHCLR is a read and write
247  * accessible register which selects the under voltage alert clear
248  * threshold used with Absolute Auxiliary ADC measurements. */
249  MXM_REG_AUXAUVTHSET = 0x37u, /*!< AUXAUVTHSET is a read and write
250  * accessible register which selects the under voltage alert set threshold
251  * used with Absolute Auxiliary ADC measurements. */
252  MXM_REG_COMPOVTH = 0x38u, /*!< COMPOVTH is a read and write
253  * accessible register which selects the cell over voltage alert threshold
254  * for the redundant comparator. */
255  MXM_REG_COMPUVTH = 0x39u, /*!< COMPUVTH is a read and write
256  * accessible register which selects the cell under voltage alert threshold
257  * for the redundant comparator. */
258  MXM_REG_COMPAUXROVTH = 0x3Au, /*!< COMPAUXROVTH is a read and write
259  * accessible register which selects the over voltage (cold) alert threshold
260  * applied during Ratiometric Auxiliary comparator measurements. */
261  MXM_REG_COMPAUXRUVTH = 0x3Bu, /*!< COMPAUXRUVTH is a read and write
262  * accessible register which selects the under voltage (hot) alert threshold
263  * applied during Ratiometric Auxiliary comparator measurements. */
264  MXM_REG_COMPAUXAOVTH = 0x3Cu, /*!< COMPAUXAOVTH is a read and write
265  * accessible register which selects the over voltage alert threshold
266  * applied during Absolute Auxiliary comparator measurements. */
267  MXM_REG_COMPAUXAUVTH = 0x3Du, /*!< COMPAUXAUVTH is a read and write
268  * accessible register which selects the under voltage alert threshold
269  * applied during Absolute Auxiliary comparator measurements. */
270  MXM_REG_COMPOPNTH = 0x3Eu, /*!< COMPOPNTH is a read and write
271  * accessible register which selects the under voltage alert threshold
272  * applied to Unipolar Cell inputs in Open Diagnostic Mode. */
273  MXM_REG_COMPAUXROPNTH = 0x3Fu, /*!< COMPAUXROPNTH is a read and write
274  * accessible register which selects the under voltage alert threshold
275  * applied to Ratiometric Auxiliary inputs in Open Diagnostic Mode. */
276  MXM_REG_COMPAUXAOPNTH = 0x40u, /*!< COMPAUXAOPNTH is a read and write
277  * accessible register which selects the under voltage alert threshold
278  * applied to Absolute Auxiliary inputs in Open Diagnostic Mode. */
279  MXM_REG_COMPACCOVTH = 0x41u, /*!< COMPACCOVTH is a read and write
280  * accessible register which selects the over voltage alert threshold
281  * applied during comparator accuracy diagnostics. */
282  MXM_REG_COMPACCUVTH = 0x42u, /*!< COMPACCUVTH is a read and write
283  * accessible register which selects the under voltage alert threshold
284  * applied during comparator accuracy diagnostics. */
285  MXM_REG_BALSHRTTHR = 0x43u, /*!< BALSHRTTHR is a read and write
286  * accessible register which selects alert threshold used during the
287  * Balance Switch Short Diagnostic mode. */
288  MXM_REG_BALLOWTHR = 0x44u, /*!< BALLOWTHR is a read and write
289  * accessible register which selects alert low threshold used during the
290  * Balance Switch Open Diagnostic Mode. */
291  MXM_REG_BALHIGHTHR = 0x45u, /*!< BALHIGHTHR is a read and write
292  * accessible register which selects alert High threshold used during the
293  * Balance Switch Open Diagnostic mode. */
294  MXM_REG_CSA = 0x46u, /*!< MAX17852 only: CSA is a read
295  * accessible register which holds the current value for each enabled
296  * individual auxiliary measurement result. */
297  MXM_REG_CELL1 = 0x47u, /*!< CELLn is a read accessible
298  * register which holds the current value for each individual cell
299  * measurement result. */
300  MXM_REG_CELL2 = 0x48u, /*!< CELLn is a read accessible
301  * register which holds the current value for each individual cell
302  * measurement result. */
303  MXM_REG_CELL3 = 0x49u, /*!< CELLn is a read accessible
304  * register which holds the current value for each individual cell
305  * measurement result. */
306  MXM_REG_CELL4 = 0x4Au, /*!< CELLn is a read accessible
307  * register which holds the current value for each individual cell
308  * measurement result. */
309  MXM_REG_CELL5 = 0x4Bu, /*!< CELLn is a read accessible
310  * register which holds the current value for each individual cell
311  * measurement result. */
312  MXM_REG_CELL6 = 0x4Cu, /*!< CELLn is a read accessible
313  * register which holds the current value for each individual cell
314  * measurement result. */
315  MXM_REG_CELL7 = 0x4Du, /*!< CELLn is a read accessible
316  * register which holds the current value for each individual cell
317  * measurement result. */
318  MXM_REG_CELL8 = 0x4Eu, /*!< CELLn is a read accessible
319  * register which holds the current value for each individual cell
320  * measurement result. */
321  MXM_REG_CELL9 = 0x4Fu, /*!< CELLn is a read accessible
322  * register which holds the current value for each individual cell
323  * measurement result. */
324  MXM_REG_CELL10 = 0x50u, /*!< CELLn is a read accessible
325  * register which holds the current value for each individual cell
326  * measurement result. */
327  MXM_REG_CELL11 = 0x51u, /*!< CELLn is a read accessible
328  * register which holds the current value for each individual cell
329  * measurement result. */
330  MXM_REG_CELL12 = 0x52u, /*!< CELLn is a read accessible
331  * register which holds the current value for each individual cell
332  * measurement result. */
333  MXM_REG_CELL13 = 0x53u, /*!< CELLn is a read accessible
334  * register which holds the current value for each individual cell
335  * measurement result. */
336  MXM_REG_CELL14 = 0x54u, /*!< CELLn is a read accessible
337  * register which holds the current value for each individual cell
338  * measurement result. */
339  MXM_REG_BLOCK = 0x55u, /*!< BLOCK is a read accessible
340  * register which holds the current value for the total block
341  * measurement result. */
342  MXM_REG_TOTAL = 0x56u, /*!< TOTAL is a read accessible
343  * register which holds the current value for the sum of all enabled
344  * measurement results within the stack. */
345  MXM_REG_DIAG1 = 0x57u, /*!< DIAG1 is a read-only
346  * register which contains the Diagnostic result requested by the
347  * DIAGCFG:DIAGSEL1 selection taken during the last ADC acquisition. */
348  MXM_REG_DIAG2 = 0x58u, /*!< DIAG2 is a read-only
349  * register which contains the Diagnostic result requested by the
350  * DIAGCFG:DIAGSEL2 selection taken during the last ADC acquisition. */
351  MXM_REG_AUX0 = 0x59u, /*!< AUXn is a read accessible
352  * register which holds the current value for each enabled individual
353  * auxiliary measurement result. */
354  MXM_REG_AUX1 = 0x5Au, /*!< AUXn is a read accessible
355  * register which holds the current value for each enabled individual
356  * auxiliary measurement result. */
357  MXM_REG_AUX2 = 0x5Bu, /*!< AUXn is a read accessible
358  * register which holds the current value for each enabled individual
359  * auxiliary measurement result. */
360  MXM_REG_AUX3 = 0x5Cu, /*!< AUXn is a read accessible
361  * register which holds the current value for each enabled individual
362  * auxiliary measurement result. */
363  MXM_REG_AUX4 = 0x5Du, /*!< MAX17853 only: AUXn is a
364  * read accessible register which holds the current value for each
365  * enabled individual auxiliary measurement result. */
366  MXM_REG_AUX5 = 0x5Eu, /*!< MAX17853 only: AUXn is a
367  * read accessible register which holds the current value for each
368  * enabled individual auxiliary measurement result. */
369  MXM_REG_POLARITYCTRL = 0x5Fu, /*!< POLARITYCTRL is a read and
370  * write accessible register which governs the measurement type
371  * used during scans. In general, Unipolar mode indicates a Cell and
372  * Bipolar mode indicates a Bus-Bar. */
373  MXM_REG_AUXREFCTRL = 0x60u, /*!< AUXREFCTRL is a read and
374  * write accessible register which governs the reference range used
375  * for enabled Auxiliary channels during ADC and COMP acquisition
376  * sequences. */
377  MXM_REG_AUXTIME = 0x61u, /*!< AUXTIME is a read
378  * and write accessible register which governs the setting time
379  * allowed for biasing AUX/GPIO pins prior to measurements. */
380  MXM_REG_ACQCFG = 0x62u, /*!< ACQCFG is a read and write
381  * accessible register which governs several aspects of the
382  * measurement and acquisition procedure. */
383  MXM_REG_BALSWDLY = 0x63u, /*!< BALSWDLY is a read and
384  * write accessible register which selects the delay intervals
385  * used within Manual and Automated Cell Balancing operations
386  * when ADC measurements are requested. */
387  MXM_REG_MEASUREEN1 = 0x64u, /*!< MEASUREEN1 is a read and write
388  * accessible register which governs the channels measured during
389  * ADC and COMP acquisition sequences. */
390  MXM_REG_MEASUREEN2 = 0x65u, /*!< MEASUREEN2 is a read and write
391  * accessible register which governs the auxiliary channels measured
392  * during ADC and COMP acquisition sequences, as well as
393  * IIR initialization. */
394  MXM_REG_SCANCTRL = 0x66u, /*!< SCANCTRL is a read and write
395  * accessible register which governs the internal measurement
396  * acquisitions (scan) requested of the device. The register also manages
397  * the handling of data generated as a result of any scan request.
398  *
399  * ADC Scans are used for precision measurements of cell and auxiliary
400  * voltages.
401  *
402  * COMP Scans are used for periodic safety/redundancy checking
403  * of ADC results, and in some cases, enhanced communication efficiency.
404  *
405  * On Demand Calibration will run an internal calibration of the ADC and
406  * update the Calibration Data Registers. All ADC measurements requested
407  * by Scan and Diagnostic Configuration and Control settings will be
408  * ignored.
409  *
410  * Balance Switch and Cell Sense Wire Open ADC Diagnostic Scans are a
411  * special class of ADC Scan. Use of these settings temporarily
412  * overrides other Scan and Diagnostic Configuration and Control settings.
413  * See BALSW and Cell Sense Wire Diagnostics for details. */
414  MXM_REG_ADCTEST1A = 0x67u, /*!< ADCTEST1A is a read and write
415  * accessible register which contains user specified arguments used in ALU
416  * Diagnostics. */
417  MXM_REG_ADCTEST1B = 0x68u, /*!< ADCTEST1B is a read and write
418  * accessible register which contains user specified arguments used in ALU
419  * Diagnostics. */
420  MXM_REG_ADCTEST2A = 0x69u, /*!< ADCTEST2A is a read and write
421  * accessible register which contains user specified arguments used in ALU
422  * Diagnostics. */
423  MXM_REG_ADCTEST2B = 0x6Au, /*!< ADCTEST2B is a read and write
424  * accessible register which contains user specified arguments used in ALU
425  * Diagnostics. */
426  MXM_REG_DIAGCFG = 0x6Bu, /*!< DIAGCFG is a read and write
427  * accessible register which governs diagnostic source and mode options
428  * applied to the internal measurement acquisitions (scans). */
429  MXM_REG_CTSTCFG = 0x6Cu, /*!< CTSTCFG is a read and write
430  * accessible register which controls the application of diagnostic
431  * current sources to selected cell input channels. */
432  MXM_REG_AUXSTCFG = 0x6Du, /*!< AUXSTCFG is a read and write
433  * accessible register which controls the application of diagnostic modes
434  * and current source to selected Auxiliary and/or CSA input channels. */
435  MXM_REG_DIAGGENCFG = 0x6Eu, /*!< DIAGGENCFG is a read and write
436  * accessible register which controls the application of general diagnostic
437  * modes to the selected Auxiliary and/or CSA input paths. */
438  MXM_REG_BALSWCTRL = 0x6Fu, /*!< BALSWCTRL is a read and write
439  * accessible register which governs the behavior of the Charge Balancing
440  * Switches in Manual and Auto Cell Balancing modes.
441  *
442  * Write access to this register is blocked during Automated Cell
443  * Balancing operations (CBMODE=001, 1xx). */
444  MXM_REG_BALEXP1 = 0x70u, /*!< BALEXPn is a read and write
445  * accessible register which holds the Cell Balancing Expiration Time
446  * for CELLn (using the switch across SWn and SWn-1).
447  *
448  * BALEXP1 sets the Expiration Time for all Group Auto Cell Balancing and
449  * Discharge modes and the Watchdog time out for Manual Cell Balancing mode.
450  *
451  * Write access to this register is blocked during all Cell Balancing
452  * operations (CBMODE!=000). */
453  MXM_REG_BALEXP2 = 0x71u, /*!< BALEXPn is a read and write
454  * accessible register which holds the Cell Balancing Expiration Time
455  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
456  * Auto Cell Balancing modes only.
457  *
458  * Write access to this register is blocked during Automatic Cell
459  * Balancing operations (CBMODE=1xx). */
460  MXM_REG_BALEXP3 = 0x72u, /*!< BALEXPn is a read and write
461  * accessible register which holds the Cell Balancing Expiration Time
462  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
463  * Auto Cell Balancing modes only.
464  *
465  * Write access to this register is blocked during Automatic Cell
466  * Balancing operations (CBMODE=1xx). */
467  MXM_REG_BALEXP4 = 0x73u, /*!< BALEXPn is a read and write
468  * accessible register which holds the Cell Balancing Expiration Time
469  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
470  * Auto Cell Balancing modes only.
471  *
472  * Write access to this register is blocked during Automatic Cell
473  * Balancing operations (CBMODE=1xx). */
474  MXM_REG_BALEXP5 = 0x74u, /*!< BALEXPn is a read and write
475  * accessible register which holds the Cell Balancing Expiration Time
476  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
477  * Auto Cell Balancing modes only.
478  *
479  * Write access to this register is blocked during Automatic Cell
480  * Balancing operations (CBMODE=1xx). */
481  MXM_REG_BALEXP6 = 0x75u, /*!< BALEXPn is a read and write
482  * accessible register which holds the Cell Balancing Expiration Time
483  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
484  * Auto Cell Balancing modes only.
485  *
486  * Write access to this register is blocked during Automatic Cell
487  * Balancing operations (CBMODE=1xx). */
488  MXM_REG_BALEXP7 = 0x76u, /*!< BALEXPn is a read and write
489  * accessible register which holds the Cell Balancing Expiration Time
490  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
491  * Auto Cell Balancing modes only.
492  *
493  * Write access to this register is blocked during Automatic Cell
494  * Balancing operations (CBMODE=1xx). */
495  MXM_REG_BALEXP8 = 0x77u, /*!< BALEXPn is a read and write
496  * accessible register which holds the Cell Balancing Expiration Time
497  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
498  * Auto Cell Balancing modes only.
499  *
500  * Write access to this register is blocked during Automatic Cell
501  * Balancing operations (CBMODE=1xx). */
502  MXM_REG_BALEXP9 = 0x78u, /*!< BALEXPn is a read and write
503  * accessible register which holds the Cell Balancing Expiration Time
504  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
505  * Auto Cell Balancing modes only.
506  *
507  * Write access to this register is blocked during Automatic Cell
508  * Balancing operations (CBMODE=1xx). */
509  MXM_REG_BALEXP10 = 0x79u, /*!< BALEXPn is a read and write
510  * accessible register which holds the Cell Balancing Expiration Time
511  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
512  * Auto Cell Balancing modes only.
513  *
514  * Write access to this register is blocked during Automatic Cell
515  * Balancing operations (CBMODE=1xx). */
516  MXM_REG_BALEXP11 = 0x7Au, /*!< BALEXPn is a read and write
517  * accessible register which holds the Cell Balancing Expiration Time
518  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
519  * Auto Cell Balancing modes only.
520  *
521  * Write access to this register is blocked during Automatic Cell
522  * Balancing operations (CBMODE=1xx). */
523  MXM_REG_BALEXP12 = 0x7Bu, /*!< BALEXPn is a read and write
524  * accessible register which holds the Cell Balancing Expiration Time
525  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
526  * Auto Cell Balancing modes only.
527  *
528  * Write access to this register is blocked during Automatic Cell
529  * Balancing operations (CBMODE=1xx). */
530  MXM_REG_BALEXP13 = 0x7Cu, /*!< BALEXPn is a read and write
531  * accessible register which holds the Cell Balancing Expiration Time
532  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
533  * Auto Cell Balancing modes only.
534  *
535  * Write access to this register is blocked during Automatic Cell
536  * Balancing operations (CBMODE=1xx). */
537  MXM_REG_BALEXP14 = 0x7Du, /*!< BALEXPn is a read and write
538  * accessible register which holds the Cell Balancing Expiration Time
539  * for CELLn (using the switch across SWn and SWn-1). Used in Individual
540  * Auto Cell Balancing modes only.
541  *
542  * Write access to this register is blocked during Automatic Cell
543  * Balancing operations (CBMODE=1xx). */
544  MXM_REG_BALAUTOUVTHR = 0x7Eu, /*!< BALAUTOUVTHR is a read and write
545  * accessible register which selects the cell under voltage exit threshold
546  * for the ADC when used in Automated Cell Balancing operations.
547  *
548  * A write to this register allows direct setting or automatic selection
549  * of this threshold.
550  *
551  * Write access to this register is blocked during Automatic Cell
552  * Balancing operations (CBMODE=1xx). Also, during active measurement scans,
553  * all writes with CBUVMINCELL=1 will be blocked and will result in ALRTRJCT
554  * being issued (since the MINCELL data may be altered as a result of the
555  * scan in progress).
556  *
557  * A read from this register will display the current value of the threshold
558  * and the method used for its selection. */
559  MXM_REG_BALDLYCTRL = 0x7Fu, /*!< BALDLYCTRL is a read and write
560  * accessible register which selects the delay/timing intervals used within
561  * Automated Cell Balancing operations.
562  *
563  * Write access to this register is blocked during Automated Cell Balancing
564  * operations (CBMODE=001, 1xx). */
565  MXM_REG_BALCTRL = 0x80u, /*!< BALCTRL is a read and write
566  * accessible register which initiates and controls all internal Cell
567  * Balancing modes and operations.
568  *
569  * Any write to this register to a mode other than CBMODE=000 (Disable)
570  * will restart the CBTIMER at zero and launch the requested mode of
571  * operation. */
572  MXM_REG_BALSTAT = 0x81u, /*!< BALSTAT is a read accessible
573  * register which allows the monitoring of any Automated Cell Balancing
574  * operations currently in progress.
575  *
576  * Once a CBMODE is initiated, all status bits persist and are cleared
577  * only when CBMODE is written to 000 (Disabled) or when a new CBMODE
578  * operation is initiated via CBSTART. */
579  MXM_REG_BALUVSTAT = 0x82u, /*!< BALUVSTAT is a read accessible
580  * register which relates current summary information on the Cell
581  * voltages vs. the CBUVTHR undervoltage threshold. */
582  MXM_REG_BALDATA = 0x83u, /*!< BALDATA is a read accessible
583  * register which relates current summary information on the Cell voltage
584  * vs. the CBUVTHR undervoltage threshold. */
585  MXM_REG_I2CPNTR = 0x84u, /*!< MAX17852 only: I2CPNTR is a
586  * read and write accessible register which contains two Pointer bytes
587  * (Register Addresses) available for I2C Master transactions.
588  *
589  * Once I2CSEND initiates a read or write transaction, attempts to write
590  * I2CPNTR during the transaction will be ignored and will case an
591  * I2CRJCT fault to be issued. */
592  MXM_REG_I2CWDATA1 = 0x85u, /*!< MAX17852 only: I2CWDATA1 is a
593  * read and write accessible register which contains the upper data bytes
594  * available for I2C Master Write Mode transactions.
595  *
596  * Once I2CSEND initiates an I2C read or write transaction, attempts to
597  * write I2CWDATA1 during the transaction will be ignored and will cause
598  * an I2CRJCT fault to be issued. */
599  MXM_REG_I2CWDATA2 = 0x86u, /*!< MAX17852 only: I2CWDATA2 is a
600  * read and write accessible register which contains the lower data bytes
601  * available for I2C Master Write Mode transactions.
602  *
603  * Once I2CSEND initiates an I2C read or write transaction, attempts to
604  * write I2CWDATA2 during the transaction will be ignored and will cause
605  * an I2CRJCT fault to be issued. */
606  MXM_REG_I2CRDATA1 = 0x87u, /*!< MAX17852 only: I2CRDATA1 is a
607  * read accessible register which contains the upper data bytes received
608  * for I2C Master Read Mode transactions.
609  *
610  * Note during I2C read transactions, data is updated as each byte is
611  * received/acknowledged, so reading back this register during active
612  * I2C read transactions will cause an I2CRJCT fault to be issued. */
613  MXM_REG_I2CRDATA2 = 0x88u, /*!< MAX17852 only: I2CRDATA2 is a
614  * read accessible register which contains the lower data bytes received
615  * for I2C Master Read Mode transactions.
616  *
617  * Note during I2C read transactions, data is updated as each byte is
618  * received/acknowledged, so reading back this register during active
619  * I2C read transactions will cause an I2CRJCT fault to be issued. */
620  MXM_REG_I2CCFG = 0x89u, /*!< MAX17852 only: I2CCFG is a
621  * read and write accessible register which configures I2C Master
622  * modes and transaction formats.
623  *
624  * Once I2CSEND initiates a read or write transaction, attempts to
625  * write I2CCFG during the transaction will be ignored and will cause
626  * and I2CRJCT fault to be issued. */
627  MXM_REG_I2CSTAT = 0x8Au, /*!< MAX17852 only: I2CSTAT is
628  * a read and write accessible register which shows the current status
629  * of the I2C Master.
630  *
631  * The I2CSTATUS bits are updated in real time, indicating the current
632  * state of the I2C Master and any requested transaction. This status
633  * can be cleared by write operations and modified by transaction progress
634  * or subsequent transaction requests.
635  *
636  * The second byte contains I2C Fault bits, indicating a fault was
637  * observed during an I2C transaction. These bits are updated as they
638  * occur and are only cleared by writing to zero. Several faults may
639  * occur during a corrupted transaction, so it is best to wait until
640  * I2CSTATUS reads 10 (Transaction Error) to ensure all errors have
641  * been reported.
642  *
643  * While not advisable, if further I2C transactions are requested before
644  * the I2C Fault bits from previous transactions are read back and cleared,
645  * a cumulative history of faults will be listed, even if subsequent
646  * transactions are successful. */
647  MXM_REG_I2CSEND = 0x8Bu, /*!< MAX17852 only: I2CSEND is a
648  * read and write accessible register which configures and initiates
649  * an I2C Master transaction.
650  *
651  * A write to this register will initiate an I2C Master transaction.
652  * Only one transaction is supported at any given time. If a write to
653  * I2CSEND occurs during an active I2C transaction already in progress,
654  * the latest transaction request will be ignored and the I2CSEND
655  * contents will not be updated. If this occurs, an I2CRJCT fault will
656  * be issued.
657  *
658  * A read from this register will readback the current contents. This
659  * will represent the last transaction request accepted by the I2C Master. */
660  MXM_REG_ID1 = 0x8Cu, /*!< ID1 is a read accessible register
661  * which contains the 2 LSBytes of the unique Device ID stored in ROM and
662  * subject to ROMCRC validation. */
663  MXM_REG_ID2 = 0x8Du, /*!< ID2 is a read accessible register
664  * which contains the 2 MSBytes of the unique Device ID stored in ROM and
665  * subject to ROMCRC validation. */
666  MXM_REG_OTP2 = 0x8Eu, /*!< Factory Calibration Data ROM
667  * and subject to ROMCRC validation. */
668  MXM_REG_OTP3 = 0x8Fu, /*!< Factory Calibration Data ROM
669  * and subject to ROMCRC validation. */
670  MXM_REG_OTP4 = 0x90u, /*!< Factory Calibration Data ROM
671  * and subject to ROMCRC validation. */
672  MXM_REG_OTP5 = 0x91u, /*!< Factory Calibration Data ROM
673  * and subject to ROMCRC validation. */
674  MXM_REG_OTP6 = 0x92u, /*!< Factory Calibration Data ROM
675  * and subject to ROMCRC validation. */
676  MXM_REG_OTP7 = 0x93u, /*!< Factory Calibration Data ROM
677  * and subject to ROMCRC validation. */
678  MXM_REG_OTP8 = 0x94u, /*!< Factory Calibration Data ROM
679  * and subject to ROMCRC validation. */
680  MXM_REG_OTP9 = 0x95u, /*!< Factory Calibration Data ROM
681  * and subject to ROMCRC validation. */
682  MXM_REG_OTP10 = 0x96u, /*!< Factory Calibration Data ROM
683  * and subject to ROMCRC validation. */
684  MXM_REG_OTP11 = 0x97u, /*!< Factory Calibration Data ROM
685  * and subject to ROMCRC validation. */
686  MXM_REG_OTP12 = 0x98u, /*!< Factory Calibration Data ROM
687  * and subject to ROMCRC validation. */
689 
690 /**
691  * @brief Type for register access for monitoring ICs.
692  */
693 typedef uint16_t MXM_REG_BM;
694 
695 /**
696  * @brief Define enumeration values for bitmasks
697  * @details Generates a bitmask from start to end.
698  * Examples:
699  * - 0000 0001b == MXM_REG_BIT_DEFN(0, 0)
700  * - 0000 1000b == MXM_REG_BIT_DEFN(3, 3)
701  * - 0011 1000b == MXM_REG_BIT_DEFN(3, 5)
702  */
703 #define MXM_REG_BIT_DEFN(start, end) ((MXM_REG_BM)(((MXM_REG_BM)1u << ((end) - (start) + 1u)) - 1u) << (start))
704 
705 /**
706  * @defgroup mxm_bm Bitmasks for register access of MAX1785x
707  * @{
708  */
709 /**
710  * @brief Monitoring Register Null byte
711  */
712 #define MXM_BM_NULL ((MXM_REG_BM)0x00u)
713 /**
714  * @brief Monitoring Register LSB
715  */
716 #define MXM_BM_LSB ((MXM_REG_BM)MXM_REG_BIT_DEFN(0u, 7u))
717 /**
718  * @brief Monitoring Register MSB
719  */
720 #define MXM_BM_MSB ((MXM_REG_BM)MXM_REG_BIT_DEFN(8u, 15u))
721 /**
722  * @brief All bits of monitoring register
723  */
724 #define MXM_BM_WHOLE_REG ((MXM_REG_BM)0xFFFFu)
725 /**
726  * @brief Monitoring Register Version/Model
727  */
728 #define MXM_REG_VERSION_MOD ((MXM_REG_BM)MXM_REG_BIT_DEFN(4u, 15u))
729 /**
730  * @brief Monitoring Register Version/Silicon Version
731  */
732 #define MXM_REG_VERSION_VER ((MXM_REG_BM)MXM_REG_BIT_DEFN(0u, 3u))
733 /**
734  * @brief Monitoring Register 14bit ADC value
735  */
736 #define MXM_REG_ADC_14BIT_VALUE ((MXM_REG_BM)MXM_REG_BIT_DEFN(2u, 15u))
737 /**
738  * @brief ALRTRST bit in STATUS1
739  */
740 #define MXM_REG_STATUS1_ALRTRST ((MXM_REG_BM)((MXM_REG_BM)(1u) << (14u)))
741 /**
742  * @brief ALRTINTRFC bit in STATUS1
743  */
744 #define MXM_REG_STATUS1_ALRTINTRFC ((MXM_REG_BM)((1u) << (4u)))
745 
746 /**
747  * @}
748  */
749 
750 /*========== Extern Constant and Variable Declarations ======================*/
751 
752 /*========== Extern Function Prototypes =====================================*/
753 
754 /*========== Externalized Static Functions Prototypes (Unit Test) ===========*/
755 
756 #endif /* FOXBMS__MXM_REGISTER_MAP_H_ */
General macros and definitions for the whole platform.
uint16_t MXM_REG_BM
Type for register access for monitoring ICs.
MXM_REG_NAME_e
MAX1785x register names.
@ MXM_REG_AUXREFCTRL
@ MXM_REG_CTSTCFG
@ MXM_REG_COMPOVTH
@ MXM_REG_ADCTEST2A
@ MXM_REG_MINMAXCELL
@ MXM_REG_PACKCFG
@ MXM_REG_ADCTEST1B
@ MXM_REG_CELL1
@ MXM_REG_CELL4
@ MXM_REG_AUXSTCFG
@ MXM_REG_BALSHRTTHR
@ MXM_REG_GPIOCFG
@ MXM_REG_BIPUVTHSET
@ MXM_REG_BALEXP11
@ MXM_REG_MSMTCH
@ MXM_REG_STATUS1
@ MXM_REG_ALRTAUXUV
@ MXM_REG_BALAUTOUVTHR
@ MXM_REG_BALEXP6
@ MXM_REG_AUX4
@ MXM_REG_STATUS3
@ MXM_REG_CSAUVTHSET
@ MXM_REG_STATUS2
@ MXM_REG_BALEXP2
@ MXM_REG_OTP4
@ MXM_REG_AUXROVTHSET
@ MXM_REG_OTP3
@ MXM_REG_I2CRDATA2
@ MXM_REG_SWACTION
@ MXM_REG_COMPACCOVTH
@ MXM_REG_AUX0
@ MXM_REG_CSA
@ MXM_REG_ALRTSUM
@ MXM_REG_CELL10
@ MXM_REG_OTP5
@ MXM_REG_BALEXP13
@ MXM_REG_BALLOWTHR
@ MXM_REG_ALRTUVCELL
@ MXM_REG_I2CCFG
@ MXM_REG_OVTHCLR
@ MXM_REG_BALEXP5
@ MXM_REG_ALRTAUXOVEN
@ MXM_REG_COMPACCUVTH
@ MXM_REG_I2CWDATA2
@ MXM_REG_UVTHSET
@ MXM_REG_BALEXP10
@ MXM_REG_OTP9
@ MXM_REG_AUX3
@ MXM_REG_BIPOVTHSET
@ MXM_REG_ALRTOVCELL
@ MXM_REG_BALEXP1
@ MXM_REG_COMPAUXAOPNTH
@ MXM_REG_UVTHCLR
@ MXM_REG_SCANCTRL
@ MXM_REG_BALSTAT
@ MXM_REG_BIPUVTHCLR
@ MXM_REG_CSAOVTHSET
@ MXM_REG_ALRTIRQEN
@ MXM_REG_OTP11
@ MXM_REG_VERSION
@ MXM_REG_MEASUREEN2
@ MXM_REG_ALRTCOMPAUXOV
@ MXM_REG_I2CSTAT
@ MXM_REG_COMPAUXAOVTH
@ MXM_REG_ID1
@ MXM_REG_AUX5
@ MXM_REG_BALEXP14
@ MXM_REG_I2CPNTR
@ MXM_REG_AUXAUVTHSET
@ MXM_REG_ALRTAUXUVEN
@ MXM_REG_CELL9
@ MXM_REG_AUXTIME
@ MXM_REG_BLOCK
@ MXM_REG_DEVCFG2
@ MXM_REG_ALRTAUXOV
@ MXM_REG_COMPOPNTH
@ MXM_REG_COMPAUXRUVTH
@ MXM_REG_OTP10
@ MXM_REG_AUXGPIOCFG
@ MXM_REG_I2CWDATA1
@ MXM_REG_BLKOVTHCLR
@ MXM_REG_AUXAOVTHSET
@ MXM_REG_OTP7
@ MXM_REG_CELL3
@ MXM_REG_BALEXP8
@ MXM_REG_FMEA1
@ MXM_REG_CSAUVTHCLR
@ MXM_REG_I2CRDATA1
@ MXM_REG_ID2
@ MXM_REG_BALEXP9
@ MXM_REG_ALRTCALTST
@ MXM_REG_TOTAL
@ MXM_REG_BALUVSTAT
@ MXM_REG_CELL14
@ MXM_REG_CELL6
@ MXM_REG_OTP8
@ MXM_REG_I2CSEND
@ MXM_REG_ACQCFG
@ MXM_REG_BALCTRL
@ MXM_REG_CELL2
@ MXM_REG_BLKUVTHCLR
@ MXM_REG_BALEXP7
@ MXM_REG_CSAOVTHCLR
@ MXM_REG_DIAG1
@ MXM_REG_BIPOVTHCLR
@ MXM_REG_BALDLYCTRL
@ MXM_REG_ALRTUVEN
@ MXM_REG_BLKUVTHSET
@ MXM_REG_BLKOVTHSET
@ MXM_REG_COMPAUXROVTH
@ MXM_REG_DIAG2
@ MXM_REG_BALEXP3
@ MXM_REG_DIAGCFG
@ MXM_REG_ADCTEST2B
@ MXM_REG_CELL11
@ MXM_REG_AUXAUVTHCLR
@ MXM_REG_ALRTAUXPRTCT
@ MXM_REG_MEASUREEN1
@ MXM_REG_BALSWDLY
@ MXM_REG_BALDATA
@ MXM_REG_CELL5
@ MXM_REG_OTP2
@ MXM_REG_POLARITYCTRL
@ MXM_REG_CELL13
@ MXM_REG_OVTHSET
@ MXM_REG_AUX2
@ MXM_REG_DIAGGENCFG
@ MXM_REG_BALSWCTRL
@ MXM_REG_OTP6
@ MXM_REG_FMEA2
@ MXM_REG_COMPAUXROPNTH
@ MXM_REG_AUX1
@ MXM_REG_CELL7
@ MXM_REG_AUXOVTHCLR
@ MXM_REG_ALRTCOMPOV
@ MXM_REG_AUXRUVTHCLR
@ MXM_REG_ALRTCOMPAUXUV
@ MXM_REG_ADDRESS
@ MXM_REG_BALEXP12
@ MXM_REG_AUXROVTHCLR
@ MXM_REG_ALRTCOMPUV
@ MXM_REG_DEVCFG1
@ MXM_REG_OTP12
@ MXM_REG_ALRTOVEN
@ MXM_REG_ADCTEST1A
@ MXM_REG_COMPUVTH
@ MXM_REG_CELL8
@ MXM_REG_AUXRUVTHSET
@ MXM_REG_COMPAUXAUVTH
@ MXM_REG_CELL12
@ MXM_REG_BALHIGHTHR
@ MXM_REG_ALRTBALSW
@ MXM_REG_BALEXP4