The cache of the MCU must be activated, otherwise the performance hit is too
high. But if DMA is used in conjunction with the cache, cache coherency
problems arise. If a variable X is copied in the cache, it will not be updated
in the main memory. Similarly, if X is written in the main memory, it will not
be updated in the cache.
To solve this problem, a non cacheable area must be declared in the RAM. The
arrays read/written by DMA must then be located in this area.
The next step is the adapt the linker script. In this example, the size of the
non-cacheable area is 4kB, or 0x1000. In the linker script, the initial
size declared for the RAM is 0x7F000. The size of the non-cacheable area
must be subtracted, so the new RAM size is 0x7E000.
The next region after RAM starts at 0x08008000. The start address of the
non-cacheable area is then 0x08008000-0x1000=0x08007000. The resulting
section of the linker script is