foxBMS - Unit Tests  1.4.0
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test_mxm_17841b.c
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41 
42 /**
43  * @file test_mxm_17841b.c
44  * @author foxBMS Team
45  * @date 2020-06-22 (date of creation)
46  * @updated 2022-07-28 (date of last update)
47  * @version v1.4.0
48  * @ingroup UNIT_TEST_IMPLEMENTATION
49  * @prefix MXM
50  *
51  * @brief Test for the Maxim MAX17841B driver.
52  *
53  * @details def
54  *
55  */
56 
57 /*========== Includes =======================================================*/
58 #include "unity.h"
59 #include "Mockfassert.h"
60 #include "Mockmxm_cfg.h"
61 #include "Mockos.h"
62 
63 #include "mxm_17841b.h"
64 #include "mxm_bitextract.h"
65 #include "test_assert_helper.h"
66 
67 /*========== Definitions and Implementations for Unit Test ==================*/
68 /** replicating the config register length in the driver */
69 #define MXM_41B_CONFIG_REGISTER_LENGTH (7u)
70 
73  .substate = MXM_41B_ENTRY_SUBSTATE,
74  .extendMessageBytes = 0,
75  .waitCounter = 0,
76  .regRXIntEnable = 0x00u,
77  .regTXIntEnable = 0x00u,
78  .regRXStatus = 0x00u,
79  .regTXStatus = 0x00u,
80  .regConfig1 = MXM_41B_CONFIG_1_DEFAULT_VALUE,
81  .regConfig2 = MXM_41B_CONFIG_2_DEFAULT_VALUE,
82  .regConfig3 = MXM_41B_CONFIG_3_DEFAULT_VALUE,
83  .hwModel = 0,
84  .hwMaskRevision = 0,
85  .spiRXBuffer = {0},
86  .spiTXBuffer = {0},
87 };
88 
89 uint16_t commandBuffer[10] = {0};
90 uint16_t rxBuffer[100] = {0};
91 
93 
94 /*========== Setup and Teardown =============================================*/
95 void setUp(void) {
98 
99  commandBuffer[0] = 0;
100  commandBuffer[1] = 0;
101  commandBuffer[2] = 0;
102  commandBuffer[3] = 0;
103  commandBuffer[4] = 0;
104  commandBuffer[5] = 0;
105  commandBuffer[6] = 0;
106  commandBuffer[7] = 0;
107  commandBuffer[8] = 0;
108  commandBuffer[9] = 0;
109 
111 }
112 
113 void tearDown(void) {
114 }
115 
116 /*========== Test Cases =====================================================*/
117 /**
118  * \defgroup mxm41b-set-state-request tests for function MXM_41BSetStateRequest
119  * @{
120  */
121 
122 /**
123  * @brief Test with an invalid pointer
124  * @details This test calls #MXM_41BSetStateRequest() with an invalid pointer
125  * value and expects an assertion to be triggered.
126  */
130 }
131 
132 /**
133  * @brief Test that the only transition from uninitialized is initialization
134  * @details This test expects the state machine to be in state
135  * #MXM_STATEMACH_41B_UNINITIALIZED and various transitions to other
136  * states. The only valid transition has to be to
137  * #MXM_STATEMACH_41B_INIT. This is check by evaluating the return
138  * value of #MXM_41BSetStateRequest().
139  */
141  TEST_ASSERT_EQUAL(
142  STD_NOT_OK,
145  TEST_ASSERT_EQUAL(
146  STD_NOT_OK,
149  TEST_ASSERT_EQUAL(
150  STD_NOT_OK,
153  TEST_ASSERT_EQUAL(
154  STD_OK,
156 }
157 
159  /* start in Idle state */
161 
162  TEST_ASSERT_EQUAL(
163  STD_OK,
166 
167  /* try additional transition (even though not in idle state anymore) */
168  TEST_ASSERT_EQUAL(
169  STD_NOT_OK,
172 }
173 
175  TEST_ASSERT_EQUAL(
176  STD_OK,
178 }
179 
181  TEST_ASSERT_EQUAL(
182  STD_NOT_OK,
184 
185  TEST_ASSERT_EQUAL(
186  STD_NOT_OK,
188 
189  TEST_ASSERT_EQUAL(
190  STD_OK,
192 }
193 
195  TEST_ASSERT_EQUAL(
196  STD_NOT_OK,
198 
199  TEST_ASSERT_EQUAL(
200  STD_NOT_OK,
202 
203  TEST_ASSERT_EQUAL(
204  STD_OK,
206 }
207 
209  TEST_ASSERT_EQUAL(
210  STD_NOT_OK,
212 }
213 
214 /** @}
215  * end of tests for function MXM_41BSetStateRequest */
216 
217 /**
218  * \defgroup mxm41b-write-register-function tests for function MXM_41BWriteRegisterFunction
219  * @{
220  */
222  TEST_ASSERT_EQUAL(STD_NOT_OK, MXM_41BWriteRegisterFunction(&mxm_41bState, 0xFF, 0));
224 }
225 
227  /* standard state should be only fourth bit set */
228  TEST_ASSERT_EQUAL(0x10u, mxm_41bState.regConfig2);
229  TEST_ASSERT_EQUAL(
231  TEST_ASSERT_EQUAL(0x10u, mxm_41bState.regConfig2);
232 
233  /* after writing register, fifth bit should be set in addition */
234  TEST_ASSERT_EQUAL(
236  TEST_ASSERT_EQUAL((0x10u | (1u << 5u)), mxm_41bState.regConfig2);
237 
238  /* standard state should be third, second, first and zero bit set */
239  TEST_ASSERT_EQUAL(0xFu, mxm_41bState.regConfig3);
240 
241  /* 0us --> 0 */
242  TEST_ASSERT_EQUAL(
243  STD_OK,
245  TEST_ASSERT_EQUAL(0x0u, mxm_41bState.regConfig3);
246 
247  /* 10us --> 1 */
248  TEST_ASSERT_EQUAL(
249  STD_OK,
251  TEST_ASSERT_EQUAL(0x1u, mxm_41bState.regConfig3);
252 
253  /* 640us --> 0x7 */
254  TEST_ASSERT_EQUAL(
255  STD_OK,
257  TEST_ASSERT_EQUAL(0x7u, mxm_41bState.regConfig3);
258 
259  /* INF DLY --> 0xF */
260  TEST_ASSERT_EQUAL(
261  STD_OK,
263  TEST_ASSERT_EQUAL(0xFu, mxm_41bState.regConfig3);
264 
265  /* standard state should be zero */
266  TEST_ASSERT_EQUAL(0x0u, mxm_41bState.regRXIntEnable);
267 
268  /* rx error int on --> 0x80 */
269  TEST_ASSERT_EQUAL(
271  TEST_ASSERT_EQUAL(0x80u, mxm_41bState.regRXIntEnable);
272 
273  /* rx error int off --> 0 */
274  TEST_ASSERT_EQUAL(
276  TEST_ASSERT_EQUAL(0x0u, mxm_41bState.regRXIntEnable);
277 
278  /* standard state should be zero */
279  TEST_ASSERT_EQUAL(0x0u, mxm_41bState.regRXIntEnable);
280 
281  /* rx overflow int on --> 0x8 */
282  TEST_ASSERT_EQUAL(
284  TEST_ASSERT_EQUAL(0x8u, mxm_41bState.regRXIntEnable);
285 
286  /* rx overflow int off --> 0 */
287  TEST_ASSERT_EQUAL(
289  TEST_ASSERT_EQUAL(0x0u, mxm_41bState.regRXIntEnable);
290 }
291 /** @}
292  * end of tests for function MXM_41BWriteRegisterFunction */
293 
294 /**
295  * \defgroup mxm41b-read-register-function tests for function MXM_41BReadRegisterFunction
296  * @{
297  */
299  MXM_41B_REG_BIT_VALUE result = {0};
300  TEST_ASSERT_EQUAL(STD_NOT_OK, MXM_41BReadRegisterFunction(&mxm_41bState, 0xFF, &result));
303 }
305  MXM_41B_REG_BIT_VALUE result = 42;
306  /* set register */
308 
309  /* read all functions in this register */
311  TEST_ASSERT_EQUAL(MXM_41B_REG_FALSE, result);
312 
313  TEST_ASSERT_EQUAL(
315  TEST_ASSERT_EQUAL(MXM_41B_REG_FALSE, result);
316 
317  /* set register with bit RX_EMPTY */
319 
320  /* read all functions in this register */
322  TEST_ASSERT_EQUAL(MXM_41B_REG_FALSE, result);
323 
324  TEST_ASSERT_EQUAL(
326  TEST_ASSERT_EQUAL(MXM_41B_REG_TRUE, result);
327 
328  /* set register with bit RX_BUSY */
329  mxm_41bState.regRXStatus = 0x20u;
330 
331  /* read all functions in this register */
333  TEST_ASSERT_EQUAL(MXM_41B_REG_TRUE, result);
334 
335  TEST_ASSERT_EQUAL(
337  TEST_ASSERT_EQUAL(MXM_41B_REG_FALSE, result);
338 
339  /* set register to zero */
341 
342  /* read all functions in this register */
344  TEST_ASSERT_EQUAL(MXM_41B_REG_FALSE, result);
345 
346  /* set register with TX_PREAMBLES */
347  mxm_41bState.regConfig2 = 0x20u;
348 
349  /* read all functions in this register */
351  TEST_ASSERT_EQUAL(MXM_41B_REG_TRUE, result);
352 }
353 /** @}
354  * end of tests for function MXM_41BReadRegisterFunction */
355 
356 /**
357  * \defgroup mxm41b-state-machine tests for the MXM_41b-state-machine
358  * @{
359  */
364 }
365 
367  /* force state-machine in idle state */
369 
370  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
372  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
373 }
374 
375 void testStateCheckFMEA(void) {
376  /* force state-machine in check_fmea state */
378 
379  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_CHECK_FMEA, mxm_41bState.state);
380 
381  /* create a buffer with the assumed output of the ASCI and inject into SPI read */
382  uint16_t rxBuffer[10] = {0x13u, 0x00u};
383  MXM_ReceiveData_ExpectAndReturn(mxm_41bState.spiTXBuffer, mxm_41bState.spiRXBuffer, 2, STD_OK);
384  MXM_ReceiveData_ReturnArrayThruPtr_rxBuffer(rxBuffer, 2);
386  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_CHECK_FMEA, mxm_41bState.state);
387 
388  /* check if the values are parsed correctly */
389  MXM_GetSPIStateReady_ExpectAndReturn(STD_OK);
391  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
392  TEST_ASSERT_EQUAL(MXM_41B_STATE_PROCESSED, status41b);
393 }
394 
396  /* force state-machine in check_fmea state */
398 
399  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_CHECK_FMEA, mxm_41bState.state);
400 
401  /* create a buffer with the assumed output of the ASCI and inject into SPI read */
402  /* simulate an GNDL Alert in FMEA register */
403  uint16_t rxBuffer[10] = {0x13u, 0x01u};
404  MXM_ReceiveData_ExpectAndReturn(mxm_41bState.spiTXBuffer, mxm_41bState.spiRXBuffer, 2, STD_OK);
405  MXM_ReceiveData_ReturnArrayThruPtr_rxBuffer(rxBuffer, 2);
407  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_CHECK_FMEA, mxm_41bState.state);
408 
409  /* check if the values are parsed correctly */
410  MXM_GetSPIStateReady_ExpectAndReturn(STD_OK);
412  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
413  TEST_ASSERT_EQUAL(MXM_41B_STATE_ERROR, status41b);
414 }
415 
417  /* force state-machine in get_version state */
419 
421 
422  /* create a buffer with the assumed output of the ASCI and inject into SPI read */
423  uint16_t rxBuffer[10] = {0x15u, 0x84u, 0x12u};
424  MXM_ReceiveData_ExpectAndReturn(mxm_41bState.spiTXBuffer, mxm_41bState.spiRXBuffer, 3, STD_OK);
425  MXM_ReceiveData_ReturnArrayThruPtr_rxBuffer(rxBuffer, 3);
428 
429  /* check if the values are parsed correctly */
430  MXM_GetSPIStateReady_ExpectAndReturn(STD_OK);
432  TEST_ASSERT_EQUAL(0x841u, mxm_41bState.hwModel);
433  TEST_ASSERT_EQUAL(0x2u, mxm_41bState.hwMaskRevision);
434 }
435 
437  /* force state-machine in clear_receive_buffer state */
439 
441 
442  /* create a buffer with the assumed input to the ASCI */
443  uint16_t tx_buffer[10] = {0xE0u};
444  MXM_SendData_ExpectAndReturn(tx_buffer, 1, STD_OK);
446 
447  /* check if the write was successful */
448  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
449  TEST_ASSERT_EQUAL(MXM_41B_STATE_PROCESSED, status41b);
450 }
451 
453  /* force state-machine in clear_receive_buffer state */
455 
457 
458  /* create a buffer with the assumed input to the ASCI */
459  uint16_t tx_buffer[10] = {0xE0u};
460  /* simulate a failure of writing */
461  MXM_SendData_ExpectAndReturn(tx_buffer, 1, STD_NOT_OK);
463 
464  /* check if the write was successful */
465  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
466  TEST_ASSERT_EQUAL(MXM_41B_STATE_ERROR, status41b);
467 }
468 
470  /* force state-machine in clear_transmit_buffer state */
472 
474 
475  /* create a buffer with the assumed input to the ASCI */
476  uint16_t tx_buffer[10] = {0x20u};
477  MXM_SendData_ExpectAndReturn(tx_buffer, 1, STD_OK);
479 
480  /* check if the write was successful */
481  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
482  TEST_ASSERT_EQUAL(MXM_41B_STATE_PROCESSED, status41b);
483 }
484 
486  /* force state-machine in clear_transmit_buffer state */
488 
490 
491  /* create a buffer with the assumed input to the ASCI */
492  uint16_t tx_buffer[10] = {0x20u};
493  /* simulate a failure of writing */
494  MXM_SendData_ExpectAndReturn(tx_buffer, 1, STD_NOT_OK);
496 
497  /* check if the write was successful */
498  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
499  TEST_ASSERT_EQUAL(MXM_41B_STATE_ERROR, status41b);
500 }
501 
503  /* force state-machine in MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_READ_AND_READ_BACK_RCV_BUF */
506  /* prepare RX buffer with not received RX_Stop_Status bit */
507  mxm_41bState.spiRXBuffer[1] = 0;
508 
509  /* transition */
511 
513 }
514 
516  /* force state-machine in MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_READ_AND_READ_BACK_RCV_BUF */
519  /* prepare RX buffer with received RX_Stop_Status bit */
520  mxm_41bState.spiRXBuffer[1] |= (0x01u << 1u);
521 
522  /* transition */
523  MXM_ReceiveData_IgnoreAndReturn(STD_OK);
525 
527 }
528 
529 void testStateDefault(void) {
530  /* force state-machine in invalid state */
533 
534  /* transition */
535  MXM_ReceiveData_IgnoreAndReturn(STD_OK);
537 }
538 
539 /** tests the normally to be expected flow through the initialization state */
541  /* force state-machine in init state */
543 
544  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_INIT, mxm_41bState.state);
545  TEST_ASSERT_EQUAL(MXM_41B_ENTRY_SUBSTATE, mxm_41bState.substate);
546 
547  /* first the bridge IC should be shut down */
548  MXM_ShutDownBridgeIc_Expect();
549  /* timestamp for the shutdown */
550  const uint32_t shutdownTimestamp = 42u;
551  OS_GetTickCount_ExpectAndReturn(shutdownTimestamp);
553 
554  /* next call the timestamp will be checked, simulate time is not up yet */
555  OS_CheckTimeHasPassed_ExpectAndReturn(shutdownTimestamp, 0u, false);
556  OS_CheckTimeHasPassed_IgnoreArg_timeToPass_ms();
558 
559  /* next call the timestamp will be checked again, simulate time is up */
560  OS_CheckTimeHasPassed_ExpectAndReturn(shutdownTimestamp, 0u, true);
561  OS_CheckTimeHasPassed_IgnoreArg_timeToPass_ms();
562  /* now the bridge IC should be reenabled */
563  MXM_EnableBridgeIc_Expect();
565 
566  /* now the default configuration should be sent to the bridge IC */
567  MXM_SendData_ExpectAndReturn(mxm_41bState.spiTXBuffer, 8, STD_OK);
569 
570  /* default values to check against */
571  const uint8_t mxm_41B_reg_default_values[MXM_41B_CONFIG_REGISTER_LENGTH] = {
579  MXM_ReceiveData_ExpectAndReturn(
582 
583  /* inject the values by copying into the pointer (can be done since we know the address) */
584  for (uint8_t i = 0u; i < MXM_41B_CONFIG_REGISTER_LENGTH; i++) {
585  mxm_41bState.spiRXBuffer[i + 1u] = mxm_41B_reg_default_values[i];
586  }
587 
588  MXM_GetSPIStateReady_ExpectAndReturn(STD_OK);
590 
591  /* and now we should be done and back in idle */
592  TEST_ASSERT_EQUAL(MXM_STATEMACH_41B_IDLE, mxm_41bState.state);
593  TEST_ASSERT_EQUAL(MXM_41B_ENTRY_SUBSTATE, mxm_41bState.substate);
594 }
595 
596 /** @}
597  * end tests for the state-machine */
@ STD_NOT_OK
Definition: fstd_types.h:83
@ STD_OK
Definition: fstd_types.h:82
#define NULL_PTR
Null pointer.
Definition: fstd_types.h:76
void testReadRegisterFunctionWithIllegalValues(void)
void testReadRegisterFunctionWithLegalValues(void)
void testStateRequestInconsistentInputPayload(void)
void testSetStateRequestInvalidInstancePointer(void)
Test with an invalid pointer.
void testTransitionsOnlyAllowedInIdleAfterInit(void)
void testStateRequestConsistentInput(void)
void testStateRequestInconsistentInputRXBuffer(void)
void testOnlyAllowedTransitionFromUnitializedIsInit(void)
Test that the only transition from uninitialized is initialization.
void testStateRequestInconsistentInputProcessed(void)
void testStateGetVersion(void)
void testStateClearTransmitBuffer(void)
void testStateDefault(void)
void testStateInitNormalFlow(void)
void testStateClearTransmitBufferFailedSPIWrite(void)
void testStateCheckFmeaGNDLAlert(void)
void testStateClearReceiveBufferFailedSPIWrite(void)
void testStateStayInIdle(void)
void testStateUARTWaitForRXStatusChangeFail(void)
void testStateStayInUninitialized(void)
void testStateClearReceiveBuffer(void)
void testStateCheckFMEA(void)
void testStateUARTWaitForRXStatusChangeSuccess(void)
void testWriteRegisterFunctionWithLegalValues(void)
void testWriteRegisterFunctionWithIllegalValues(void)
STD_RETURN_TYPE_e MXM_41BSetStateRequest(MXM_41B_INSTANCE_s *pInstance, MXM_STATEMACH_41B_e state, uint16_t *pPayload, uint8_t payloadLength, uint8_t extendMessageBytes, uint16_t *pRxBuffer, uint16_t rxBufferLength, MXM_41B_STATE_REQUEST_STATUS_e *processed)
Set state transition for MAX17841B-state-machine.
Definition: mxm_17841b.c:784
void MXM_41BStateMachine(MXM_41B_INSTANCE_s *pInstance)
Execute state-machine for the MAX17841B.
Definition: mxm_17841b.c:927
STD_RETURN_TYPE_e MXM_41BWriteRegisterFunction(MXM_41B_INSTANCE_s *pInstance, MXM_41B_REG_FUNCTION_e registerFunction, MXM_41B_REG_BIT_VALUE value)
Write a register function.
Definition: mxm_17841b.c:846
void MXM_41BInitializeStateStruct(MXM_41B_INSTANCE_s *pInstance)
Initializes the state struct with default values.
Definition: mxm_17841b.c:973
STD_RETURN_TYPE_e MXM_41BReadRegisterFunction(const MXM_41B_INSTANCE_s *const kpkInstance, MXM_41B_REG_FUNCTION_e registerFunction, MXM_41B_REG_BIT_VALUE *pValue)
Read the value of a register function.
Definition: mxm_17841b.c:892
Headers for the driver for the MAX17841B ASCI and MAX1785x monitoring chip.
@ MXM_STATEMACH_41B_MAXSTATE
Definition: mxm_17841b.h:95
@ MXM_STATEMACH_41B_GET_VERSION
Definition: mxm_17841b.h:89
@ MXM_STATEMACH_41B_CLEAR_RECEIVE_BUFFER
Definition: mxm_17841b.h:93
@ MXM_STATEMACH_41B_CLEAR_TRANSMIT_BUFFER
Definition: mxm_17841b.h:94
@ MXM_STATEMACH_41B_UNINITIALIZED
Definition: mxm_17841b.h:85
@ MXM_STATEMACH_41B_INIT
Definition: mxm_17841b.h:86
@ MXM_STATEMACH_41B_CHECK_FMEA
Definition: mxm_17841b.h:88
@ MXM_STATEMACH_41B_IDLE
Definition: mxm_17841b.h:87
@ MXM_STATEMACH_41B_UART_TRANSACTION
Definition: mxm_17841b.h:92
@ MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_WRITE
Definition: mxm_17841b.h:118
@ MXM_41B_UART_READ_BACK_RECEIVE_BUFFER_SAVE
Definition: mxm_17841b.h:120
@ MXM_41B_ENTRY_SUBSTATE
Definition: mxm_17841b.h:102
@ MXM_41B_UART_WAIT_FOR_RX_STATUS_CHANGE_READ_AND_READ_BACK_RCV_BUF
Definition: mxm_17841b.h:119
@ MXM_41B_REG_FUNCTION_RX_BUSY_STATUS
Definition: mxm_17841b.h:142
@ MXM_41B_REG_FUNCTION_RX_EMPTY_STATUS
Definition: mxm_17841b.h:145
@ MXM_41B_REG_FUNCTION_TX_PREAMBLES
Definition: mxm_17841b.h:146
@ MXM_41B_REG_FUNCTION_RX_ERROR_INT
Definition: mxm_17841b.h:148
@ MXM_41B_REG_FUNCTION_KEEP_ALIVE
Definition: mxm_17841b.h:147
@ MXM_41B_REG_FUNCTION_RX_OVERFLOW_INT
Definition: mxm_17841b.h:149
MXM_41B_STATE_REQUEST_STATUS_e
Request status of MAX17841B states.
Definition: mxm_17841b.h:131
@ MXM_41B_STATE_ERROR
Definition: mxm_17841b.h:135
@ MXM_41B_STATE_UNPROCESSED
Definition: mxm_17841b.h:133
@ MXM_41B_STATE_PROCESSED
Definition: mxm_17841b.h:134
Bit extraction function for MXM_17841b.
#define MXM_41B_REG_FALSE
uint8_t MXM_41B_REG_BIT_VALUE
Bit-values for registers.
#define MXM_41B_REG_KEEP_ALIVE_0US
#define MXM_41B_REG_TRUE
#define MXM_41B_REG_KEEP_ALIVE_10US
#define MXM_41B_REG_KEEP_ALIVE_640US
#define MXM_41B_REG_KEEP_ALIVE_INF_DLY
#define MXM_41B_CONFIG_3_DEFAULT_VALUE
Definition: mxm_cfg.h:104
#define MXM_41B_CONFIG_1_DEFAULT_VALUE
Definition: mxm_cfg.h:92
#define MXM_41B_CONFIG_2_DEFAULT_VALUE
Definition: mxm_cfg.h:98
#define MXM_41B_RX_INT_ENABLE_DEFAULT_VALUE
Definition: mxm_cfg.h:81
#define MXM_41B_RX_INT_FLAG_DEFAULT_VALUE
Definition: mxm_cfg.h:83
#define MXM_41B_TX_INT_ENABLE_DEFAULT_VALUE
Definition: mxm_cfg.h:82
#define MXM_41B_TX_INT_FLAG_DEFAULT_VALUE
Definition: mxm_cfg.h:84
Struct for the state-variable of state-machine.
Definition: mxm_17841b.h:158
uint8_t regRXIntEnable
Definition: mxm_17841b.h:168
uint8_t hwMaskRevision
Definition: mxm_17841b.h:178
MXM_41B_STATE_REQUEST_STATUS_e * processed
Definition: mxm_17841b.h:165
uint16_t spiRXBuffer[MXM_SPI_RX_BUFFER_LENGTH]
Definition: mxm_17841b.h:180
uint16_t spiTXBuffer[MXM_SPI_TX_BUFFER_LENGTH]
Definition: mxm_17841b.h:181
MXM_41B_SUBSTATES_e substate
Definition: mxm_17841b.h:160
MXM_STATEMACH_41B_e state
Definition: mxm_17841b.h:159
Helper for unit tests.
#define TEST_ASSERT_FAIL_ASSERT(_code_under_test)
assert whether assert macro has failed
uint16_t rxBuffer[100]
uint16_t commandBuffer[10]
#define MXM_41B_CONFIG_REGISTER_LENGTH
MXM_41B_STATE_REQUEST_STATUS_e status41b
static MXM_41B_INSTANCE_s mxm_41bState
void setUp(void)
void tearDown(void)